1 /* 2 * Copyright (c) 2022-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_BOARD_H 9 #define _HPM_BOARD_H 10 #include <stdio.h> 11 #include "hpm_common.h" 12 #include "hpm_clock_drv.h" 13 #include "hpm_soc.h" 14 #include "hpm_soc_feature.h" 15 #include "pinmux.h" 16 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 17 #include "hpm_debug_console.h" 18 #endif 19 20 #define BOARD_NAME "hpm6300evk" 21 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) 22 23 /* dma section */ 24 #define BOARD_APP_XDMA HPM_XDMA 25 #define BOARD_APP_HDMA HPM_HDMA 26 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 27 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 28 #define BOARD_APP_DMAMUX HPM_DMAMUX 29 30 #ifndef BOARD_RUNNING_CORE 31 #define BOARD_RUNNING_CORE HPM_CORE0 32 #endif 33 34 /* uart section */ 35 #ifndef BOARD_APP_UART_BASE 36 #define BOARD_APP_UART_BASE HPM_UART2 37 #define BOARD_APP_UART_IRQ IRQn_UART2 38 #define BOARD_APP_UART_BAUDRATE (115200UL) 39 #define BOARD_APP_UART_CLK_NAME clock_uart2 40 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX 41 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX 42 #endif 43 44 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 45 #ifndef BOARD_CONSOLE_TYPE 46 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART 47 #endif 48 49 #if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE 50 #ifndef BOARD_CONSOLE_UART_BASE 51 #if BOARD_RUNNING_CORE == HPM_CORE0 52 #define BOARD_CONSOLE_UART_BASE HPM_UART0 53 #define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 54 #define BOARD_CONSOLE_UART_IRQ IRQn_UART0 55 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX 56 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX 57 #else 58 #define BOARD_CONSOLE_UART_BASE HPM_UART13 59 #define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 60 #define BOARD_CONSOLE_UART_IRQ IRQn_UART13 61 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX 62 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX 63 #endif 64 #endif 65 #define BOARD_CONSOLE_UART_BAUDRATE (115200UL) 66 #endif 67 #endif 68 69 /* uart rx idle demo section */ 70 #define BOARD_UART_IDLE BOARD_APP_UART_BASE 71 #define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ 72 #define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME 73 #define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ 74 #define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ 75 76 #define BOARD_UART_IDLE_TRGM HPM_TRGM1 77 #define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PA24 78 #define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM1_INPUT_SRC_TRGM1_P4 79 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 80 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI 81 82 #define BOARD_UART_IDLE_GPTMR HPM_GPTMR2 83 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr2 84 #define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR2 85 #define BOARD_UART_IDLE_GPTMR_CMP_CH 0 86 #define BOARD_UART_IDLE_GPTMR_CAP_CH 2 87 88 /* uart lin sample section */ 89 #define BOARD_UART_LIN BOARD_APP_UART_BASE 90 #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ 91 #define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME 92 #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC 93 #define BOARD_UART_LIN_TX_PIN (26U) /* PC26 should align with used pin in pinmux configuration */ 94 95 /* uart microros sample section */ 96 #define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE 97 #define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ 98 #define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 99 100 /* rtthread-nano finsh section */ 101 #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE 102 103 /* usb cdc acm uart section */ 104 #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE 105 #define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 106 #define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ 107 #define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ 108 109 /* modbus sample section */ 110 #define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE 111 #define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 112 #define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ 113 #define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ 114 115 /* sdram section */ 116 #define BOARD_SDRAM_ADDRESS (0x40000000UL) 117 #define BOARD_SDRAM_SIZE (32 * SIZE_1MB) 118 #define BOARD_SDRAM_CS FEMC_SDRAM_CS0 119 #define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS 120 #define BOARD_SDRAM_REFRESH_COUNT (8192UL) 121 #define BOARD_SDRAM_REFRESH_IN_MS (64UL) 122 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) 123 124 /* nor flash section */ 125 #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) 126 #define BOARD_FLASH_SIZE (16 * SIZE_1MB) 127 128 /* i2c section */ 129 #define BOARD_APP_I2C_BASE HPM_I2C0 130 #define BOARD_APP_I2C_IRQ IRQn_I2C0 131 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 132 #define BOARD_APP_I2C_DMA HPM_HDMA 133 #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX 134 #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 135 #define BOARD_I2C_GPIO_CTRL HPM_GPIO0 136 #define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOC 137 #define BOARD_I2C_SCL_GPIO_PIN 13 138 #define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOC 139 #define BOARD_I2C_SDA_GPIO_PIN 14 140 141 /* ACMP desction */ 142 #define BOARD_ACMP HPM_ACMP 143 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 144 #define BOARD_ACMP_IRQ IRQn_ACMP_1 145 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ 146 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ 147 148 /* dma section */ 149 #define BOARD_APP_XDMA HPM_XDMA 150 #define BOARD_APP_HDMA HPM_HDMA 151 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 152 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 153 #define BOARD_APP_DMAMUX HPM_DMAMUX 154 155 /* gptmr section */ 156 #define BOARD_GPTMR HPM_GPTMR2 157 #define BOARD_GPTMR_IRQ IRQn_GPTMR2 158 #define BOARD_GPTMR_CHANNEL 0 159 #define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR2_0 160 #define BOARD_GPTMR_CLK_NAME clock_gptmr2 161 #define BOARD_GPTMR_PWM HPM_GPTMR2 162 #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR2_0 163 #define BOARD_GPTMR_PWM_CHANNEL 0 164 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr2 165 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR2 166 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR2 167 #define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 168 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr2 169 170 /* gpio section */ 171 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ 172 #define BOARD_APP_GPIO_PIN 2 173 174 /* pinmux section */ 175 #define USING_GPIO0_FOR_GPIOZ 176 #ifndef USING_GPIO0_FOR_GPIOZ 177 #define BOARD_APP_GPIO_CTRL HPM_BGPIO 178 #define BOARD_APP_GPIO_IRQ IRQn_BGPIO 179 #else 180 #define BOARD_APP_GPIO_CTRL HPM_GPIO0 181 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z 182 #endif 183 184 /* gpiom section */ 185 #define BOARD_APP_GPIOM_BASE HPM_GPIOM 186 #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO 187 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast 188 189 /* spi section */ 190 #define BOARD_APP_SPI_BASE HPM_SPI3 191 #define BOARD_APP_SPI_CLK_NAME clock_spi3 192 #define BOARD_APP_SPI_IRQ IRQn_SPI3 193 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) 194 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) 195 #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) 196 #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX 197 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX 198 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 199 #define BOARD_SPI_CS_PIN IOC_PAD_PC18 200 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) 201 202 /* Flash section */ 203 #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) 204 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) 205 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) 206 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) 207 208 /* i2s section */ 209 #define BOARD_APP_I2S_BASE HPM_I2S0 210 #define BOARD_APP_I2S_DATA_LINE (2U) 211 #define BOARD_APP_I2S_CLK_NAME clock_i2s0 212 #define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 213 #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 214 215 /* enet section */ 216 #define BOARD_ENET_PPS HPM_ENET0 217 #define BOARD_ENET_PPS_IDX enet_pps_0 218 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 219 220 #define BOARD_ENET_RMII HPM_ENET0 221 #define BOARD_ENET_RMII_RST_GPIO 222 #define BOARD_ENET_RMII_RST_GPIO_INDEX 223 #define BOARD_ENET_RMII_RST_GPIO_PIN 224 #define BOARD_ENET_RMII HPM_ENET0 225 #define BOARD_ENET_RMII_INT_REF_CLK (1U) 226 #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) 227 #define BOARD_ENET_RMII_PPS0_PINOUT (1) 228 229 #define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ 230 #define BOARD_ENET0_INT_REF_CLK (1U) 231 #define BOARD_ENET0_PHY_RST_TIME (30) 232 233 #if BOARD_ENET0_INF 234 #define BOARD_ENET0_TX_DLY (0U) 235 #define BOARD_ENET0_RX_DLY (0U) 236 #endif 237 238 #if __USE_ENET_PTP 239 #define BOARD_ENET0_PTP_CLOCK (clock_ptp0) 240 #endif 241 242 243 /* ADC section */ 244 #define BOARD_APP_ADC16_NAME "ADC0" 245 #define BOARD_APP_ADC16_BASE HPM_ADC0 246 #define BOARD_APP_ADC16_IRQn IRQn_ADC0 247 #define BOARD_APP_ADC16_CH_1 (6U) 248 #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) 249 250 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 251 #define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 252 #define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 253 #define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI 254 #define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 255 256 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A 257 258 /* DAC section */ 259 #define BOARD_DAC_BASE HPM_DAC 260 #define BOARD_DAC_IRQn IRQn_DAC 261 #define BOARD_APP_DAC_CLOCK_NAME clock_dac0 262 263 /* CAN section */ 264 #define BOARD_APP_CAN_BASE HPM_CAN1 265 #define BOARD_APP_CAN_IRQn IRQn_CAN1 266 267 /* 268 * timer for board delay 269 */ 270 #define BOARD_DELAY_TIMER (HPM_GPTMR3) 271 #define BOARD_DELAY_TIMER_CH 0 272 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) 273 274 #define BOARD_CALLBACK_TIMER (HPM_GPTMR3) 275 #define BOARD_CALLBACK_TIMER_CH 1 276 #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 277 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) 278 279 /* SDXC section */ 280 #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) 281 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) 282 #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) 283 #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) 284 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 285 #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC0) 286 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) 287 #define BOARD_APP_EMMC_SUPPORT_1V8 (0) 288 #define BOARD_APP_EMMC_SUPPORT_4BIT (1) 289 #define BOARD_APP_EMMC_HOST_USING_IRQ (0) 290 291 /* USB section */ 292 #define BOARD_USB0_ID_PORT (HPM_GPIO0) 293 #define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC) 294 #define BOARD_USB0_ID_GPIO_PIN (23) 295 296 /*BLDC pwm*/ 297 298 /*PWM define*/ 299 #define BOARD_BLDCPWM HPM_PWM0 300 #define BOARD_BLDC_UH_PWM_OUTPIN (0U) 301 #define BOARD_BLDC_UL_PWM_OUTPIN (1U) 302 #define BOARD_BLDC_VH_PWM_OUTPIN (2U) 303 #define BOARD_BLDC_VL_PWM_OUTPIN (3U) 304 #define BOARD_BLDC_WH_PWM_OUTPIN (4U) 305 #define BOARD_BLDC_WL_PWM_OUTPIN (5U) 306 #define BOARD_BLDCPWM_TRGM HPM_TRGM0 307 #define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 308 #define BOARD_BLDCPWM_CMP_INDEX_0 (0U) 309 #define BOARD_BLDCPWM_CMP_INDEX_1 (1U) 310 #define BOARD_BLDCPWM_CMP_INDEX_2 (2U) 311 #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) 312 #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) 313 #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) 314 #define BOARD_BLDCPWM_CMP_INDEX_6 (6U) 315 #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) 316 #define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) 317 318 /*HALL define*/ 319 320 #define BOARD_BLDC_HALL_BASE HPM_HALL0 321 #define BOARD_BLDC_HALL_TRGM HPM_TRGM0 322 #define BOARD_BLDC_HALL_IRQ IRQn_HALL0 323 #define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 324 #define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 325 #define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 326 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) 327 328 /*QEI*/ 329 330 #define BOARD_BLDC_QEI_BASE HPM_QEI0 331 #define BOARD_BLDC_QEI_IRQ IRQn_QEI0 332 #define BOARD_BLDC_QEI_TRGM HPM_TRGM0 333 #define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P9 334 #define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P10 335 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) 336 #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 337 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) 338 339 /*Timer define*/ 340 341 #define BOARD_BLDC_TMR_1MS HPM_GPTMR2 342 #define BOARD_BLDC_TMR_CH 0 343 #define BOARD_BLDC_TMR_CMP 0 344 #define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 345 #define BOARD_BLDC_TMR_RELOAD (100000U) 346 347 /*adc*/ 348 #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 349 #define BOARD_BLDC_ADC_U_BASE HPM_ADC1 350 #define BOARD_BLDC_ADC_V_BASE HPM_ADC0 351 #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 352 #define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete 353 354 #define BOARD_BLDC_ADC_CH_U (7U) 355 #define BOARD_BLDC_ADC_CH_V (12U) 356 #define BOARD_BLDC_ADC_CH_W (5U) 357 #define BOARD_BLDC_ADC_IRQn IRQn_ADC1 358 #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) 359 #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A 360 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) 361 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) 362 #define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 363 #define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A 364 365 /* APP PWM */ 366 #define BOARD_APP_PWM HPM_PWM0 367 #define BOARD_APP_PWM_CLOCK_NAME clock_mot0 368 #define BOARD_APP_PWM_OUT1 0 369 #define BOARD_APP_PWM_OUT2 1 370 #define BOARD_APP_TRGM HPM_TRGM0 371 #define BOARD_APP_PWM_IRQ IRQn_PWM0 372 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI 373 374 #define BOARD_CPU_FREQ (480000000UL) 375 376 /* LED */ 377 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 378 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA 379 #define BOARD_LED_GPIO_PIN 7 380 #define BOARD_LED_OFF_LEVEL 1 381 #define BOARD_LED_ON_LEVEL 0 382 383 #ifndef BOARD_SHOW_CLOCK 384 #define BOARD_SHOW_CLOCK 1 385 #endif 386 #ifndef BOARD_SHOW_BANNER 387 #define BOARD_SHOW_BANNER 1 388 #endif 389 390 /* FreeRTOS Definitions */ 391 #define BOARD_FREERTOS_TIMER HPM_GPTMR1 392 #define BOARD_FREERTOS_TIMER_CHANNEL 1 393 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 394 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 395 396 /* Threadx Definitions */ 397 #define BOARD_THREADX_TIMER HPM_GPTMR1 398 #define BOARD_THREADX_TIMER_CHANNEL 1 399 #define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 400 #define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 401 /* Tamper Section */ 402 #define BOARD_TAMP_NO_LEVEL_PINS 403 #define BOARD_TAMP_ACTIVE_CH 6 404 405 #if defined(__cplusplus) 406 extern "C" { 407 #endif /* __cplusplus */ 408 409 typedef void (*board_timer_cb)(void); 410 411 void board_init(void); 412 void board_init_console(void); 413 414 void board_init_uart(UART_Type *ptr); 415 void board_init_i2c(I2C_Type *ptr); 416 417 void board_init_can(CAN_Type *ptr); 418 419 uint32_t board_init_femc_clock(void); 420 421 void board_init_sdram_pins(void); 422 void board_init_gpio_pins(void); 423 void board_init_spi_pins(SPI_Type *ptr); 424 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); 425 void board_write_spi_cs(uint32_t pin, uint8_t state); 426 void board_init_led_pins(void); 427 428 void board_led_write(uint8_t state); 429 void board_led_toggle(void); 430 431 /* Initialize SoC overall clocks */ 432 void board_init_clock(void); 433 434 uint32_t board_init_spi_clock(SPI_Type *ptr); 435 436 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); 437 438 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); 439 440 void board_init_adc16_pins(void); 441 442 void board_init_dac_pins(DAC_Type *ptr); 443 444 uint32_t board_init_can_clock(CAN_Type *ptr); 445 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); 446 uint32_t board_init_i2s_clock(I2S_Type *ptr); 447 uint32_t board_init_pdm_clock(void); 448 uint32_t board_init_dao_clock(void); 449 450 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); 451 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); 452 bool board_sd_detect_card(SDXC_Type *ptr); 453 454 void board_init_usb_pins(void); 455 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); 456 uint8_t board_get_usb_id_status(void); 457 458 void board_init_enet_pps_pins(ENET_Type *ptr); 459 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); 460 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); 461 hpm_stat_t board_init_enet_pins(ENET_Type *ptr); 462 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); 463 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); 464 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); 465 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); 466 /* 467 * @brief Initialize PMP and PMA for but not limited to the following purposes: 468 * -- non-cacheable memory initialization 469 */ 470 void board_init_pmp(void); 471 472 void board_delay_us(uint32_t us); 473 void board_delay_ms(uint32_t ms); 474 475 void board_timer_create(uint32_t ms, board_timer_cb cb); 476 void board_ungate_mchtmr_at_lp_mode(void); 477 478 /* Initialize the UART clock */ 479 uint32_t board_init_uart_clock(UART_Type *ptr); 480 481 uint32_t board_init_pwm_clock(PWM_Type *ptr); 482 483 /* 484 * Get GPIO pin level of onboard LED 485 */ 486 uint8_t board_get_led_gpio_off_level(void); 487 488 void board_sd_power_switch(SDXC_Type *ptr, bool on_off); 489 #if defined(__cplusplus) 490 } 491 #endif /* __cplusplus */ 492 #endif /* _HPM_BOARD_H */ 493