1# Copyright 2021 hpmicro
2# SPDX-License-Identifier: BSD-3-Clause
3
4flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
5
6proc init_clock {} {
7    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
8    $::_TARGET0 riscv dmi_write 0x3C 0x1
9
10    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
11    $::_TARGET0 riscv dmi_write 0x3C 0x2
12
13    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
14    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
15
16    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
17    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
18
19    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
20    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
21
22    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
23    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
24    echo "clocks has been enabled!"
25}
26
27proc init_sdram { } {
28# configure dram frequency
29# 133Mhz pll1_clk0: 266Mhz divide by 2
30    #$::_TARGET0 riscv dmi_write 0x39 0xF4001820
31    $::_TARGET0 riscv dmi_write 0x3C 0x201
32# 166Mhz pll2_clk0: 333Mhz divide by 2
33    $::_TARGET0 riscv dmi_write 0x39 0xF4001820
34    $::_TARGET0 riscv dmi_write 0x3C 0x401
35
36    # PD13
37    $::_TARGET0 riscv dmi_write 0x39 0xF4040368
38    $::_TARGET0 riscv dmi_write 0x3C 0xC
39    # PD12
40    $::_TARGET0 riscv dmi_write 0x39 0xF4040360
41    $::_TARGET0 riscv dmi_write 0x3C 0xC
42    # PD10
43    $::_TARGET0 riscv dmi_write 0x39 0xF4040350
44    $::_TARGET0 riscv dmi_write 0x3C 0xC
45    # PD09
46    $::_TARGET0 riscv dmi_write 0x39 0xF4040348
47    $::_TARGET0 riscv dmi_write 0x3C 0xC
48    # PD08
49    $::_TARGET0 riscv dmi_write 0x39 0xF4040340
50    $::_TARGET0 riscv dmi_write 0x3C 0xC
51    # PD07
52    $::_TARGET0 riscv dmi_write 0x39 0xF4040338
53    $::_TARGET0 riscv dmi_write 0x3C 0xC
54    # PD06
55    $::_TARGET0 riscv dmi_write 0x39 0xF4040330
56    $::_TARGET0 riscv dmi_write 0x3C 0xC
57    # PD05
58    $::_TARGET0 riscv dmi_write 0x39 0xF4040328
59    $::_TARGET0 riscv dmi_write 0x3C 0xC
60    # PD04
61    $::_TARGET0 riscv dmi_write 0x39 0xF4040320
62    $::_TARGET0 riscv dmi_write 0x3C 0xC
63    # PD03
64    $::_TARGET0 riscv dmi_write 0x39 0xF4040318
65    $::_TARGET0 riscv dmi_write 0x3C 0xC
66    # PD02
67    $::_TARGET0 riscv dmi_write 0x39 0xF4040310
68    $::_TARGET0 riscv dmi_write 0x3C 0xC
69    # PD01
70    $::_TARGET0 riscv dmi_write 0x39 0xF4040308
71    $::_TARGET0 riscv dmi_write 0x3C 0xC
72    # PD00
73    $::_TARGET0 riscv dmi_write 0x39 0xF4040300
74    $::_TARGET0 riscv dmi_write 0x3C 0xC
75    # PC29
76    $::_TARGET0 riscv dmi_write 0x39 0xF40402E8
77    $::_TARGET0 riscv dmi_write 0x3C 0xC
78    # PC28
79    $::_TARGET0 riscv dmi_write 0x39 0xF40402E0
80    $::_TARGET0 riscv dmi_write 0x3C 0xC
81    # PC27
82    $::_TARGET0 riscv dmi_write 0x39 0xF40402D8
83    $::_TARGET0 riscv dmi_write 0x3C 0xC
84
85    # PC22
86    $::_TARGET0 riscv dmi_write 0x39 0xF40402B0
87    $::_TARGET0 riscv dmi_write 0x3C 0xC
88    # PC21
89    $::_TARGET0 riscv dmi_write 0x39 0xF40402A8
90    $::_TARGET0 riscv dmi_write 0x3C 0xC
91    # PC17
92    $::_TARGET0 riscv dmi_write 0x39 0xF4040288
93    $::_TARGET0 riscv dmi_write 0x3C 0xC
94    # PC15
95    $::_TARGET0 riscv dmi_write 0x39 0xF4040278
96    $::_TARGET0 riscv dmi_write 0x3C 0xC
97    # PC12
98    $::_TARGET0 riscv dmi_write 0x39 0xF4040260
99    $::_TARGET0 riscv dmi_write 0x3C 0xC
100    # PC11
101    $::_TARGET0 riscv dmi_write 0x39 0xF4040258
102    $::_TARGET0 riscv dmi_write 0x3C 0xC
103    # PC10
104    $::_TARGET0 riscv dmi_write 0x39 0xF4040250
105    $::_TARGET0 riscv dmi_write 0x3C 0xC
106    # PC09
107    $::_TARGET0 riscv dmi_write 0x39 0xF4040248
108    $::_TARGET0 riscv dmi_write 0x3C 0xC
109    # PC08
110    $::_TARGET0 riscv dmi_write 0x39 0xF4040240
111    $::_TARGET0 riscv dmi_write 0x3C 0xC
112    # PC07
113    $::_TARGET0 riscv dmi_write 0x39 0xF4040238
114    $::_TARGET0 riscv dmi_write 0x3C 0xC
115    # PC06
116    $::_TARGET0 riscv dmi_write 0x39 0xF4040230
117    $::_TARGET0 riscv dmi_write 0x3C 0xC
118    # PC05
119    $::_TARGET0 riscv dmi_write 0x39 0xF4040228
120    $::_TARGET0 riscv dmi_write 0x3C 0xC
121    # PC04
122    $::_TARGET0 riscv dmi_write 0x39 0xF4040220
123    $::_TARGET0 riscv dmi_write 0x3C 0xC
124
125    # PC14
126    $::_TARGET0 riscv dmi_write 0x39 0xF4040270
127    $::_TARGET0 riscv dmi_write 0x3C 0xC
128    # PC13
129    $::_TARGET0 riscv dmi_write 0x39 0xF4040268
130    $::_TARGET0 riscv dmi_write 0x3C 0xC
131    # PC16
132    # $::_TARGET0 riscv dmi_write 0x39 0xF4040280
133    $::_TARGET0 riscv dmi_write 0x3C 0x1000C
134    # PC26
135    $::_TARGET0 riscv dmi_write 0x39 0xF40402D0
136    $::_TARGET0 riscv dmi_write 0x3C 0xC
137    # PC25
138    $::_TARGET0 riscv dmi_write 0x39 0xF40402C8
139    $::_TARGET0 riscv dmi_write 0x3C 0xC
140    # PC19
141    $::_TARGET0 riscv dmi_write 0x39 0xF4040298
142    $::_TARGET0 riscv dmi_write 0x3C 0xC
143    # PC18
144    $::_TARGET0 riscv dmi_write 0x39 0xF4040290
145    $::_TARGET0 riscv dmi_write 0x3C 0xC
146    # PC23
147    $::_TARGET0 riscv dmi_write 0x39 0xF40402B8
148    $::_TARGET0 riscv dmi_write 0x3C 0xC
149    # PC24
150    $::_TARGET0 riscv dmi_write 0x39 0xF40402C0
151    $::_TARGET0 riscv dmi_write 0x3C 0xC
152    # PC30
153    $::_TARGET0 riscv dmi_write 0x39 0xF40402F0
154    $::_TARGET0 riscv dmi_write 0x3C 0xC
155    # PC31
156    $::_TARGET0 riscv dmi_write 0x39 0xF40402F8
157    $::_TARGET0 riscv dmi_write 0x3C 0xC
158    # PC02
159    $::_TARGET0 riscv dmi_write 0x39 0xF4040210
160    $::_TARGET0 riscv dmi_write 0x3C 0xC
161    # PC03
162    $::_TARGET0 riscv dmi_write 0x39 0xF4040218
163    $::_TARGET0 riscv dmi_write 0x3C 0xC
164
165    # dramc configuration
166    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
167    $::_TARGET0 riscv dmi_write 0x3C 0x1
168    sleep 10
169    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
170    $::_TARGET0 riscv dmi_write 0x3C 0x2
171    $::_TARGET0 riscv dmi_write 0x39 0xF3050008
172    $::_TARGET0 riscv dmi_write 0x3C 0x30524
173    $::_TARGET0 riscv dmi_write 0x39 0xF305000C
174    $::_TARGET0 riscv dmi_write 0x3C 0x6030524
175    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
176    $::_TARGET0 riscv dmi_write 0x3C 0x10000000
177
178    # 32MB
179    $::_TARGET0 riscv dmi_write 0x39 0xF3050010
180    $::_TARGET0 riscv dmi_write 0x3C 0x4000001b
181    $::_TARGET0 riscv dmi_write 0x39 0xF3050014
182    $::_TARGET0 riscv dmi_write 0x3C 0
183    # 16-bit
184    $::_TARGET0 riscv dmi_write 0x39 0xF3050040
185    $::_TARGET0 riscv dmi_write 0x3C 0xf31
186
187    # 133Mhz configuration
188    #$::_TARGET0 riscv dmi_write 0x39 0xF3050044
189    $::_TARGET0 riscv dmi_write 0x3C 0x884e22
190    # 166Mhz configuration
191    $::_TARGET0 riscv dmi_write 0x39 0xF3050044
192    $::_TARGET0 riscv dmi_write 0x3C 0x884e33
193
194    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
195    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
196    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
197    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
198    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
199    $::_TARGET0 riscv dmi_write 0x3C 0x2020300
200
201    # config delay cell
202    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
203    $::_TARGET0 riscv dmi_write 0x3C 0x3b
204    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
205    $::_TARGET0 riscv dmi_write 0x3C 0x203b
206
207    $::_TARGET0 riscv dmi_write 0x39 0xF3050094
208    $::_TARGET0 riscv dmi_write 0x3C 0
209    $::_TARGET0 riscv dmi_write 0x39 0xF3050098
210    $::_TARGET0 riscv dmi_write 0x3C 0
211
212    # precharge all
213    $::_TARGET0 riscv dmi_write 0x39 0xF3050090
214    $::_TARGET0 riscv dmi_write 0x3C 0x40000000
215    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
216    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
217    sleep 500
218    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
219    $::_TARGET0 riscv dmi_write 0x3C 0x3
220    # auto refresh
221    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
222    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
223    sleep 500
224    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
225    $::_TARGET0 riscv dmi_write 0x3C 0x3
226    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
227    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
228    sleep 500
229    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
230    $::_TARGET0 riscv dmi_write 0x3C 0x3
231
232    # set mode
233    $::_TARGET0 riscv dmi_write 0x39 0xF30500A0
234    $::_TARGET0 riscv dmi_write 0x3C 0x33
235    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
236    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
237    sleep 500
238    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
239    $::_TARGET0 riscv dmi_write 0x3C 0x3
240
241    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
242    $::_TARGET0 riscv dmi_write 0x3C 0x2020301
243    echo "SDRAM has been initialized"
244}
245
246$_TARGET0 configure -event reset-init {
247    init_clock
248    init_sdram
249}
250
251$_TARGET0 configure -event gdb-attach {
252    reset halt
253}
254