1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_BOARD_H 9 #define _HPM_BOARD_H 10 #include <stdio.h> 11 #include "hpm_common.h" 12 #include "hpm_clock_drv.h" 13 #include "hpm_soc.h" 14 #include "hpm_soc_feature.h" 15 #include "pinmux.h" 16 #include "hpm_lcdc_drv.h" 17 #include "hpm_trgm_drv.h" 18 #ifdef CONFIG_HPM_PANEL 19 #include "hpm_panel.h" 20 #endif 21 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 22 #include "hpm_debug_console.h" 23 #endif 24 25 #define BOARD_NAME "hpm6750evk" 26 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) 27 28 #define SEC_CORE_IMG_START ILM_LOCAL_BASE 29 30 #ifndef BOARD_RUNNING_CORE 31 #define BOARD_RUNNING_CORE HPM_CORE0 32 #endif 33 34 /* uart section */ 35 #ifndef BOARD_APP_UART_BASE 36 #define BOARD_APP_UART_BASE HPM_UART13 37 #define BOARD_APP_UART_IRQ IRQn_UART13 38 #define BOARD_APP_UART_BAUDRATE (115200UL) 39 #define BOARD_APP_UART_CLK_NAME clock_uart13 40 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX 41 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX 42 #endif 43 44 /* uart rx idle demo section */ 45 #define BOARD_UART_IDLE BOARD_APP_UART_BASE 46 #define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ 47 #define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME 48 #define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ 49 #define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ 50 51 #define BOARD_UART_IDLE_TRGM HPM_TRGM2 52 #define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 53 #define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 54 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 55 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI 56 57 #define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 58 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 59 #define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 60 #define BOARD_UART_IDLE_GPTMR_CMP_CH 0 61 #define BOARD_UART_IDLE_GPTMR_CAP_CH 2 62 63 /* uart microros sample section */ 64 #define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE 65 #define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ 66 #define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 67 68 /* rtthread-nano finsh section */ 69 #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE 70 71 /* usb cdc acm uart section */ 72 #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE 73 #define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 74 #define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ 75 #define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ 76 77 /* modbus sample section */ 78 #define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE 79 #define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 80 #define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ 81 #define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ 82 83 /* uart lin sample section */ 84 #define BOARD_UART_LIN BOARD_APP_UART_BASE 85 #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ 86 #define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME 87 #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ 88 #define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ 89 90 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 91 #ifndef BOARD_CONSOLE_TYPE 92 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART 93 #endif 94 95 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART 96 #ifndef BOARD_CONSOLE_UART_BASE 97 #if BOARD_RUNNING_CORE == HPM_CORE0 98 #define BOARD_CONSOLE_UART_BASE HPM_UART0 99 #define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 100 #define BOARD_CONSOLE_UART_IRQ IRQn_UART0 101 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX 102 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX 103 #else 104 #define BOARD_CONSOLE_UART_BASE HPM_UART13 105 #define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 106 #define BOARD_CONSOLE_UART_IRQ IRQn_UART13 107 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX 108 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX 109 #endif 110 #endif 111 #define BOARD_CONSOLE_UART_BAUDRATE (115200UL) 112 #endif 113 #endif 114 115 /* sdram section */ 116 #define BOARD_SDRAM_ADDRESS (0x40000000UL) 117 #define BOARD_SDRAM_SIZE (32 * SIZE_1MB) 118 #define BOARD_SDRAM_CS FEMC_SDRAM_CS0 119 #define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS 120 #define BOARD_SDRAM_REFRESH_COUNT (8192UL) 121 #define BOARD_SDRAM_REFRESH_IN_MS (64UL) 122 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) 123 124 #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) 125 #define BOARD_FLASH_SIZE (16 << 20) 126 127 #define BOARD_FEMC_DQS_FLOATING 1 128 129 /* lcd section */ 130 #define BOARD_LCD_BASE HPM_LCDC 131 #define BOARD_LCD_IRQ IRQn_LCDC_D0 132 #define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 133 #define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB 134 #define BOARD_LCD_POWER_GPIO_PIN 16 135 #define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 136 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB 137 #define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 138 139 /* i2c section */ 140 #define BOARD_APP_I2C_BASE HPM_I2C0 141 #define BOARD_APP_I2C_IRQ IRQn_I2C0 142 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 143 #define BOARD_APP_I2C_DMA HPM_HDMA 144 #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX 145 #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 146 147 #define BOARD_CAM_I2C_BASE HPM_I2C0 148 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 149 #define BOARD_SUPPORT_CAM_RESET 150 #define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 151 #define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY 152 #define BOARD_CAM_RST_GPIO_PIN 5 153 154 #define BOARD_CAP_I2C_BASE (HPM_I2C0) 155 #define BOARD_CAP_I2C_CLK_NAME clock_i2c0 156 #define BOARD_CAP_RST_GPIO (HPM_GPIO0) 157 #define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) 158 #define BOARD_CAP_RST_GPIO_PIN (9) 159 #define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) 160 #define BOARD_CAP_INTR_GPIO (HPM_GPIO0) 161 #define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) 162 #define BOARD_CAP_INTR_GPIO_PIN (8) 163 #define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) 164 #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) 165 #define BOARD_CAP_I2C_SDA_GPIO_PIN (10) 166 #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) 167 #define BOARD_CAP_I2C_CLK_GPIO_PIN (11) 168 169 /* ACMP desction */ 170 #define BOARD_ACMP HPM_ACMP 171 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 172 #define BOARD_ACMP_IRQ IRQn_ACMP_1 173 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ 174 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ 175 176 /* dma section */ 177 #define BOARD_APP_XDMA HPM_XDMA 178 #define BOARD_APP_HDMA HPM_HDMA 179 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 180 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 181 #define BOARD_APP_DMAMUX HPM_DMAMUX 182 183 /* gptmr section */ 184 #define BOARD_GPTMR HPM_GPTMR4 185 #define BOARD_GPTMR_IRQ IRQn_GPTMR4 186 #define BOARD_GPTMR_CHANNEL 1 187 #define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_1 188 #define BOARD_GPTMR_CLK_NAME clock_gptmr4 189 #define BOARD_GPTMR_PWM HPM_GPTMR5 190 #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_2 191 #define BOARD_GPTMR_PWM_CHANNEL 2 192 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 193 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 194 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 195 #define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 196 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 197 198 /* gpio section */ 199 #define BOARD_R_GPIO_CTRL HPM_GPIO0 200 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB 201 #define BOARD_R_GPIO_PIN 11 202 #define BOARD_G_GPIO_CTRL HPM_GPIO0 203 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB 204 #define BOARD_G_GPIO_PIN 12 205 #define BOARD_B_GPIO_CTRL HPM_GPIO0 206 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB 207 #define BOARD_B_GPIO_PIN 13 208 209 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 210 211 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB 212 #define BOARD_LED_GPIO_PIN 12 213 #define BOARD_LED_OFF_LEVEL 1 214 #define BOARD_LED_ON_LEVEL 0 215 216 #define BOARD_LED_TOGGLE_RGB 1 217 218 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ 219 #define BOARD_APP_GPIO_PIN 2 220 221 /* pinmux section */ 222 #define USING_GPIO0_FOR_GPIOZ 223 #ifndef USING_GPIO0_FOR_GPIOZ 224 #define BOARD_APP_GPIO_CTRL HPM_BGPIO 225 #define BOARD_APP_GPIO_IRQ IRQn_BGPIO 226 #else 227 #define BOARD_APP_GPIO_CTRL HPM_GPIO0 228 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z 229 #endif 230 231 /* gpiom section */ 232 #define BOARD_APP_GPIOM_BASE HPM_GPIOM 233 #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO 234 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast 235 236 /* spi section */ 237 #define BOARD_APP_SPI_BASE HPM_SPI2 238 #define BOARD_APP_SPI_CLK_NAME clock_spi2 239 #define BOARD_APP_SPI_IRQ IRQn_SPI2 240 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) 241 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) 242 #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) 243 #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX 244 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX 245 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 246 #define BOARD_SPI_CS_PIN IOC_PAD_PE31 247 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) 248 249 /* Flash section */ 250 #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) 251 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) 252 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) 253 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) 254 255 /* lcd section */ 256 257 #ifndef BOARD_LCD_WIDTH 258 #define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH 259 #endif 260 #ifndef BOARD_LCD_HEIGHT 261 #define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT 262 #endif 263 264 /* pdma section */ 265 #define BOARD_PDMA_BASE HPM_PDMA 266 267 /* i2s section */ 268 #define BOARD_APP_I2S_BASE HPM_I2S0 269 #define BOARD_APP_I2S_DATA_LINE (2U) 270 #define BOARD_APP_I2S_CLK_NAME clock_i2s0 271 #define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX 272 #define BOARD_APP_I2S_IRQ IRQn_I2S0 273 #define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 274 #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 275 #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) 276 #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) 277 278 /* enet section */ 279 #define BOARD_ENET_COUNT (2U) 280 #define BOARD_ENET_PPS HPM_ENET0 281 #define BOARD_ENET_PPS_IDX enet_pps_0 282 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 283 284 #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii 285 #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 286 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF 287 #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) 288 #define BOARD_ENET_RGMII HPM_ENET0 289 #define BOARD_ENET_RGMII_TX_DLY (0U) 290 #define BOARD_ENET_RGMII_RX_DLY (23U) 291 #define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 292 #define BOARD_ENET_RGMII_PPS0_PINOUT (1) 293 294 #define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii 295 #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 296 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE 297 #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) 298 #define BOARD_ENET_RMII HPM_ENET1 299 #define BOARD_ENET_RMII_INT_REF_CLK (1U) 300 #define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 301 #define BOARD_ENET_RMII_PPS0_PINOUT (0) 302 303 #define BOARD_ENET0_RST_GPIO HPM_GPIO0 304 #define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF 305 #define BOARD_ENET0_RST_GPIO_PIN (0U) 306 #define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ 307 #define BOARD_ENET0_INT_REF_CLK (0U) 308 #define BOARD_ENET0_PHY_RST_TIME (30) 309 #if BOARD_ENET0_INF 310 #define BOARD_ENET0_TX_DLY (0U) 311 #define BOARD_ENET0_RX_DLY (21U) 312 #endif 313 #if __USE_ENET_PTP 314 #define BOARD_ENET0_PTP_CLOCK (clock_ptp0) 315 #endif 316 317 #define BOARD_ENET1_RST_GPIO HPM_GPIO0 318 #define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE 319 #define BOARD_ENET1_RST_GPIO_PIN (26U) 320 321 #define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ 322 #define BOARD_ENET1_INT_REF_CLK (1U) 323 #define BOARD_ENET1_PHY_RST_TIME (30) 324 325 #if BOARD_ENET1_INF 326 #define BOARD_ENET1_TX_DLY (0U) 327 #define BOARD_ENET1_RX_DLY (0U) 328 #endif 329 330 #if __USE_ENET_PTP 331 #define BOARD_ENET1_PTP_CLOCK (clock_ptp1) 332 #endif 333 334 /* ADC section */ 335 #define BOARD_APP_ADC12_NAME "ADC0" 336 #define BOARD_APP_ADC12_BASE HPM_ADC0 337 #define BOARD_APP_ADC12_IRQn IRQn_ADC0 338 #define BOARD_APP_ADC12_CH_1 (11U) 339 #define BOARD_APP_ADC12_CLK_NAME (clock_adc0) 340 341 #define BOARD_APP_ADC16_NAME "ADC3" 342 #define BOARD_APP_ADC16_BASE HPM_ADC3 343 #define BOARD_APP_ADC16_IRQn IRQn_ADC3 344 #define BOARD_APP_ADC16_CH_1 (2U) 345 #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) 346 347 #define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 348 #define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 349 #define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 350 #define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI 351 #define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 352 353 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 354 #define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 355 #define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 356 #define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI 357 #define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 358 359 #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A 360 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A 361 362 /* CAN section */ 363 #define BOARD_APP_CAN_BASE HPM_CAN0 364 #define BOARD_APP_CAN_IRQn IRQn_CAN0 365 366 /* 367 * timer for board delay 368 */ 369 #define BOARD_DELAY_TIMER (HPM_GPTMR7) 370 #define BOARD_DELAY_TIMER_CH 0 371 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) 372 373 #define BOARD_CALLBACK_TIMER (HPM_GPTMR7) 374 #define BOARD_CALLBACK_TIMER_CH 1 375 #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 376 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) 377 378 /* SDXC section */ 379 #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) 380 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) 381 #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) 382 #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) 383 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 384 #define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (0) 385 #define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (0) 386 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 387 #define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) 388 #if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) 389 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 390 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ 391 #endif 392 393 #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) 394 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) 395 #define BOARD_APP_EMMC_SUPPORT_1V8 (0) 396 #define BOARD_APP_EMMC_SUPPORT_4BIT (1) 397 #define BOARD_APP_EMMC_HOST_USING_IRQ (0) 398 399 /* USB section */ 400 #define BOARD_USB0_ID_PORT (HPM_GPIO0) 401 #define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) 402 #define BOARD_USB0_ID_GPIO_PIN (10) 403 404 #define BOARD_USB0_OC_PORT (HPM_GPIO0) 405 #define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) 406 #define BOARD_USB0_OC_GPIO_PIN (8) 407 408 #define BOARD_USB1_ID_PORT (HPM_GPIO0) 409 #define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) 410 #define BOARD_USB1_ID_GPIO_PIN (7) 411 412 #define BOARD_USB1_OC_PORT (HPM_GPIO0) 413 #define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) 414 #define BOARD_USB1_OC_GPIO_PIN (5) 415 416 /*BLDC pwm*/ 417 418 /*PWM define*/ 419 #define BOARD_BLDCPWM HPM_PWM2 420 #define BOARD_BLDC_UH_PWM_OUTPIN (0U) 421 #define BOARD_BLDC_UL_PWM_OUTPIN (1U) 422 #define BOARD_BLDC_VH_PWM_OUTPIN (2U) 423 #define BOARD_BLDC_VL_PWM_OUTPIN (3U) 424 #define BOARD_BLDC_WH_PWM_OUTPIN (4U) 425 #define BOARD_BLDC_WL_PWM_OUTPIN (5U) 426 #define BOARD_BLDCPWM_TRGM HPM_TRGM2 427 #define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 428 #define BOARD_BLDCPWM_CMP_INDEX_0 (0U) 429 #define BOARD_BLDCPWM_CMP_INDEX_1 (1U) 430 #define BOARD_BLDCPWM_CMP_INDEX_2 (2U) 431 #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) 432 #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) 433 #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) 434 #define BOARD_BLDCPWM_CMP_INDEX_6 (6U) 435 #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) 436 #define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) 437 438 /*HALL define*/ 439 440 #define BOARD_BLDC_HALL_BASE HPM_HALL2 441 #define BOARD_BLDC_HALL_TRGM HPM_TRGM2 442 #define BOARD_BLDC_HALL_IRQ IRQn_HALL2 443 #define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 444 #define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 445 #define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 446 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) 447 448 /*QEI*/ 449 450 #define BOARD_BLDC_QEI_BASE HPM_QEI2 451 #define BOARD_BLDC_QEI_IRQ IRQn_QEI2 452 #define BOARD_BLDC_QEI_TRGM HPM_TRGM2 453 #define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 454 #define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 455 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) 456 #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 457 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) 458 459 /*Timer define*/ 460 461 #define BOARD_TMR_1MS HPM_GPTMR2 462 #define BOARD_TMR_1MS_CH 0 463 #define BOARD_TMR_1MS_CMP 0 464 #define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 465 #define BOARD_TMR_1MS_RELOAD (100000U) 466 467 #define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS 468 #define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH 469 #define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP 470 #define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ 471 #define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD 472 473 /*adc*/ 474 #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 475 #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 476 #define BOARD_BLDC_ADC_V_BASE HPM_ADC1 477 #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 478 #define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete 479 480 #define BOARD_BLDC_ADC_CH_U (7U) 481 #define BOARD_BLDC_ADC_CH_V (10U) 482 #define BOARD_BLDC_ADC_CH_W (11U) 483 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 484 #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) 485 #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A 486 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) 487 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) 488 #define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF 489 #define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A 490 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 491 492 /* APP PWM */ 493 #define BOARD_APP_PWM HPM_PWM2 494 #define BOARD_APP_PWM_CLOCK_NAME clock_mot2 495 #define BOARD_APP_PWM_OUT1 0 496 #define BOARD_APP_PWM_OUT2 1 497 #define BOARD_APP_TRGM HPM_TRGM2 498 #define BOARD_APP_PWM_IRQ IRQn_PWM2 499 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI 500 501 /* RGB LED Section */ 502 #define BOARD_RED_PWM_IRQ IRQn_PWM1 503 #define BOARD_RED_PWM HPM_PWM1 504 #define BOARD_RED_PWM_OUT 8 505 #define BOARD_RED_PWM_CMP 8 506 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true 507 #define BOARD_RED_PWM_CLOCK_NAME clock_mot1 508 509 #define BOARD_GREEN_PWM_IRQ IRQn_PWM0 510 #define BOARD_GREEN_PWM HPM_PWM0 511 #define BOARD_GREEN_PWM_OUT 8 512 #define BOARD_GREEN_PWM_CMP 8 513 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true 514 #define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 515 516 #define BOARD_BLUE_PWM_IRQ IRQn_PWM1 517 #define BOARD_BLUE_PWM HPM_PWM1 518 #define BOARD_BLUE_PWM_OUT 9 519 #define BOARD_BLUE_PWM_CMP 9 520 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true 521 #define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 522 523 #define BOARD_RGB_RED 0 524 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) 525 #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) 526 527 #define BOARD_CPU_FREQ (648000000UL) 528 529 #define BOARD_APP_DISPLAY_CLOCK clock_display 530 531 #ifndef BOARD_SHOW_CLOCK 532 #define BOARD_SHOW_CLOCK 1 533 #endif 534 #ifndef BOARD_SHOW_BANNER 535 #define BOARD_SHOW_BANNER 1 536 #endif 537 538 /* FreeRTOS Definitions */ 539 #define BOARD_FREERTOS_TIMER HPM_GPTMR4 540 #define BOARD_FREERTOS_TIMER_CHANNEL 1 541 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 542 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 543 544 /* Threadx Definitions */ 545 #define BOARD_THREADX_TIMER HPM_GPTMR4 546 #define BOARD_THREADX_TIMER_CHANNEL 1 547 #define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR4 548 #define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr4 549 /* Tamper Section */ 550 #define BOARD_TAMP_ACTIVE_CH 8 551 #define BOARD_TAMP_LOW_LEVEL_CH 10 552 553 #if defined(__cplusplus) 554 extern "C" { 555 #endif /* __cplusplus */ 556 557 typedef void (*board_timer_cb)(void); 558 559 void board_init(void); 560 void board_init_console(void); 561 562 void board_init_core1(void); 563 564 void board_init_uart(UART_Type *ptr); 565 void board_init_i2c(I2C_Type *ptr); 566 void board_init_lcd(void); 567 void board_lcd_backlight(bool is_on); 568 void board_panel_para_to_lcdc(lcdc_config_t *config); 569 void board_init_can(CAN_Type *ptr); 570 571 uint32_t board_init_femc_clock(void); 572 573 void board_init_sdram_pins(void); 574 void board_init_gpio_pins(void); 575 void board_init_spi_pins(SPI_Type *ptr); 576 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); 577 void board_write_spi_cs(uint32_t pin, uint8_t state); 578 void board_init_led_pins(void); 579 580 /* cap touch */ 581 void board_init_cap_touch(void); 582 583 void board_led_write(uint8_t state); 584 void board_led_toggle(void); 585 586 void board_fpga_power_enable(void); 587 588 void board_init_cam_pins(void); 589 void board_write_cam_rst(uint8_t state); 590 591 /* Initialize SoC overall clocks */ 592 void board_init_clock(void); 593 594 /* Initialize the UART clock */ 595 uint32_t board_init_uart_clock(UART_Type *ptr); 596 597 /* Initialize the CAM(camera) dot clock */ 598 uint32_t board_init_cam_clock(CAM_Type *ptr); 599 600 /* Initialize the LCD pixel clock */ 601 uint32_t board_init_lcd_clock(void); 602 603 uint32_t board_init_spi_clock(SPI_Type *ptr); 604 605 uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); 606 607 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); 608 609 uint32_t board_init_can_clock(CAN_Type *ptr); 610 611 uint32_t board_init_pwm_clock(PWM_Type *ptr); 612 613 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); 614 hpm_stat_t board_set_audio_pll_clock(uint32_t freq); 615 616 void board_init_i2s_pins(I2S_Type *ptr); 617 uint32_t board_init_i2s_clock(I2S_Type *ptr); 618 uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); 619 uint32_t board_init_pdm_clock(void); 620 uint32_t board_init_dao_clock(void); 621 622 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); 623 624 void board_init_dao_pins(void); 625 626 void board_init_adc12_pins(void); 627 void board_init_adc16_pins(void); 628 629 void board_init_usb_pins(void); 630 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); 631 632 void board_init_enet_pps_pins(ENET_Type *ptr); 633 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); 634 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); 635 hpm_stat_t board_init_enet_pins(ENET_Type *ptr); 636 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); 637 hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); 638 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); 639 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); 640 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); 641 642 #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT 643 hpm_stat_t board_init_multiple_enet_pins(void); 644 hpm_stat_t board_init_multiple_enet_clock(void); 645 hpm_stat_t board_reset_multiple_enet_phy(void); 646 hpm_stat_t board_init_enet_phy(ENET_Type *ptr); 647 ENET_Type *board_get_enet_base(uint8_t idx); 648 uint8_t board_get_enet_phy_itf(uint8_t idx); 649 void board_get_enet_phy_status(uint8_t idx, void *status); 650 #endif 651 652 /* 653 * @brief Initialize PMP and PMA for but not limited to the following purposes: 654 * -- non-cacheable memory initialization 655 */ 656 void board_init_pmp(void); 657 658 void board_delay_ms(uint32_t ms); 659 void board_delay_us(uint32_t us); 660 661 void board_timer_create(uint32_t ms, board_timer_cb cb); 662 663 void board_init_rgb_pwm_pins(void); 664 void board_enable_output_rgb_led(uint8_t color); 665 void board_disable_output_rgb_led(uint8_t color); 666 667 /* 668 * Keep mchtmr clock on low power mode 669 */ 670 void board_ungate_mchtmr_at_lp_mode(void); 671 672 /* 673 * Get PWM output level of onboard LED 674 */ 675 uint8_t board_get_led_pwm_off_level(void); 676 677 /* 678 * Get GPIO pin level of onboard LED 679 */ 680 uint8_t board_get_led_gpio_off_level(void); 681 682 void board_init_trgm0_p6_pin(void); 683 684 void board_sd_power_switch(SDXC_Type *ptr, bool on_off); 685 686 #if defined(__cplusplus) 687 } 688 #endif /* __cplusplus */ 689 #endif /* _HPM_BOARD_H */ 690