1 /*
2 * Copyright (c) 2021-2024 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 */
6
7 #include "board.h"
8 #include "hpm_uart_drv.h"
9 #include "hpm_gptmr_drv.h"
10 #include "hpm_lcdc_drv.h"
11 #include "hpm_i2c_drv.h"
12 #include "hpm_gpio_drv.h"
13 #include "hpm_debug_console.h"
14 #include "hpm_femc_drv.h"
15 #include "pinmux.h"
16 #include "hpm_pmp_drv.h"
17 #include "assert.h"
18 #include "hpm_clock_drv.h"
19 #include "hpm_sysctl_drv.h"
20 #include "hpm_sdxc_drv.h"
21 #include "hpm_pwm_drv.h"
22 #include "hpm_trgm_drv.h"
23 #include "hpm_pllctl_drv.h"
24 #include "hpm_enet_drv.h"
25 #include "hpm_pcfg_drv.h"
26
27 static board_timer_cb timer_cb;
28
29 /**
30 * @brief FLASH configuration option definitions:
31 * option[0]:
32 * [31:16] 0xfcf9 - FLASH configuration option tag
33 * [15:4] 0 - Reserved
34 * [3:0] option words (exclude option[0])
35 * option[1]:
36 * [31:28] Flash probe type
37 * 0 - SFDP SDR / 1 - SFDP DDR
38 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
39 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
40 * 6 - OctaBus DDR (SPI -> OPI DDR)
41 * 8 - Xccela DDR (SPI -> OPI DDR)
42 * 10 - EcoXiP DDR (SPI -> OPI DDR)
43 * [27:24] Command Pads after Power-on Reset
44 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
45 * [23:20] Command Pads after Configuring FLASH
46 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
47 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
48 * 0 - Not needed
49 * 1 - QE bit is at bit 6 in Status Register 1
50 * 2 - QE bit is at bit1 in Status Register 2
51 * 3 - QE bit is at bit7 in Status Register 2
52 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
53 * [15:8] Dummy cycles
54 * 0 - Auto-probed / detected / default value
55 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
56 * [7:4] Misc.
57 * 0 - Not used
58 * 1 - SPI mode
59 * 2 - Internal loopback
60 * 3 - External DQS
61 * [3:0] Frequency option
62 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
63 *
64 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
65 * [31:20] Reserved
66 * [19:16] IO voltage
67 * 0 - 3V / 1 - 1.8V
68 * [15:12] Pin group
69 * 0 - 1st group / 1 - 2nd group
70 * [11:8] Connection selection
71 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
72 * [7:0] Drive Strength
73 * 0 - Default value
74 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
75 * JESD216)
76 * [31:16] reserved
77 * [15:12] Sector Erase Command Option, not required here
78 * [11:8] Sector Size Option, not required here
79 * [7:0] Flash Size Option
80 * 0 - 4MB / 1 - 8MB / 2 - 16MB
81 */
82 #if defined(FLASH_XIP) && FLASH_XIP
83 __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0};
84 #endif
85
86 #if defined(FLASH_UF2) && FLASH_UF2
87 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
88 #endif
89
board_init_console(void)90 void board_init_console(void)
91 {
92 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
93 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
94 console_config_t cfg;
95
96 /* uart needs to configure pin function before enabling clock, otherwise the level change of
97 uart rx pin when configuring pin function will cause a wrong data to be received.
98 And a uart rx dma request will be generated by default uart fifo dma trigger level. */
99 init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
100
101 /* Configure the UART clock to 24MHz */
102 clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
103 clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
104
105 cfg.type = BOARD_CONSOLE_TYPE;
106 cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE;
107 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
108 cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
109
110 if (status_success != console_init(&cfg)) {
111 /* failed to initialize debug console */
112 while (1) {
113 }
114 }
115 #else
116 while (1) {
117 }
118 #endif
119 #endif
120 }
121
board_print_clock_freq(void)122 void board_print_clock_freq(void)
123 {
124 printf("==============================\n");
125 printf(" %s clock summary\n", BOARD_NAME);
126 printf("==============================\n");
127 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
128 printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
129 printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0));
130 printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1));
131 printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2));
132 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
133 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
134 printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
135 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
136 printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
137 printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
138 printf("display:\t %luHz\n", clock_get_frequency(clock_display));
139 printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0));
140 printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1));
141 printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg));
142 printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma));
143 printf("==============================\n");
144 }
145
board_init_uart(UART_Type * ptr)146 void board_init_uart(UART_Type *ptr)
147 {
148 /* configure uart's pin before opening uart's clock */
149 init_uart_pins(ptr);
150 board_init_uart_clock(ptr);
151 }
152
board_init_ahb(void)153 void board_init_ahb(void)
154 {
155 clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/
156 }
157
board_print_banner(void)158 void board_print_banner(void)
159 {
160 const uint8_t banner[] = {"\n\
161 ----------------------------------------------------------------------\n\
162 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
163 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
164 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
165 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
166 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
167 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
168 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
169 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
170 ----------------------------------------------------------------------\n"};
171 #ifdef SDK_VERSION_STRING
172 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
173 #endif
174 printf("%s", banner);
175 }
176
board_turnoff_rgb_led(void)177 static void board_turnoff_rgb_led(void)
178 {
179 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PE_SET(BOARD_LED_OFF_LEVEL);
180 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
181 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
182 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
183
184 HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
185 HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
186 HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
187 }
188
board_ungate_mchtmr_at_lp_mode(void)189 void board_ungate_mchtmr_at_lp_mode(void)
190 {
191 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
192 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
193 }
194
board_init(void)195 void board_init(void)
196 {
197 board_turnoff_rgb_led();
198 board_init_clock();
199 board_init_console();
200 board_init_pmp();
201 board_init_ahb();
202 #if BOARD_SHOW_CLOCK
203 board_print_clock_freq();
204 #endif
205 #if BOARD_SHOW_BANNER
206 board_print_banner();
207 #endif
208 }
209
board_init_core1(void)210 void board_init_core1(void)
211 {
212 board_init_console();
213 board_init_pmp();
214 }
215
board_init_sdram_pins(void)216 void board_init_sdram_pins(void)
217 {
218 init_sdram_pins();
219 }
220
board_init_femc_clock(void)221 uint32_t board_init_femc_clock(void)
222 {
223 clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */
224 /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */
225
226 return clock_get_frequency(clock_femc);
227 }
228
229 uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz);
230
231 #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13
232
set_reset_pin_level_tm070rdh13(uint8_t level)233 static void set_reset_pin_level_tm070rdh13(uint8_t level)
234 {
235 gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, level);
236 }
237
set_backlight_tm070rdh13(uint16_t percent)238 static void set_backlight_tm070rdh13(uint16_t percent)
239 {
240 gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, percent > 0 ? 1 : 0);
241 }
242
board_init_lcd_rgb_tm070rdh13(void)243 void board_init_lcd_rgb_tm070rdh13(void)
244 {
245 init_lcd_pins(BOARD_LCD_BASE);
246
247 gpio_set_pin_output(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN);
248 gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 0);
249 gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 1);
250
251 gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN);
252 gpio_set_pin_output(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN);
253
254 hpm_panel_hw_interface_t hw_if = {0};
255 hpm_panel_t *panel = hpm_panel_find_device_default();
256 const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
257 uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_display, timing->pixel_clock_khz);
258 hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13;
259 hw_if.set_backlight = set_backlight_tm070rdh13;
260 hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
261 hpm_panel_register_interface(panel, &hw_if);
262
263 printf("name: %s, lcdc_clk: %ukhz\n",
264 hpm_panel_get_name(panel),
265 lcdc_pixel_clk_khz);
266
267 hpm_panel_reset(panel);
268 hpm_panel_init(panel);
269 hpm_panel_power_on(panel);
270 }
271
272 #endif
273
274 #ifdef CONFIG_HPM_PANEL
275
board_lcdc_clock_init(clock_name_t clock_name,uint32_t pixel_clk_khz)276 uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz)
277 {
278 clock_add_to_group(clock_name, 0);
279
280 uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000;
281 uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz;
282 clock_set_source_divider(clock_name, clk_src_pll4_clk0, div);
283 return clock_get_frequency(clock_name) / 1000;
284 }
285
board_lcd_backlight(bool is_on)286 void board_lcd_backlight(bool is_on)
287 {
288 hpm_panel_t *panel = hpm_panel_find_device_default();
289 hpm_panel_set_backlight(panel, is_on == true ? 100 : 0);
290 }
291
board_init_lcd(void)292 void board_init_lcd(void)
293 {
294 #ifdef CONFIG_PANEL_RGB_TM070RDH13
295 board_init_lcd_rgb_tm070rdh13();
296 #endif
297 }
298
board_panel_para_to_lcdc(lcdc_config_t * config)299 void board_panel_para_to_lcdc(lcdc_config_t *config)
300 {
301 const hpm_panel_timing_t *timing;
302 hpm_panel_t *panel = hpm_panel_find_device_default();
303
304 timing = hpm_panel_get_timing(panel);
305 config->resolution_x = timing->hactive;
306 config->resolution_y = timing->vactive;
307
308 config->hsync.pulse_width = timing->hsync_len;
309 config->hsync.back_porch_pulse = timing->hback_porch;
310 config->hsync.front_porch_pulse = timing->hfront_porch;
311
312 config->vsync.pulse_width = timing->vsync_len;
313 config->vsync.back_porch_pulse = timing->vback_porch;
314 config->vsync.front_porch_pulse = timing->vfront_porch;
315
316 config->control.invert_hsync = timing->hsync_pol;
317 config->control.invert_vsync = timing->vsync_pol;
318 config->control.invert_href = timing->de_pol;
319 config->control.invert_pixel_data = timing->pixel_data_pol;
320 config->control.invert_pixel_clock = timing->pixel_clk_pol;
321 }
322 #endif
323
board_delay_ms(uint32_t ms)324 void board_delay_ms(uint32_t ms)
325 {
326 clock_cpu_delay_ms(ms);
327 }
328
board_delay_us(uint32_t us)329 void board_delay_us(uint32_t us)
330 {
331 clock_cpu_delay_us(us);
332 }
333
board_timer_isr(void)334 void board_timer_isr(void)
335 {
336 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
337 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
338 timer_cb();
339 }
340 }
341 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
342
board_timer_create(uint32_t ms,board_timer_cb cb)343 void board_timer_create(uint32_t ms, board_timer_cb cb)
344 {
345 uint32_t gptmr_freq;
346 gptmr_channel_config_t config;
347
348 timer_cb = cb;
349 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
350
351 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
352 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
353
354 config.reload = gptmr_freq / 1000 * ms;
355 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
356 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
357 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
358
359 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
360 }
361
board_i2c_bus_clear(I2C_Type * ptr)362 void board_i2c_bus_clear(I2C_Type *ptr)
363 {
364 init_i2c_pins_as_gpio(ptr);
365 if (ptr == BOARD_CAP_I2C_BASE) {
366 gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN);
367 gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
368 if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) {
369 printf("CLK is low, please power cycle the board\n");
370 while (1) {
371 }
372 }
373 if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) {
374 printf("SDA is low, try to issue I2C bus clear\n");
375 } else {
376 printf("I2C bus is ready\n");
377 return;
378 }
379
380 gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
381 while (1) {
382 for (uint32_t i = 0; i < 9; i++) {
383 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1);
384 board_delay_ms(10);
385 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0);
386 board_delay_ms(10);
387 }
388 board_delay_ms(100);
389 }
390 printf("I2C bus is cleared\n");
391 }
392 }
393
board_init_i2c(I2C_Type * ptr)394 void board_init_i2c(I2C_Type *ptr)
395 {
396 hpm_stat_t stat;
397 uint32_t freq;
398 i2c_config_t config;
399
400 board_i2c_bus_clear(ptr);
401
402 init_i2c_pins(ptr);
403 clock_add_to_group(clock_i2c0, 0);
404 clock_add_to_group(clock_i2c1, 0);
405 clock_add_to_group(clock_i2c2, 0);
406 clock_add_to_group(clock_i2c3, 0);
407 /* Configure the I2C clock to 24MHz */
408 clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U);
409
410 config.i2c_mode = i2c_mode_normal;
411 config.is_10bit_addressing = false;
412 freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME);
413 stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config);
414 if (stat != status_success) {
415 printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE);
416 while (1) {
417 }
418 }
419 }
420
board_init_uart_clock(UART_Type * ptr)421 uint32_t board_init_uart_clock(UART_Type *ptr)
422 {
423 uint32_t freq = 0;
424 clock_name_t clock_name = clock_uart0;
425 bool need_init_clock = true;
426 if (ptr == HPM_UART0) {
427 clock_name = clock_uart0;
428 } else if (ptr == HPM_UART1) {
429 clock_name = clock_uart1;
430 } else if (ptr == HPM_UART2) {
431 clock_name = clock_uart2;
432 } else if (ptr == HPM_UART3) {
433 clock_name = clock_uart3;
434 } else if (ptr == HPM_UART4) {
435 clock_name = clock_uart4;
436 } else if (ptr == HPM_UART5) {
437 clock_name = clock_uart5;
438 } else if (ptr == HPM_UART6) {
439 clock_name = clock_uart6;
440 } else if (ptr == HPM_UART7) {
441 clock_name = clock_uart7;
442 } else if (ptr == HPM_UART8) {
443 clock_name = clock_uart8;
444 } else if (ptr == HPM_UART9) {
445 clock_name = clock_uart9;
446 } else if (ptr == HPM_UART10) {
447 clock_name = clock_uart10;
448 } else if (ptr == HPM_UART11) {
449 clock_name = clock_uart11;
450 } else if (ptr == HPM_UART12) {
451 clock_name = clock_uart12;
452 } else if (ptr == HPM_UART13) {
453 clock_name = clock_uart13;
454 } else if (ptr == HPM_UART14) {
455 clock_name = clock_uart14;
456 } else if (ptr == HPM_UART15) {
457 clock_name = clock_uart15;
458 } else {
459 /* Unsupported instance */
460 need_init_clock = false;
461 }
462
463 if (need_init_clock) {
464 clock_set_source_divider(clock_name, clk_src_osc24m, 1);
465 clock_add_to_group(clock_name, 0);
466 freq = clock_get_frequency(clock_name);
467 }
468
469 return freq;
470 }
471
board_init_spi_clock(SPI_Type * ptr)472 uint32_t board_init_spi_clock(SPI_Type *ptr)
473 {
474 if (ptr == HPM_SPI2) {
475 /* SPI2 clock configure */
476 clock_add_to_group(clock_spi2, 0);
477 clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */
478
479 return clock_get_frequency(clock_spi2);
480 }
481 return 0;
482 }
483
board_init_cap_touch(void)484 void board_init_cap_touch(void)
485 {
486 init_cap_pins();
487 gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0);
488 gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
489
490 board_delay_ms(1);
491 gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
492 board_delay_ms(1);
493 gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1);
494 board_delay_ms(6);
495 gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
496
497 board_init_i2c(BOARD_CAP_I2C_BASE);
498 }
499
board_init_gpio_pins(void)500 void board_init_gpio_pins(void)
501 {
502 init_gpio_pins();
503 }
504
board_init_spi_pins(SPI_Type * ptr)505 void board_init_spi_pins(SPI_Type *ptr)
506 {
507 init_spi_pins(ptr);
508 }
509
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)510 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
511 {
512 init_spi_pins_with_gpio_as_cs(ptr);
513 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
514 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
515 }
516
board_write_spi_cs(uint32_t pin,uint8_t state)517 void board_write_spi_cs(uint32_t pin, uint8_t state)
518 {
519 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
520 }
521
board_get_led_pwm_off_level(void)522 uint8_t board_get_led_pwm_off_level(void)
523 {
524 return BOARD_LED_OFF_LEVEL;
525 }
526
board_get_led_gpio_off_level(void)527 uint8_t board_get_led_gpio_off_level(void)
528 {
529 return BOARD_LED_OFF_LEVEL;
530 }
531
board_init_led_pins(void)532 void board_init_led_pins(void)
533 {
534 board_turnoff_rgb_led();
535 init_led_pins_as_gpio();
536 gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level());
537 gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level());
538 gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level());
539 }
540
board_led_toggle(void)541 void board_led_toggle(void)
542 {
543 #ifdef BOARD_LED_TOGGLE_RGB
544 static uint8_t i;
545 gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & (1 << i)) << BOARD_R_GPIO_PIN);
546 i++;
547 i = i % 3;
548 #else
549 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
550 #endif
551 }
552
board_led_write(uint8_t state)553 void board_led_write(uint8_t state)
554 {
555 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
556 }
557
board_init_cam_pins(void)558 void board_init_cam_pins(void)
559 {
560 init_cam_pins();
561 /* enable cam RST pin out with high level */
562 gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1);
563 }
564
board_write_cam_rst(uint8_t state)565 void board_write_cam_rst(uint8_t state)
566 {
567 gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state);
568
569 }
570
board_init_usb_pins(void)571 void board_init_usb_pins(void)
572 {
573 /* set pull-up for USBx OC pins and ID pins */
574 init_usb_pins();
575
576 /* configure USBx ID pins as input function */
577 gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
578 gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN);
579
580 /* configure USBx OC Flag pins as input function */
581 gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN);
582 gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN);
583 }
584
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)585 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
586 {
587 (void) usb_index;
588 (void) level;
589 }
590
board_init_pmp(void)591 void board_init_pmp(void)
592 {
593 uint32_t start_addr;
594 uint32_t end_addr;
595 uint32_t length;
596 pmp_entry_t pmp_entry[16];
597 uint8_t index = 0;
598
599 /* Init noncachable memory */
600 extern uint32_t __noncacheable_start__[];
601 extern uint32_t __noncacheable_end__[];
602 start_addr = (uint32_t) __noncacheable_start__;
603 end_addr = (uint32_t) __noncacheable_end__;
604 length = end_addr - start_addr;
605 if (length > 0) {
606 /* Ensure the address and the length are power of 2 aligned */
607 assert((length & (length - 1U)) == 0U);
608 assert((start_addr & (length - 1U)) == 0U);
609 pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
610 pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
611 pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
612 pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
613 index++;
614 }
615
616 pmp_config(&pmp_entry[0], index);
617 }
618
board_init_clock(void)619 void board_init_clock(void)
620 {
621 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
622 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
623 /* Configure the External OSC ramp-up time: ~9ms */
624 pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
625
626 /* Select clock setting preset1 */
627 sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
628 }
629
630 /* Add most Clocks to group 0 */
631 /* not open uart clock in this API, uart should configure pin function before opening clock */
632 clock_add_to_group(clock_cpu0, 0);
633 clock_add_to_group(clock_mchtmr0, 0);
634 clock_add_to_group(clock_axi0, 0);
635 clock_add_to_group(clock_axi1, 0);
636 clock_add_to_group(clock_axi2, 0);
637 clock_add_to_group(clock_ahb, 0);
638 clock_add_to_group(clock_femc, 0);
639 clock_add_to_group(clock_xpi0, 0);
640 clock_add_to_group(clock_xpi1, 0);
641 clock_add_to_group(clock_gptmr0, 0);
642 clock_add_to_group(clock_gptmr1, 0);
643 clock_add_to_group(clock_gptmr2, 0);
644 clock_add_to_group(clock_gptmr3, 0);
645 clock_add_to_group(clock_gptmr4, 0);
646 clock_add_to_group(clock_gptmr5, 0);
647 clock_add_to_group(clock_gptmr6, 0);
648 clock_add_to_group(clock_gptmr7, 0);
649 clock_add_to_group(clock_i2c0, 0);
650 clock_add_to_group(clock_i2c1, 0);
651 clock_add_to_group(clock_i2c2, 0);
652 clock_add_to_group(clock_i2c3, 0);
653 clock_add_to_group(clock_spi0, 0);
654 clock_add_to_group(clock_spi1, 0);
655 clock_add_to_group(clock_spi2, 0);
656 clock_add_to_group(clock_spi3, 0);
657 clock_add_to_group(clock_can0, 0);
658 clock_add_to_group(clock_can1, 0);
659 clock_add_to_group(clock_can2, 0);
660 clock_add_to_group(clock_can3, 0);
661 clock_add_to_group(clock_display, 0);
662 clock_add_to_group(clock_sdxc0, 0);
663 clock_add_to_group(clock_sdxc1, 0);
664 clock_add_to_group(clock_camera0, 0);
665 clock_add_to_group(clock_camera1, 0);
666 clock_add_to_group(clock_ptpc, 0);
667 clock_add_to_group(clock_ref0, 0);
668 clock_add_to_group(clock_ref1, 0);
669 clock_add_to_group(clock_watchdog0, 0);
670 clock_add_to_group(clock_eth0, 0);
671 clock_add_to_group(clock_eth1, 0);
672 clock_add_to_group(clock_sdp, 0);
673 clock_add_to_group(clock_xdma, 0);
674 clock_add_to_group(clock_ram0, 0);
675 clock_add_to_group(clock_ram1, 0);
676 clock_add_to_group(clock_usb0, 0);
677 clock_add_to_group(clock_usb1, 0);
678 clock_add_to_group(clock_jpeg, 0);
679 clock_add_to_group(clock_pdma, 0);
680 clock_add_to_group(clock_kman, 0);
681 clock_add_to_group(clock_gpio, 0);
682 clock_add_to_group(clock_mbx0, 0);
683 clock_add_to_group(clock_hdma, 0);
684 clock_add_to_group(clock_rng, 0);
685 clock_add_to_group(clock_mot0, 0);
686 clock_add_to_group(clock_mot1, 0);
687 clock_add_to_group(clock_mot2, 0);
688 clock_add_to_group(clock_mot3, 0);
689 clock_add_to_group(clock_acmp, 0);
690 clock_add_to_group(clock_dao, 0);
691 clock_add_to_group(clock_synt, 0);
692 clock_add_to_group(clock_lmm0, 0);
693 clock_add_to_group(clock_lmm1, 0);
694 clock_add_to_group(clock_pdm, 0);
695
696 clock_add_to_group(clock_adc0, 0);
697 clock_add_to_group(clock_adc1, 0);
698 clock_add_to_group(clock_adc2, 0);
699 clock_add_to_group(clock_adc3, 0);
700
701 clock_add_to_group(clock_i2s0, 0);
702 clock_add_to_group(clock_i2s1, 0);
703 clock_add_to_group(clock_i2s2, 0);
704 clock_add_to_group(clock_i2s3, 0);
705 /* Connect Group0 to CPU0 */
706 clock_connect_group_to_cpu(0, 0);
707
708 /* Add the CPU1 clock to Group1 */
709 clock_add_to_group(clock_mchtmr1, 1);
710 clock_add_to_group(clock_mbx1, 1);
711 /* Connect Group1 to CPU1 */
712 clock_connect_group_to_cpu(1, 1);
713
714 /* Bump up DCDC voltage to 1200mv */
715 pcfg_dcdc_set_voltage(HPM_PCFG, 1200);
716 pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG);
717
718 if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
719 printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ);
720 while (1) {
721 }
722 }
723
724 clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
725 clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
726 clock_update_core_clock();
727
728 clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/
729 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
730 clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
731 }
732
board_init_cam_clock(CAM_Type * ptr)733 uint32_t board_init_cam_clock(CAM_Type *ptr)
734 {
735 uint32_t freq = 0;
736 if (ptr == HPM_CAM0) {
737 /* Configure camera clock to 24MHz */
738 clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U);
739 freq = clock_get_frequency(clock_camera0);
740 } else if (ptr == HPM_CAM1) {
741 /* Configure camera clock to 24MHz */
742 clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U);
743 freq = clock_get_frequency(clock_camera1);
744 } else {
745 /* Invalid camera instance */
746 }
747 return freq;
748 }
749
board_init_lcd_clock(void)750 uint32_t board_init_lcd_clock(void)
751 {
752 uint32_t freq;
753 clock_add_to_group(clock_display, 0);
754 /* Configure LCDC clock to 59.4MHz */
755 clock_set_source_divider(clock_display, clk_src_pll4_clk0, 10U);
756 freq = clock_get_frequency(clock_display);
757 return freq;
758 }
759
board_init_dao_clock(void)760 uint32_t board_init_dao_clock(void)
761 {
762 clock_add_to_group(clock_dao, 0);
763
764 sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25);
765 sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk);
766
767 return clock_get_frequency(clock_dao);
768 }
769
board_init_pdm_clock(void)770 uint32_t board_init_pdm_clock(void)
771 {
772 clock_add_to_group(clock_pdm, 0);
773
774 sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
775 sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
776
777 return clock_get_frequency(clock_pdm);
778 }
779
board_set_audio_pll_clock(uint32_t freq)780 hpm_stat_t board_set_audio_pll_clock(uint32_t freq)
781 {
782 return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */
783 }
784
board_init_i2s_pins(I2S_Type * ptr)785 void board_init_i2s_pins(I2S_Type *ptr)
786 {
787 init_i2s_pins(ptr);
788 }
789
board_init_i2s_clock(I2S_Type * ptr)790 uint32_t board_init_i2s_clock(I2S_Type *ptr)
791 {
792 uint32_t freq = 0;
793
794 if (ptr == HPM_I2S0) {
795 clock_add_to_group(clock_i2s0, 0);
796
797 sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
798 sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
799
800 freq = clock_get_frequency(clock_i2s0);
801 } else if (ptr == HPM_I2S1) {
802 clock_add_to_group(clock_i2s1, 0);
803
804 sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25);
805 sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk);
806
807 freq = clock_get_frequency(clock_i2s1);
808 } else {
809 ;
810 }
811
812 return freq;
813 }
814
815 /* adjust I2S source clock base on sample rate */
board_config_i2s_clock(I2S_Type * ptr,uint32_t sample_rate)816 uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate)
817 {
818 uint32_t freq = 0;
819
820 if (ptr == HPM_I2S0) {
821 clock_add_to_group(clock_i2s0, 0);
822 if ((sample_rate % 22050) == 0) {
823 clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */
824 } else {
825 clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */
826 }
827 clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0);
828 freq = clock_get_frequency(clock_i2s0);
829 } else if (ptr == HPM_I2S1) {
830 clock_add_to_group(clock_i2s1, 0);
831 if ((sample_rate % 22050) == 0) {
832 clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */
833 } else {
834 clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */
835 }
836 clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1);
837 freq = clock_get_frequency(clock_i2s1);
838 } else {
839 ;
840 }
841
842 return freq;
843 }
844
board_init_adc12_pins(void)845 void board_init_adc12_pins(void)
846 {
847 init_adc12_pins();
848 }
849
board_init_adc16_pins(void)850 void board_init_adc16_pins(void)
851 {
852 init_adc16_pins();
853 }
854
board_init_adc12_clock(ADC12_Type * ptr,bool clk_src_ahb)855 uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb)
856 {
857 uint32_t freq = 0;
858
859 if (ptr == HPM_ADC0) {
860 if (clk_src_ahb) {
861 /* Configure the ADC clock from AHB (@200MHz by default)*/
862 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
863 } else {
864 /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
865 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
866 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
867 }
868 freq = clock_get_frequency(clock_adc0);
869 } else if (ptr == HPM_ADC1) {
870 if (clk_src_ahb) {
871 /* Configure the ADC clock from AHB (@200MHz by default)*/
872 clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
873 } else {
874 /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
875 clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
876 clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U);
877 }
878 freq = clock_get_frequency(clock_adc1);
879 } else if (ptr == HPM_ADC2) {
880 if (clk_src_ahb) {
881 /* Configure the ADC clock from AHB (@200MHz by default)*/
882 clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
883 } else {
884 /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
885 clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
886 clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U);
887 }
888 freq = clock_get_frequency(clock_adc2);
889 }
890
891 return freq;
892 }
893
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)894 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
895 {
896 uint32_t freq = 0;
897
898 if (ptr == HPM_ADC3) {
899 if (clk_src_ahb) {
900 /* Configure the ADC clock from AHB (@200MHz by default)*/
901 clock_set_adc_source(clock_adc3, clk_adc_src_ahb0);
902 } else {
903 /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
904 clock_set_adc_source(clock_adc3, clk_adc_src_ana2);
905 clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U);
906 }
907
908 freq = clock_get_frequency(clock_adc3);
909 }
910
911 return freq;
912 }
913
board_init_can(CAN_Type * ptr)914 void board_init_can(CAN_Type *ptr)
915 {
916 init_can_pins(ptr);
917 }
918
board_init_can_clock(CAN_Type * ptr)919 uint32_t board_init_can_clock(CAN_Type *ptr)
920 {
921 uint32_t freq = 0;
922 if (ptr == HPM_CAN0) {
923 /* Set the CAN0 peripheral clock to 80MHz */
924 clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5);
925 freq = clock_get_frequency(clock_can0);
926 } else if (ptr == HPM_CAN1) {
927 /* Set the CAN1 peripheral clock to 80MHz */
928 clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5);
929 freq = clock_get_frequency(clock_can1);
930 } else if (ptr == HPM_CAN2) {
931 /* Set the CAN2 peripheral clock to 80MHz */
932 clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5);
933 freq = clock_get_frequency(clock_can2);
934 } else if (ptr == HPM_CAN3) {
935 /* Set the CAN3 peripheral clock to 80MHz */
936 clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5);
937 freq = clock_get_frequency(clock_can3);
938 } else {
939 /* Invalid CAN instance */
940 }
941 return freq;
942 }
943
board_init_gptmr_clock(GPTMR_Type * ptr)944 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
945 {
946 uint32_t freq = 0;
947
948 if (ptr == HPM_GPTMR0) {
949 clock_add_to_group(clock_gptmr0, 0);
950 clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
951 freq = clock_get_frequency(clock_gptmr0);
952 }
953 else if (ptr == HPM_GPTMR1) {
954 clock_add_to_group(clock_gptmr1, 0);
955 clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
956 freq = clock_get_frequency(clock_gptmr1);
957 }
958 else if (ptr == HPM_GPTMR2) {
959 clock_add_to_group(clock_gptmr2, 0);
960 clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
961 freq = clock_get_frequency(clock_gptmr2);
962 }
963 else if (ptr == HPM_GPTMR3) {
964 clock_add_to_group(clock_gptmr3, 0);
965 clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
966 freq = clock_get_frequency(clock_gptmr3);
967 }
968 else if (ptr == HPM_GPTMR4) {
969 clock_add_to_group(clock_gptmr4, 0);
970 clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4);
971 freq = clock_get_frequency(clock_gptmr4);
972 }
973 else if (ptr == HPM_GPTMR5) {
974 clock_add_to_group(clock_gptmr5, 0);
975 clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4);
976 freq = clock_get_frequency(clock_gptmr5);
977 }
978 else if (ptr == HPM_GPTMR6) {
979 clock_add_to_group(clock_gptmr6, 0);
980 clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4);
981 freq = clock_get_frequency(clock_gptmr6);
982 }
983 else if (ptr == HPM_GPTMR7) {
984 clock_add_to_group(clock_gptmr7, 0);
985 clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4);
986 freq = clock_get_frequency(clock_gptmr7);
987 }
988 else {
989 /* Invalid instance */
990 }
991 return freq;
992 }
993
994
995 /*
996 * this function will be called during startup to initialize external memory for data use
997 */
_init_ext_ram(void)998 void _init_ext_ram(void)
999 {
1000 uint32_t femc_clk_in_hz;
1001 clock_add_to_group(clock_femc, 0);
1002 board_init_sdram_pins();
1003 femc_clk_in_hz = board_init_femc_clock();
1004
1005 femc_config_t config = {0};
1006 femc_sdram_config_t sdram_config = {0};
1007
1008 femc_default_config(HPM_FEMC, &config);
1009 femc_init(HPM_FEMC, &config);
1010
1011 femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);
1012
1013 sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
1014 sdram_config.prescaler = 0x3;
1015 sdram_config.burst_len_in_byte = 8;
1016 sdram_config.auto_refresh_count_in_one_burst = 1;
1017 sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
1018 sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
1019
1020 sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */
1021 sdram_config.refresh_recover_in_ns = 60; /* Trc */
1022 sdram_config.act_to_precharge_in_ns = 42; /* Tras */
1023 sdram_config.act_to_rw_in_ns = 18; /* Trcd */
1024 sdram_config.precharge_to_act_in_ns = 18; /* Trp */
1025 sdram_config.act_to_act_in_ns = 12; /* Trrd */
1026 sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
1027 sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */
1028
1029 sdram_config.cs = BOARD_SDRAM_CS;
1030 sdram_config.base_address = BOARD_SDRAM_ADDRESS;
1031 sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
1032 sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
1033 sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
1034 sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
1035 sdram_config.delay_cell_disable = true;
1036 sdram_config.delay_cell_value = 0;
1037
1038 femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
1039 }
1040
board_sd_power_switch(SDXC_Type * ptr,bool on_off)1041 void board_sd_power_switch(SDXC_Type *ptr, bool on_off)
1042 {
1043 if (ptr == BOARD_APP_SDCARD_SDXC_BASE) {
1044 init_sdxc_pwr_pin(ptr, true);
1045 gpio_set_pin_output_with_initial(BOARD_APP_SDCARD_POWER_EN_GPIO_BASE, BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX, BOARD_APP_SDCARD_POWER_EN_GPIO_PIN, on_off);
1046 }
1047 }
1048
board_sd_configure_clock(SDXC_Type * ptr,uint32_t freq,bool need_inverse)1049 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse)
1050 {
1051 uint32_t actual_freq = 0;
1052 do {
1053 if (ptr != BOARD_APP_SDCARD_SDXC_BASE) {
1054 break;
1055 }
1056 clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
1057 sdxc_enable_inverse_clock(ptr, false);
1058 sdxc_enable_sd_clock(ptr, false);
1059 /* Configure the clock below 400KHz for the identification state */
1060 if (freq <= 400000UL) {
1061 clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63);
1062 }
1063 /* configure the clock to 24MHz for the SDR12/Default speed */
1064 else if (freq <= 26000000UL) {
1065 clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
1066 }
1067 /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
1068 else if (freq <= 52000000UL) {
1069 clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8);
1070 }
1071 /* Configure the clock to 100MHz for the SDR50 */
1072 else if (freq <= 100000000UL) {
1073 clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4);
1074 }
1075 /* Configure the clock to 166MHz for SDR104/HS200/HS400 */
1076 else if (freq <= 208000000UL) {
1077 clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2);
1078 }
1079 /* For other unsupported clock ranges, configure the clock to 24MHz */
1080 else {
1081 clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
1082 }
1083 if (need_inverse) {
1084 sdxc_enable_inverse_clock(ptr, true);
1085 }
1086 sdxc_enable_sd_clock(ptr, true);
1087 actual_freq = clock_get_frequency(sdxc_clk);
1088 } while (false);
1089
1090 return actual_freq;
1091 }
1092
board_sd_switch_pins_to_1v8(SDXC_Type * ptr)1093 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr)
1094 {
1095 /* This feature is not supported */
1096 }
1097
board_sd_detect_card(SDXC_Type * ptr)1098 bool board_sd_detect_card(SDXC_Type *ptr)
1099 {
1100 GPIO_Type *gpio = BOARD_APP_SDCARD_CARD_DETECTION_GPIO;
1101 uint32_t gpio_index = BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX;
1102 uint32_t pin_index = BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX;
1103 return ((gpio->DI[gpio_index].VALUE & (1UL << pin_index)) == 0U);
1104 }
1105
set_rgb_output_off(PWM_Type * ptr,uint8_t pin,uint8_t cmp_index)1106 static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index)
1107 {
1108 pwm_cmp_config_t cmp_config = {0};
1109 pwm_output_channel_t ch_config = {0};
1110
1111 pwm_stop_counter(ptr);
1112 pwm_get_default_cmp_config(ptr, &cmp_config);
1113 pwm_get_default_output_channel_config(ptr, &ch_config);
1114
1115 pwm_set_reload(ptr, 0, 0xF);
1116 pwm_set_start_count(ptr, 0, 0);
1117
1118 cmp_config.mode = pwm_cmp_mode_output_compare;
1119 cmp_config.cmp = 0x10;
1120 cmp_config.update_trigger = pwm_shadow_register_update_on_modify;
1121 pwm_config_cmp(ptr, cmp_index, &cmp_config);
1122
1123 ch_config.cmp_start_index = cmp_index;
1124 ch_config.cmp_end_index = cmp_index;
1125 ch_config.invert_output = false;
1126
1127 pwm_config_output_channel(ptr, pin, &ch_config);
1128 }
1129
board_init_rgb_pwm_pins(void)1130 void board_init_rgb_pwm_pins(void)
1131 {
1132 trgm_output_t config = {0};
1133 board_turnoff_rgb_led();
1134
1135 set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP);
1136 set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP);
1137 set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP);
1138
1139 init_rgb_pwm_pins();
1140
1141 config.type = 0;
1142 config.invert = false;
1143
1144 /* Red: TRGM1 P1 */
1145 config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH8REF;
1146 trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT1, &config);
1147
1148 /* Green: TRGM0 P6 */
1149 config.input = HPM_TRGM0_INPUT_SRC_PWM0_CH8REF;
1150 trgm_output_config(HPM_TRGM0, TRGM_TRGOCFG_TRGM_OUT6, &config);
1151
1152 /* Blue: TRGM1 P3 */
1153 config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH9REF;
1154 trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT3, &config);
1155 }
1156
board_disable_output_rgb_led(uint8_t color)1157 void board_disable_output_rgb_led(uint8_t color)
1158 {
1159 switch (color) {
1160 case BOARD_RGB_RED:
1161 trgm_disable_io_output(HPM_TRGM1, 1 << 1);
1162 break;
1163 case BOARD_RGB_GREEN:
1164 trgm_disable_io_output(HPM_TRGM0, 1 << 6);
1165 break;
1166 case BOARD_RGB_BLUE:
1167 trgm_disable_io_output(HPM_TRGM1, 1 << 3);
1168 break;
1169 default:
1170 while (1) {
1171 ;
1172 }
1173 }
1174 }
1175
board_enable_output_rgb_led(uint8_t color)1176 void board_enable_output_rgb_led(uint8_t color)
1177 {
1178 switch (color) {
1179 case BOARD_RGB_RED:
1180 trgm_enable_io_output(HPM_TRGM1, 1 << 1);
1181 break;
1182 case BOARD_RGB_GREEN:
1183 trgm_enable_io_output(HPM_TRGM0, 1 << 6);
1184 break;
1185 case BOARD_RGB_BLUE:
1186 trgm_enable_io_output(HPM_TRGM1, 1 << 3);
1187 break;
1188 default:
1189 while (1) {
1190 ;
1191 }
1192 }
1193 }
1194
board_init_enet_ptp_clock(ENET_Type * ptr)1195 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
1196 {
1197 /* set clock source */
1198 if (ptr == HPM_ENET0) {
1199 /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */
1200 clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */
1201 } else if (ptr == HPM_ENET1) {
1202 /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */
1203 clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */
1204 } else {
1205 return status_invalid_argument;
1206 }
1207
1208 return status_success;
1209 }
1210
board_init_enet_rmii_reference_clock(ENET_Type * ptr,bool internal)1211 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
1212 {
1213 /* Configure Enet clock to output reference clock */
1214 if (ptr == HPM_ENET1) {
1215 if (internal) {
1216 /* set pll output frequency at 1GHz */
1217 if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
1218 /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */
1219 pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4);
1220 /* set eth clock frequency at 50MHz for enet0 */
1221 clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5);
1222 } else {
1223 return status_fail;
1224 }
1225 }
1226 } else {
1227 return status_invalid_argument;
1228 }
1229
1230 enet_rmii_enable_clock(ptr, internal);
1231
1232 return status_success;
1233 }
1234
board_init_enet_rgmii_clock_delay(ENET_Type * ptr)1235 hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr)
1236 {
1237 if (ptr == HPM_ENET0) {
1238 return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY);
1239 }
1240
1241 return status_invalid_argument;
1242 }
1243
board_init_enet_pins(ENET_Type * ptr)1244 hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
1245 {
1246 init_enet_pins(ptr);
1247
1248 if (ptr == HPM_ENET0) {
1249 gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
1250 } else if (ptr == HPM_ENET1) {
1251 gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0);
1252 } else {
1253 return status_invalid_argument;
1254 }
1255
1256 return status_success;
1257 }
1258
board_reset_enet_phy(ENET_Type * ptr)1259 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
1260 {
1261 if (ptr == HPM_ENET0) {
1262 gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
1263 board_delay_ms(1);
1264 gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1);
1265 } else if (ptr == HPM_ENET1) {
1266 gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0);
1267 board_delay_ms(1);
1268 gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1);
1269 } else {
1270 return status_invalid_argument;
1271 }
1272
1273 return status_success;
1274 }
1275
board_get_enet_dma_pbl(ENET_Type * ptr)1276 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
1277 {
1278 (void) ptr;
1279 return enet_pbl_32;
1280 }
1281
board_enable_enet_irq(ENET_Type * ptr)1282 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
1283 {
1284 if (ptr == HPM_ENET0) {
1285 intc_m_enable_irq(IRQn_ENET0);
1286 } else if (ptr == HPM_ENET1) {
1287 intc_m_enable_irq(IRQn_ENET1);
1288 } else {
1289 return status_invalid_argument;
1290 }
1291
1292 return status_success;
1293 }
1294
board_disable_enet_irq(ENET_Type * ptr)1295 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
1296 {
1297 if (ptr == HPM_ENET0) {
1298 intc_m_disable_irq(IRQn_ENET0);
1299 } else if (ptr == HPM_ENET1) {
1300 intc_m_disable_irq(IRQn_ENET1);
1301 } else {
1302 return status_invalid_argument;
1303 }
1304
1305 return status_success;
1306 }
1307
board_init_enet_pps_pins(ENET_Type * ptr)1308 void board_init_enet_pps_pins(ENET_Type *ptr)
1309 {
1310 (void) ptr;
1311 init_enet_pps_pins();
1312 }
1313
1314 #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT
1315
board_init_multiple_enet_pins(void)1316 hpm_stat_t board_init_multiple_enet_pins(void)
1317 {
1318 board_init_enet_pins(HPM_ENET0);
1319 board_init_enet_pins(HPM_ENET1);
1320
1321 return status_success;
1322 }
1323
board_init_multiple_enet_clock(void)1324 hpm_stat_t board_init_multiple_enet_clock(void)
1325 {
1326 /* Set RGMII clock delay */
1327 board_init_enet_rgmii_clock_delay(HPM_ENET0);
1328
1329 /* Set RMII reference clock */
1330 board_init_enet_rmii_reference_clock(HPM_ENET1, BOARD_ENET_RMII_INT_REF_CLK);
1331 printf("Enet1 Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock");
1332
1333 return status_success;
1334 }
1335
board_reset_multiple_enet_phy(void)1336 hpm_stat_t board_reset_multiple_enet_phy(void)
1337 {
1338 board_reset_enet_phy(HPM_ENET0);
1339 board_reset_enet_phy(HPM_ENET1);
1340
1341 return status_success;
1342 }
1343
board_init_enet_phy(ENET_Type * ptr)1344 hpm_stat_t board_init_enet_phy(ENET_Type *ptr)
1345 {
1346 rtl8211_config_t phy_config0;
1347 rtl8201_config_t phy_config1;
1348
1349 if (ptr == HPM_ENET0) {
1350 rtl8211_reset(ptr);
1351 rtl8211_basic_mode_default_config(HPM_ENET0, &phy_config0);
1352 if (rtl8211_basic_mode_init(HPM_ENET0, &phy_config0) == true) {
1353 return status_success;
1354 } else {
1355 printf("Enet0 phy init failed!\n");
1356 return status_fail;
1357 }
1358 } else if (ptr == HPM_ENET1) {
1359 rtl8201_reset(HPM_ENET1);
1360 rtl8201_basic_mode_default_config(HPM_ENET1, &phy_config1);
1361 if (rtl8201_basic_mode_init(HPM_ENET1, &phy_config1) == true) {
1362 return status_success;
1363 } else {
1364 printf("Enet1 phy init failed!\n");
1365 return status_fail;
1366 }
1367 } else {
1368 return status_invalid_argument;
1369 }
1370 }
1371
board_get_enet_base(uint8_t idx)1372 ENET_Type *board_get_enet_base(uint8_t idx)
1373 {
1374 if (idx == 0) {
1375 return HPM_ENET0;
1376 } else {
1377 return HPM_ENET1;
1378 }
1379 }
1380
board_get_enet_phy_itf(uint8_t idx)1381 uint8_t board_get_enet_phy_itf(uint8_t idx)
1382 {
1383 if (idx == 0) {
1384 return BOARD_ENET_RGMII_PHY_ITF;
1385 } else {
1386 return BOARD_ENET_RMII_PHY_ITF;
1387 }
1388 }
1389
board_get_enet_phy_status(uint8_t idx,void * status)1390 void board_get_enet_phy_status(uint8_t idx, void *status)
1391 {
1392 if (idx == 0) {
1393 rtl8211_get_phy_status(HPM_ENET0, status);
1394 } else {
1395 rtl8201_get_phy_status(HPM_ENET1, status);
1396 }
1397 }
1398 #endif
1399
board_init_dao_pins(void)1400 void board_init_dao_pins(void)
1401 {
1402 init_dao_pins();
1403 }
1404