1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_BOARD_H 9 #define _HPM_BOARD_H 10 #include <stdio.h> 11 #include "hpm_common.h" 12 #include "hpm_clock_drv.h" 13 #include "hpm_soc.h" 14 #include "hpm_soc_feature.h" 15 #include "pinmux.h" 16 #include "hpm_lcdc_drv.h" 17 #include "hpm_trgm_drv.h" 18 #ifdef CONFIG_HPM_PANEL 19 #include "hpm_panel.h" 20 #endif 21 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 22 #include "hpm_debug_console.h" 23 #endif 24 25 #define BOARD_NAME "hpm6750evk2" 26 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) 27 28 #define SEC_CORE_IMG_START ILM_LOCAL_BASE 29 30 #ifndef BOARD_RUNNING_CORE 31 #define BOARD_RUNNING_CORE HPM_CORE0 32 #endif 33 34 /* uart section */ 35 #ifndef BOARD_APP_UART_BASE 36 #define BOARD_APP_UART_BASE HPM_UART13 37 #define BOARD_APP_UART_IRQ IRQn_UART13 38 #define BOARD_APP_UART_BAUDRATE (115200UL) 39 #define BOARD_APP_UART_CLK_NAME clock_uart13 40 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX 41 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX 42 #endif 43 44 /* uart rx idle demo section */ 45 #define BOARD_UART_IDLE BOARD_APP_UART_BASE 46 #define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ 47 #define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME 48 #define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ 49 #define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ 50 51 #define BOARD_UART_IDLE_TRGM HPM_TRGM2 52 #define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 53 #define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 54 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 55 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI 56 57 #define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 58 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 59 #define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 60 #define BOARD_UART_IDLE_GPTMR_CMP_CH 0 61 #define BOARD_UART_IDLE_GPTMR_CAP_CH 2 62 63 /* uart microros sample section */ 64 #define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE 65 #define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ 66 #define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 67 68 /* rtthread-nano finsh section */ 69 #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE 70 71 /* usb cdc acm uart section */ 72 #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE 73 #define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 74 #define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ 75 #define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ 76 77 /* modbus sample section */ 78 #define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE 79 #define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME 80 #define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ 81 #define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ 82 83 /* uart lin sample section */ 84 #define BOARD_UART_LIN BOARD_APP_UART_BASE 85 #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ 86 #define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME 87 #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ 88 #define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ 89 90 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 91 #ifndef BOARD_CONSOLE_TYPE 92 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART 93 #endif 94 95 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART 96 #ifndef BOARD_CONSOLE_UART_BASE 97 #if BOARD_RUNNING_CORE == HPM_CORE0 98 #define BOARD_CONSOLE_UART_BASE HPM_UART0 99 #define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 100 #define BOARD_CONSOLE_UART_IRQ IRQn_UART0 101 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX 102 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX 103 #else 104 #define BOARD_CONSOLE_UART_BASE HPM_UART13 105 #define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 106 #define BOARD_CONSOLE_UART_IRQ IRQn_UART13 107 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX 108 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX 109 #endif 110 #endif 111 #define BOARD_CONSOLE_UART_BAUDRATE (115200UL) 112 #endif 113 #endif 114 115 /* sdram section */ 116 #define BOARD_SDRAM_ADDRESS (0x40000000UL) 117 #define BOARD_SDRAM_SIZE (32 * SIZE_1MB) 118 #define BOARD_SDRAM_CS FEMC_SDRAM_CS0 119 #define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS 120 #define BOARD_SDRAM_REFRESH_COUNT (8192UL) 121 #define BOARD_SDRAM_REFRESH_IN_MS (64UL) 122 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) 123 124 #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) 125 #define BOARD_FLASH_SIZE (16 << 20) 126 127 #define BOARD_FEMC_DQS_FLOATING 1 128 129 /* lcd section */ 130 #define BOARD_LCD_BASE HPM_LCDC 131 #define BOARD_LCD_IRQ IRQn_LCDC_D0 132 #define BOARD_LCD_RESET_GPIO_BASE HPM_GPIO0 133 #define BOARD_LCD_RESET_GPIO_INDEX GPIO_DO_GPIOB 134 #define BOARD_LCD_RESET_GPIO_PIN 16 135 #define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 136 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB 137 #define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 138 #define BOARD_LCD_POWER_EN_GPIO_BASE HPM_GPIO0 139 #define BOARD_LCD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOZ 140 #define BOARD_LCD_POWER_EN_GPIO_PIN 00 141 142 /* i2c section */ 143 #define BOARD_APP_I2C_BASE HPM_I2C0 144 #define BOARD_APP_I2C_IRQ IRQn_I2C0 145 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 146 #define BOARD_APP_I2C_DMA HPM_HDMA 147 #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX 148 #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 149 150 #define BOARD_CAM_I2C_BASE HPM_I2C0 151 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 152 #define BOARD_SUPPORT_CAM_RESET 153 #define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 154 #define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY 155 #define BOARD_CAM_RST_GPIO_PIN 5 156 157 #define BOARD_CAP_I2C_BASE (HPM_I2C0) 158 #define BOARD_CAP_I2C_CLK_NAME clock_i2c0 159 #define BOARD_CAP_RST_GPIO (HPM_GPIO0) 160 #define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) 161 #define BOARD_CAP_RST_GPIO_PIN (9) 162 #define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) 163 #define BOARD_CAP_INTR_GPIO (HPM_GPIO0) 164 #define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) 165 #define BOARD_CAP_INTR_GPIO_PIN (8) 166 #define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) 167 #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) 168 #define BOARD_CAP_I2C_SDA_GPIO_PIN (10) 169 #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) 170 #define BOARD_CAP_I2C_CLK_GPIO_PIN (11) 171 172 /* ACMP desction */ 173 #define BOARD_ACMP HPM_ACMP 174 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 175 #define BOARD_ACMP_IRQ IRQn_ACMP_1 176 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ 177 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ 178 179 /* dma section */ 180 #define BOARD_APP_XDMA HPM_XDMA 181 #define BOARD_APP_HDMA HPM_HDMA 182 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 183 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 184 #define BOARD_APP_DMAMUX HPM_DMAMUX 185 186 /* gptmr section */ 187 #define BOARD_GPTMR HPM_GPTMR4 188 #define BOARD_GPTMR_IRQ IRQn_GPTMR4 189 #define BOARD_GPTMR_CHANNEL 1 190 #define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_1 191 #define BOARD_GPTMR_CLK_NAME clock_gptmr4 192 #define BOARD_GPTMR_PWM HPM_GPTMR5 193 #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_2 194 #define BOARD_GPTMR_PWM_CHANNEL 2 195 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 196 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 197 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 198 #define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 199 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 200 201 /* gpio section */ 202 #define BOARD_R_GPIO_CTRL HPM_GPIO0 203 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB 204 #define BOARD_R_GPIO_PIN 11 205 #define BOARD_G_GPIO_CTRL HPM_GPIO0 206 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB 207 #define BOARD_G_GPIO_PIN 12 208 #define BOARD_B_GPIO_CTRL HPM_GPIO0 209 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB 210 #define BOARD_B_GPIO_PIN 13 211 212 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 213 214 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB 215 #define BOARD_LED_GPIO_PIN 12 216 #define BOARD_LED_OFF_LEVEL 0 217 #define BOARD_LED_ON_LEVEL 1 218 219 #define BOARD_LED_TOGGLE_RGB 1 220 221 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ 222 #define BOARD_APP_GPIO_PIN 2 223 224 /* pinmux section */ 225 #define USING_GPIO0_FOR_GPIOZ 226 #ifndef USING_GPIO0_FOR_GPIOZ 227 #define BOARD_APP_GPIO_CTRL HPM_BGPIO 228 #define BOARD_APP_GPIO_IRQ IRQn_BGPIO 229 #else 230 #define BOARD_APP_GPIO_CTRL HPM_GPIO0 231 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z 232 #endif 233 234 /* gpiom section */ 235 #define BOARD_APP_GPIOM_BASE HPM_GPIOM 236 #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO 237 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast 238 239 /* spi section */ 240 #define BOARD_APP_SPI_BASE HPM_SPI2 241 #define BOARD_APP_SPI_CLK_NAME clock_spi2 242 #define BOARD_APP_SPI_IRQ IRQn_SPI2 243 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) 244 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) 245 #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) 246 #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX 247 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX 248 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 249 #define BOARD_SPI_CS_PIN IOC_PAD_PE31 250 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) 251 252 /* Flash section */ 253 #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) 254 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) 255 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) 256 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) 257 258 /* lcd section */ 259 260 #ifndef BOARD_LCD_WIDTH 261 #define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH 262 #endif 263 #ifndef BOARD_LCD_HEIGHT 264 #define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT 265 #endif 266 267 /* pdma section */ 268 #define BOARD_PDMA_BASE HPM_PDMA 269 270 /* i2s section */ 271 #define BOARD_APP_I2S_BASE HPM_I2S0 272 #define BOARD_APP_I2S_DATA_LINE (2U) 273 #define BOARD_APP_I2S_CLK_NAME clock_i2s0 274 #define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX 275 #define BOARD_APP_I2S_IRQ IRQn_I2S0 276 #define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 277 #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 278 #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) 279 #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) 280 281 /* enet section */ 282 #define BOARD_ENET_COUNT (2U) 283 #define BOARD_ENET_PPS HPM_ENET0 284 #define BOARD_ENET_PPS_IDX enet_pps_0 285 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 286 287 #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii 288 #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 289 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF 290 #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) 291 #define BOARD_ENET_RGMII HPM_ENET0 292 #define BOARD_ENET_RGMII_TX_DLY (0U) 293 #define BOARD_ENET_RGMII_RX_DLY (7U) 294 #define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) 295 #define BOARD_ENET_RGMII_PPS0_PINOUT (1) 296 297 #define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii 298 #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 299 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE 300 #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) 301 #define BOARD_ENET_RMII HPM_ENET1 302 #define BOARD_ENET_RMII_INT_REF_CLK (1U) 303 #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) 304 #define BOARD_ENET_RMII_PPS0_PINOUT (0) 305 306 #define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ 307 #define BOARD_ENET0_INT_REF_CLK (0U) 308 #define BOARD_ENET0_PHY_RST_TIME (30) 309 #if BOARD_ENET0_INF 310 #define BOARD_ENET0_TX_DLY (0U) 311 #define BOARD_ENET0_RX_DLY (7U) 312 #endif 313 #if __USE_ENET_PTP 314 #define BOARD_ENET0_PTP_CLOCK (clock_ptp0) 315 #endif 316 317 #define BOARD_ENET1_RST_GPIO HPM_GPIO0 318 #define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE 319 #define BOARD_ENET1_RST_GPIO_PIN (26U) 320 321 #define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ 322 #define BOARD_ENET1_INT_REF_CLK (1U) 323 #define BOARD_ENET1_PHY_RST_TIME (30) 324 325 #if BOARD_ENET1_INF 326 #define BOARD_ENET1_TX_DLY (0U) 327 #define BOARD_ENET1_RX_DLY (0U) 328 #endif 329 330 #if __USE_ENET_PTP 331 #define BOARD_ENET1_PTP_CLOCK (clock_ptp1) 332 #endif 333 334 335 /* ADC section */ 336 #define BOARD_APP_ADC12_NAME "ADC0" 337 #define BOARD_APP_ADC12_BASE HPM_ADC0 338 #define BOARD_APP_ADC12_IRQn IRQn_ADC0 339 #define BOARD_APP_ADC12_CH_1 (11U) 340 #define BOARD_APP_ADC12_CLK_NAME (clock_adc0) 341 342 #define BOARD_APP_ADC16_NAME "ADC3" 343 #define BOARD_APP_ADC16_BASE HPM_ADC3 344 #define BOARD_APP_ADC16_IRQn IRQn_ADC3 345 #define BOARD_APP_ADC16_CH_1 (2U) 346 #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) 347 348 #define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 349 #define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 350 #define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 351 #define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI 352 #define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 353 354 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 355 #define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 356 #define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 357 #define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI 358 #define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 359 360 #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A 361 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A 362 363 /* CAN section */ 364 #define BOARD_APP_CAN_BASE HPM_CAN0 365 #define BOARD_APP_CAN_IRQn IRQn_CAN0 366 367 /* 368 * timer for board delay 369 */ 370 #define BOARD_DELAY_TIMER (HPM_GPTMR7) 371 #define BOARD_DELAY_TIMER_CH 0 372 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) 373 374 #define BOARD_CALLBACK_TIMER (HPM_GPTMR7) 375 #define BOARD_CALLBACK_TIMER_CH 1 376 #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 377 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) 378 379 /* SDXC section */ 380 #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) 381 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) 382 #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) 383 #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) 384 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 385 #define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (1) 386 #define BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO (1) 387 #define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (0) 388 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 389 #define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) 390 #if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) 391 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 392 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ 393 #define BOARD_APP_SDCARD_CARD_DETECTION_GPIO HPM_GPIO0 394 #define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX GPIO_DI_GPIOD 395 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 15 396 #endif 397 #if defined(BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO) && (BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO == 1) 398 #define BOARD_APP_SDCARD_POWER_EN_GPIO_BASE HPM_GPIO0 399 #define BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOC 400 #define BOARD_APP_SDCARD_POWER_EN_GPIO_PIN 20 401 #define BOARD_APP_SDCARD_POWER_SWITCH_PIN IOC_PAD_PC20 402 #define BOARD_APP_SDCARD_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ 403 #endif 404 405 #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) 406 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) 407 #define BOARD_APP_EMMC_SUPPORT_1V8 (0) 408 #define BOARD_APP_EMMC_SUPPORT_4BIT (1) 409 #define BOARD_APP_EMMC_SUPPORT_POWER_SWITCH (1) 410 #define BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO (1) 411 #define BOARD_APP_EMMC_HOST_USING_IRQ (0) 412 #if defined(BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO) && (BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO == 1) 413 #define BOARD_APP_EMMC_POWER_SWITCH_PIN IOC_PAD_PC20 414 #define BOARD_APP_EMMC_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ 415 #endif 416 417 /* USB section */ 418 #define BOARD_USB0_ID_PORT (HPM_GPIO0) 419 #define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) 420 #define BOARD_USB0_ID_GPIO_PIN (10) 421 422 #define BOARD_USB0_OC_PORT (HPM_GPIO0) 423 #define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) 424 #define BOARD_USB0_OC_GPIO_PIN (8) 425 426 #define BOARD_USB1_ID_PORT (HPM_GPIO0) 427 #define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) 428 #define BOARD_USB1_ID_GPIO_PIN (7) 429 430 #define BOARD_USB1_OC_PORT (HPM_GPIO0) 431 #define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) 432 #define BOARD_USB1_OC_GPIO_PIN (5) 433 434 /*BLDC pwm*/ 435 436 /*PWM define*/ 437 #define BOARD_BLDCPWM HPM_PWM2 438 #define BOARD_BLDC_UH_PWM_OUTPIN (0U) 439 #define BOARD_BLDC_UL_PWM_OUTPIN (1U) 440 #define BOARD_BLDC_VH_PWM_OUTPIN (2U) 441 #define BOARD_BLDC_VL_PWM_OUTPIN (3U) 442 #define BOARD_BLDC_WH_PWM_OUTPIN (4U) 443 #define BOARD_BLDC_WL_PWM_OUTPIN (5U) 444 #define BOARD_BLDCPWM_TRGM HPM_TRGM2 445 #define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 446 #define BOARD_BLDCPWM_CMP_INDEX_0 (0U) 447 #define BOARD_BLDCPWM_CMP_INDEX_1 (1U) 448 #define BOARD_BLDCPWM_CMP_INDEX_2 (2U) 449 #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) 450 #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) 451 #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) 452 #define BOARD_BLDCPWM_CMP_INDEX_6 (6U) 453 #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) 454 #define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) 455 456 /*HALL define*/ 457 458 #define BOARD_BLDC_HALL_BASE HPM_HALL2 459 #define BOARD_BLDC_HALL_TRGM HPM_TRGM2 460 #define BOARD_BLDC_HALL_IRQ IRQn_HALL2 461 #define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 462 #define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 463 #define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 464 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) 465 466 /*QEI*/ 467 468 #define BOARD_BLDC_QEI_BASE HPM_QEI2 469 #define BOARD_BLDC_QEI_IRQ IRQn_QEI2 470 #define BOARD_BLDC_QEI_TRGM HPM_TRGM2 471 #define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 472 #define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 473 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) 474 #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 475 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) 476 477 /*HFI define*/ 478 #define MOTOR0_HFI_SPD (0.5) 479 #define MOTOR0_HFI_KP (40) 480 481 /*Timer define*/ 482 483 #define BOARD_TMR_1MS HPM_GPTMR2 484 #define BOARD_TMR_1MS_CH 0 485 #define BOARD_TMR_1MS_CMP 0 486 #define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 487 #define BOARD_TMR_1MS_RELOAD (100000U) 488 489 #define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS 490 #define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH 491 #define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP 492 #define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ 493 #define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD 494 495 /*adc*/ 496 #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 497 #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 498 #define BOARD_BLDC_ADC_V_BASE HPM_ADC1 499 #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 500 #define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete 501 502 #define BOARD_BLDC_ADC_CH_U (7U) 503 #define BOARD_BLDC_ADC_CH_V (10U) 504 #define BOARD_BLDC_ADC_CH_W (11U) 505 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 506 #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) 507 #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A 508 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) 509 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) 510 #define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF 511 #define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A 512 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 513 514 /* APP PWM */ 515 #define BOARD_APP_PWM HPM_PWM2 516 #define BOARD_APP_PWM_CLOCK_NAME clock_mot2 517 #define BOARD_APP_PWM_OUT1 0 518 #define BOARD_APP_PWM_OUT2 1 519 #define BOARD_APP_TRGM HPM_TRGM2 520 #define BOARD_APP_PWM_IRQ IRQn_PWM2 521 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI 522 523 /* RGB LED Section */ 524 #define BOARD_RED_PWM_IRQ IRQn_PWM1 525 #define BOARD_RED_PWM HPM_PWM1 526 #define BOARD_RED_PWM_OUT 8 527 #define BOARD_RED_PWM_CMP 8 528 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true 529 #define BOARD_RED_PWM_CLOCK_NAME clock_mot1 530 531 #define BOARD_GREEN_PWM_IRQ IRQn_PWM0 532 #define BOARD_GREEN_PWM HPM_PWM0 533 #define BOARD_GREEN_PWM_OUT 8 534 #define BOARD_GREEN_PWM_CMP 8 535 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true 536 #define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 537 538 #define BOARD_BLUE_PWM_IRQ IRQn_PWM1 539 #define BOARD_BLUE_PWM HPM_PWM1 540 #define BOARD_BLUE_PWM_OUT 9 541 #define BOARD_BLUE_PWM_CMP 9 542 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true 543 #define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 544 545 #define BOARD_RGB_RED 0 546 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) 547 #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) 548 549 #define BOARD_CPU_FREQ (648000000UL) 550 551 #define BOARD_APP_DISPLAY_CLOCK clock_display 552 553 #ifndef BOARD_SHOW_CLOCK 554 #define BOARD_SHOW_CLOCK 1 555 #endif 556 #ifndef BOARD_SHOW_BANNER 557 #define BOARD_SHOW_BANNER 1 558 #endif 559 560 /* FreeRTOS Definitions */ 561 #define BOARD_FREERTOS_TIMER HPM_GPTMR6 562 #define BOARD_FREERTOS_TIMER_CHANNEL 1 563 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 564 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 565 566 /* Threadx Definitions */ 567 #define BOARD_THREADX_TIMER HPM_GPTMR6 568 #define BOARD_THREADX_TIMER_CHANNEL 1 569 #define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 570 #define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 571 572 /* Tamper Section */ 573 #define BOARD_TAMP_ACTIVE_CH 8 574 #define BOARD_TAMP_LOW_LEVEL_CH 10 575 576 #if defined(__cplusplus) 577 extern "C" { 578 #endif /* __cplusplus */ 579 580 typedef void (*board_timer_cb)(void); 581 582 void board_init(void); 583 void board_init_console(void); 584 585 void board_init_core1(void); 586 587 void board_init_uart(UART_Type *ptr); 588 void board_init_i2c(I2C_Type *ptr); 589 void board_init_lcd(void); 590 void board_lcd_backlight(bool is_on); 591 void board_panel_para_to_lcdc(lcdc_config_t *config); 592 void board_init_can(CAN_Type *ptr); 593 594 uint32_t board_init_femc_clock(void); 595 596 void board_init_sdram_pins(void); 597 void board_init_gpio_pins(void); 598 void board_init_spi_pins(SPI_Type *ptr); 599 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); 600 void board_write_spi_cs(uint32_t pin, uint8_t state); 601 void board_init_led_pins(void); 602 603 /* cap touch */ 604 void board_init_cap_touch(void); 605 606 void board_led_write(uint8_t state); 607 void board_led_toggle(void); 608 609 void board_fpga_power_enable(void); 610 611 void board_init_cam_pins(void); 612 void board_write_cam_rst(uint8_t state); 613 /* Initialize SoC overall clocks */ 614 void board_init_clock(void); 615 616 /* Initialize the UART clock */ 617 uint32_t board_init_uart_clock(UART_Type *ptr); 618 619 /* Initialize the CAM(camera) dot clock */ 620 uint32_t board_init_cam_clock(CAM_Type *ptr); 621 622 /* Initialize the LCD pixel clock */ 623 uint32_t board_init_lcd_clock(void); 624 625 uint32_t board_init_spi_clock(SPI_Type *ptr); 626 627 uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); 628 629 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); 630 631 uint32_t board_init_can_clock(CAN_Type *ptr); 632 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); 633 hpm_stat_t board_set_audio_pll_clock(uint32_t freq); 634 635 void board_init_i2s_pins(I2S_Type *ptr); 636 uint32_t board_init_i2s_clock(I2S_Type *ptr); 637 uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); 638 uint32_t board_init_pdm_clock(void); 639 uint32_t board_init_dao_clock(void); 640 641 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); 642 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); 643 void board_sd_power_switch(SDXC_Type *ptr, bool on_off); 644 bool board_sd_detect_card(SDXC_Type *ptr); 645 646 void board_init_dao_pins(void); 647 648 void board_init_adc12_pins(void); 649 void board_init_adc16_pins(void); 650 651 void board_init_usb_pins(void); 652 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); 653 654 void board_init_enet_pps_pins(ENET_Type *ptr); 655 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); 656 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); 657 hpm_stat_t board_init_enet_pins(ENET_Type *ptr); 658 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); 659 hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); 660 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); 661 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); 662 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); 663 664 #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT 665 hpm_stat_t board_init_multiple_enet_pins(void); 666 hpm_stat_t board_init_multiple_enet_clock(void); 667 hpm_stat_t board_reset_multiple_enet_phy(void); 668 hpm_stat_t board_init_enet_phy(ENET_Type *ptr); 669 ENET_Type *board_get_enet_base(uint8_t idx); 670 uint8_t board_get_enet_phy_itf(uint8_t idx); 671 void board_get_enet_phy_status(uint8_t idx, void *status); 672 #endif 673 674 /* 675 * @brief Initialize PMP and PMA for but not limited to the following purposes: 676 * -- non-cacheable memory initialization 677 */ 678 void board_init_pmp(void); 679 680 void board_delay_ms(uint32_t ms); 681 void board_delay_us(uint32_t us); 682 683 void board_timer_create(uint32_t ms, board_timer_cb cb); 684 685 void board_init_rgb_pwm_pins(void); 686 void board_enable_output_rgb_led(uint8_t color); 687 void board_disable_output_rgb_led(uint8_t color); 688 689 /* 690 * Keep mchtmr clock on low power mode 691 */ 692 void board_ungate_mchtmr_at_lp_mode(void); 693 694 /* 695 * Get PWM output level of onboard LED 696 */ 697 uint8_t board_get_led_pwm_off_level(void); 698 699 /* 700 * Get GPIO pin level of onboard LED 701 */ 702 uint8_t board_get_led_gpio_off_level(void); 703 704 #if defined(__cplusplus) 705 } 706 #endif /* __cplusplus */ 707 #endif /* _HPM_BOARD_H */ 708