1# Copyright (c) 2021 HPMicro
2# SPDX-License-Identifier: BSD-3-Clause
3#
4
5
6set _CHIP hpm6750
7set _CPUTAPID 0x1000563D
8jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
9
10set _TARGET0 $_CHIP.cpu0
11target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
12
13$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
14
15targets $_TARGET0
16
17proc dmi_write {reg value} {
18    $::_TARGET0 riscv dmi_write ${reg} ${value}
19}
20
21proc dmi_read {reg} {
22    set v [$::_TARGET0 riscv dmi_read ${reg}]
23    return ${v}
24}
25proc dmi_write_memory {addr value} {
26    dmi_write 0x39 ${addr}
27    dmi_write 0x3C ${value}
28}
29
30proc dmi_read_memory {addr} {
31    set sbcs [expr 0x100000 | [dmi_read 0x38]]
32    dmi_write 0x38 ${sbcs}
33    dmi_write 0x39 ${addr}
34    set value [dmi_read 0x3C]
35    return ${value}
36}
37
38proc release_core1 {} {
39
40    set chip_rev [dmi_read_memory 0x2001FF00]
41
42    if {$chip_rev != 0x56010100 } {
43        # set start point for core1
44        dmi_write_memory 0xF4002C08 0x20016284
45    } else {
46        dmi_write_memory 0xF4002C08 0x2001660c
47    }
48
49    # set boot flag for core1
50    dmi_write_memory 0xF4002C0C 0xC1BEF1A9
51
52    # release core1
53    dmi_write_memory 0xF4002C00 0x1000
54}
55
56set _TARGET1 $_CHIP.cpu1
57target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
58$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
59
60$_TARGET1 configure -event examine-start {
61    release_core1
62}
63
64$_TARGET1 configure -event reset-deassert-pre {
65    $::_TARGET0 arp_poll
66    release_core1
67}
68