1 /* 2 * Copyright (c) 2022, sakumisu 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef CHERRYUSB_CONFIG_H 7 #define CHERRYUSB_CONFIG_H 8 9 #include <rtthread.h> 10 #include "hpm_soc_feature.h" 11 12 /* ================ USB common Configuration ================ */ 13 14 #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) 15 16 #ifndef CONFIG_USB_DBG_LEVEL 17 #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO 18 #endif 19 20 /* Enable print with color */ 21 #define CONFIG_USB_PRINTF_COLOR_ENABLE 22 23 #define CONFIG_USB_DCACHE_ENABLE 24 25 /* data align size when use dma or use dcache */ 26 #ifdef CONFIG_USB_DCACHE_ENABLE 27 #define CONFIG_USB_ALIGN_SIZE HPM_L1C_CACHELINE_SIZE // 32 or 64 28 #else 29 #define CONFIG_USB_ALIGN_SIZE 4 30 #endif 31 32 /* attribute data into no cache ram */ 33 #define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) 34 35 /* use usb_memcpy default for high performance but cost more flash memory. 36 * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. 37 */ 38 // #define CONFIG_USB_MEMCPY_DISABLE 39 40 /* ================= USB Device Stack Configuration ================ */ 41 42 /* Ep0 in and out transfer buffer */ 43 #ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN 44 #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 45 #endif 46 47 /* Setup packet log for debug */ 48 // #define CONFIG_USBDEV_SETUP_LOG_PRINT 49 50 /* Send ep0 in data from user buffer instead of copying into ep0 reqdata 51 * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE 52 */ 53 // #define CONFIG_USBDEV_EP0_INDATA_NO_COPY 54 55 /* Check if the input descriptor is correct */ 56 // #define CONFIG_USBDEV_DESC_CHECK 57 58 /* Enable test mode */ 59 // #define CONFIG_USBDEV_TEST_MODE 60 61 /* enable advance desc register api */ 62 #define CONFIG_USBDEV_ADVANCE_DESC 63 64 /* move ep0 setup handler from isr to thread */ 65 // #define CONFIG_USBDEV_EP0_THREAD 66 67 #ifndef CONFIG_USBDEV_EP0_PRIO 68 #define CONFIG_USBDEV_EP0_PRIO 4 69 #endif 70 71 #ifndef CONFIG_USBDEV_EP0_STACKSIZE 72 #define CONFIG_USBDEV_EP0_STACKSIZE 2048 73 #endif 74 75 #ifndef CONFIG_USBDEV_MSC_MAX_LUN 76 #define CONFIG_USBDEV_MSC_MAX_LUN 1 77 #endif 78 79 #ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE 80 #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 81 #endif 82 83 #ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING 84 #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" 85 #endif 86 87 #ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING 88 #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" 89 #endif 90 91 #ifndef CONFIG_USBDEV_MSC_VERSION_STRING 92 #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" 93 #endif 94 95 /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ 96 // #define CONFIG_USBDEV_MSC_POLLING 97 98 /* move msc read & write from isr to thread */ 99 // #define CONFIG_USBDEV_MSC_THREAD 100 101 #ifndef CONFIG_USBDEV_MSC_PRIO 102 #define CONFIG_USBDEV_MSC_PRIO 4 103 #endif 104 105 #ifndef CONFIG_USBDEV_MSC_STACKSIZE 106 #define CONFIG_USBDEV_MSC_STACKSIZE 2048 107 #endif 108 109 #ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE 110 #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 111 #endif 112 113 #ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS 114 #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 115 #endif 116 117 #ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME 118 #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 119 #endif 120 121 #define CONFIG_USBDEV_MTP_THREAD 122 123 #ifndef CONFIG_USBDEV_MTP_PRIO 124 #define CONFIG_USBDEV_MTP_PRIO 4 125 #endif 126 127 #ifndef CONFIG_USBDEV_MTP_STACKSIZE 128 #define CONFIG_USBDEV_MTP_STACKSIZE 4096 129 #endif 130 131 #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 132 #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 133 #endif 134 135 /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ 136 #ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 137 #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 138 #endif 139 140 #ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID 141 #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff 142 #endif 143 144 #ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC 145 #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" 146 #endif 147 148 #define CONFIG_USBDEV_RNDIS_USING_LWIP 149 #define CONFIG_USBDEV_CDC_ECM_USING_LWIP 150 151 /* ================ USB HOST Stack Configuration ================== */ 152 153 #define CONFIG_USBHOST_MAX_RHPORTS 1 154 #define CONFIG_USBHOST_MAX_EXTHUBS 1 155 #define CONFIG_USBHOST_MAX_EHPORTS 4 156 #define CONFIG_USBHOST_MAX_INTERFACES 8 157 #define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 158 #define CONFIG_USBHOST_MAX_ENDPOINTS 4 159 160 #define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 161 #define CONFIG_USBHOST_MAX_HID_CLASS 4 162 #define CONFIG_USBHOST_MAX_MSC_CLASS 2 163 #define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 164 #define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 165 166 #define CONFIG_USBHOST_DEV_NAMELEN 16 167 168 #ifndef CONFIG_USBHOST_PSC_PRIO 169 #define CONFIG_USBHOST_PSC_PRIO 0 170 #endif 171 #ifndef CONFIG_USBHOST_PSC_STACKSIZE 172 #define CONFIG_USBHOST_PSC_STACKSIZE 2048 173 #endif 174 175 //#define CONFIG_USBHOST_GET_STRING_DESC 176 177 // #define CONFIG_USBHOST_MSOS_ENABLE 178 #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE 179 #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 180 #endif 181 182 /* Ep0 max transfer buffer */ 183 #ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN 184 #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 185 #endif 186 187 #ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 188 #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 189 #endif 190 191 #ifndef CONFIG_USBHOST_MSC_TIMEOUT 192 #define CONFIG_USBHOST_MSC_TIMEOUT 5000 193 #endif 194 195 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 196 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 197 */ 198 #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE 199 #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) 200 #endif 201 202 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 203 #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE 204 #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) 205 #endif 206 207 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 208 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 209 */ 210 #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE 211 #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) 212 #endif 213 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 214 #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE 215 #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) 216 #endif 217 218 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 219 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 220 */ 221 #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE 222 #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) 223 #endif 224 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 225 #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE 226 #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) 227 #endif 228 229 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 230 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 231 */ 232 #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE 233 #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) 234 #endif 235 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 236 #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE 237 #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) 238 #endif 239 240 #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 241 // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG 242 243 #ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE 244 #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 245 #endif 246 #ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE 247 #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 248 #endif 249 250 /* ================ USB Device Port Configuration ================*/ 251 252 #ifndef CONFIG_USBDEV_MAX_BUS 253 #define CONFIG_USBDEV_MAX_BUS USB_SOC_MAX_COUNT // for now, bus num must be 1 except hpm ip 254 #endif 255 256 #ifndef CONFIG_USBDEV_EP_NUM 257 #define CONFIG_USBDEV_EP_NUM USB_SOC_DCD_MAX_ENDPOINT_COUNT 258 #endif 259 260 // #define CONFIG_USBDEV_SOF_ENABLE 261 262 /* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */ 263 #define CONFIG_USB_HS 264 265 /* ---------------- FSDEV Configuration ---------------- */ 266 //#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference 267 268 /* ---------------- DWC2 Configuration ---------------- */ 269 /* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for 270 * status information) + (2 * number of OUT endpoints) + 1 for Global NAK 271 */ 272 // #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) 273 /* IN Endpoints Max packet Size / 4 */ 274 // #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) 275 // #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4) 276 // #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) 277 // #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) 278 // #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) 279 // #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) 280 // #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) 281 // #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) 282 // #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) 283 284 // #define CONFIG_USB_DWC2_DMA_ENABLE 285 286 /* ---------------- MUSB Configuration ---------------- */ 287 // #define CONFIG_USB_MUSB_SUNXI 288 289 /* ================ USB Host Port Configuration ==================*/ 290 #ifndef CONFIG_USBHOST_MAX_BUS 291 #define CONFIG_USBHOST_MAX_BUS USB_SOC_MAX_COUNT 292 #endif 293 294 #ifndef CONFIG_USBHOST_PIPE_NUM 295 #define CONFIG_USBHOST_PIPE_NUM 10 296 #endif 297 298 /* ---------------- EHCI Configuration ---------------- */ 299 300 #define CONFIG_USB_EHCI_HCCR_OFFSET (0x100) 301 #define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 302 #define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM 303 #define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3) 304 #define CONFIG_USB_EHCI_ITD_NUM 4 305 // #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE 306 // #define CONFIG_USB_EHCI_CONFIGFLAG 307 // #define CONFIG_USB_EHCI_ISO 308 // #define CONFIG_USB_EHCI_WITH_OHCI 309 // #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE 310 311 /* ---------------- OHCI Configuration ---------------- */ 312 #define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) 313 #define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM 314 #define CONFIG_USB_OHCI_TD_NUM 3 315 // #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE 316 317 /* ---------------- XHCI Configuration ---------------- */ 318 #define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) 319 320 /* ---------------- DWC2 Configuration ---------------- */ 321 /* largest non-periodic USB packet used / 4 */ 322 // #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) 323 /* largest periodic USB packet used / 4 */ 324 // #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) 325 /* 326 * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + 327 * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario 328 */ 329 // #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE)) 330 331 /* ---------------- MUSB Configuration ---------------- */ 332 // #define CONFIG_USB_MUSB_SUNXI 333 334 #ifndef usb_phyaddr2ramaddr 335 #define usb_phyaddr2ramaddr(addr) (addr) 336 #endif 337 338 #ifndef usb_ramaddr2phyaddr 339 #define usb_ramaddr2phyaddr(addr) (addr) 340 #endif 341 342 #define CONFIG_USB_EHCI_HPMICRO 1 343 344 #endif 345