1# Copyright 2021 HPMicro
2# SPDX-License-Identifier: BSD-3-Clause
3#
4# openocd flash driver argument:
5#   - ARG7:
6#       [31:28] Flash probe type
7#         0 - SFDP SDR / 1 - SFDP DDR
8#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
9#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
10#         6 - OctaBus DDR (SPI -> OPI DDR)
11#         8 - Xccela DDR (SPI -> OPI DDR)
12#         10 - EcoXiP DDR (SPI -> OPI DDR)
13#       [27:24] Command Pads after Power-on Reset
14#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
15#       [23:20] Command Pads after Configuring FLASH
16#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
17#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
18#         0 - Not needed
19#         1 - QE bit is at bit 6 in Status Register 1
20#         2 - QE bit is at bit1 in Status Register 2
21#         3 - QE bit is at bit7 in Status Register 2
22#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
23#       [15:8] Dummy cycles
24#         0 - Auto-probed / detected / default value
25#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
26#       [7:4] Misc.
27#         0 - Not used
28#         1 - SPI mode
29#         2 - Internal loopback
30#         3 - External DQS
31#       [3:0] Frequency option
32#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
33#   - ARG8:
34#       [31:20]  Reserved
35#       [19:16] IO voltage
36#         0 - 3V / 1 - 1.8V
37#       [15:12] Pin group
38#         0 - 1st group / 1 - 2nd group
39#       [11:8] Connection selection
40#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
41#       [7:0] Drive Strength
42#         0 - Default value
43
44# xpi0 configs
45#   - flash driver:     hpm_xpi
46#   - flash ctrl index: 0xF3040000
47#   - base address:     0x80000000
48#   - flash size:       0x1000000
49#   - flash option0:    0x7
50flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7
51
52proc init_clock {} {
53    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
54    $::_TARGET0 riscv dmi_write 0x3C 0x1
55
56    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
57    $::_TARGET0 riscv dmi_write 0x3C 0x2
58
59    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
60    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
61
62    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
63    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
64
65    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
66    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
67
68    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
69    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
70    echo "clocks has been enabled!"
71}
72
73proc init_sdram { } {
74# configure dram frequency
75# 133Mhz pll1_clk0: 266Mhz divide by 2
76    #$::_TARGET0 riscv dmi_write 0x39 0xF4001820
77    $::_TARGET0 riscv dmi_write 0x3C 0x201
78# 166Mhz pll2_clk0: 333Mhz divide by 2
79    $::_TARGET0 riscv dmi_write 0x39 0xF4001820
80    $::_TARGET0 riscv dmi_write 0x3C 0x401
81
82    # PD13
83    $::_TARGET0 riscv dmi_write 0x39 0xF4040368
84    $::_TARGET0 riscv dmi_write 0x3C 0xC
85    # PD12
86    $::_TARGET0 riscv dmi_write 0x39 0xF4040360
87    $::_TARGET0 riscv dmi_write 0x3C 0xC
88    # PD10
89    $::_TARGET0 riscv dmi_write 0x39 0xF4040350
90    $::_TARGET0 riscv dmi_write 0x3C 0xC
91    # PD09
92    $::_TARGET0 riscv dmi_write 0x39 0xF4040348
93    $::_TARGET0 riscv dmi_write 0x3C 0xC
94    # PD08
95    $::_TARGET0 riscv dmi_write 0x39 0xF4040340
96    $::_TARGET0 riscv dmi_write 0x3C 0xC
97    # PD07
98    $::_TARGET0 riscv dmi_write 0x39 0xF4040338
99    $::_TARGET0 riscv dmi_write 0x3C 0xC
100    # PD06
101    $::_TARGET0 riscv dmi_write 0x39 0xF4040330
102    $::_TARGET0 riscv dmi_write 0x3C 0xC
103    # PD05
104    $::_TARGET0 riscv dmi_write 0x39 0xF4040328
105    $::_TARGET0 riscv dmi_write 0x3C 0xC
106    # PD04
107    $::_TARGET0 riscv dmi_write 0x39 0xF4040320
108    $::_TARGET0 riscv dmi_write 0x3C 0xC
109    # PD03
110    $::_TARGET0 riscv dmi_write 0x39 0xF4040318
111    $::_TARGET0 riscv dmi_write 0x3C 0xC
112    # PD02
113    $::_TARGET0 riscv dmi_write 0x39 0xF4040310
114    $::_TARGET0 riscv dmi_write 0x3C 0xC
115    # PD01
116    $::_TARGET0 riscv dmi_write 0x39 0xF4040308
117    $::_TARGET0 riscv dmi_write 0x3C 0xC
118    # PD00
119    $::_TARGET0 riscv dmi_write 0x39 0xF4040300
120    $::_TARGET0 riscv dmi_write 0x3C 0xC
121    # PC29
122    $::_TARGET0 riscv dmi_write 0x39 0xF40402E8
123    $::_TARGET0 riscv dmi_write 0x3C 0xC
124    # PC28
125    $::_TARGET0 riscv dmi_write 0x39 0xF40402E0
126    $::_TARGET0 riscv dmi_write 0x3C 0xC
127    # PC27
128    $::_TARGET0 riscv dmi_write 0x39 0xF40402D8
129    $::_TARGET0 riscv dmi_write 0x3C 0xC
130
131    # PC22
132    $::_TARGET0 riscv dmi_write 0x39 0xF40402B0
133    $::_TARGET0 riscv dmi_write 0x3C 0xC
134    # PC21
135    $::_TARGET0 riscv dmi_write 0x39 0xF40402A8
136    $::_TARGET0 riscv dmi_write 0x3C 0xC
137    # PC17
138    $::_TARGET0 riscv dmi_write 0x39 0xF4040288
139    $::_TARGET0 riscv dmi_write 0x3C 0xC
140    # PC15
141    $::_TARGET0 riscv dmi_write 0x39 0xF4040278
142    $::_TARGET0 riscv dmi_write 0x3C 0xC
143    # PC12
144    $::_TARGET0 riscv dmi_write 0x39 0xF4040260
145    $::_TARGET0 riscv dmi_write 0x3C 0xC
146    # PC11
147    $::_TARGET0 riscv dmi_write 0x39 0xF4040258
148    $::_TARGET0 riscv dmi_write 0x3C 0xC
149    # PC10
150    $::_TARGET0 riscv dmi_write 0x39 0xF4040250
151    $::_TARGET0 riscv dmi_write 0x3C 0xC
152    # PC09
153    $::_TARGET0 riscv dmi_write 0x39 0xF4040248
154    $::_TARGET0 riscv dmi_write 0x3C 0xC
155    # PC08
156    $::_TARGET0 riscv dmi_write 0x39 0xF4040240
157    $::_TARGET0 riscv dmi_write 0x3C 0xC
158    # PC07
159    $::_TARGET0 riscv dmi_write 0x39 0xF4040238
160    $::_TARGET0 riscv dmi_write 0x3C 0xC
161    # PC06
162    $::_TARGET0 riscv dmi_write 0x39 0xF4040230
163    $::_TARGET0 riscv dmi_write 0x3C 0xC
164    # PC05
165    $::_TARGET0 riscv dmi_write 0x39 0xF4040228
166    $::_TARGET0 riscv dmi_write 0x3C 0xC
167    # PC04
168    $::_TARGET0 riscv dmi_write 0x39 0xF4040220
169    $::_TARGET0 riscv dmi_write 0x3C 0xC
170
171    # PC14
172    $::_TARGET0 riscv dmi_write 0x39 0xF4040270
173    $::_TARGET0 riscv dmi_write 0x3C 0xC
174    # PC13
175    $::_TARGET0 riscv dmi_write 0x39 0xF4040268
176    $::_TARGET0 riscv dmi_write 0x3C 0xC
177    # PC16
178    # $::_TARGET0 riscv dmi_write 0x39 0xF4040280
179    $::_TARGET0 riscv dmi_write 0x3C 0x1000C
180    # PC26
181    $::_TARGET0 riscv dmi_write 0x39 0xF40402D0
182    $::_TARGET0 riscv dmi_write 0x3C 0xC
183    # PC25
184    $::_TARGET0 riscv dmi_write 0x39 0xF40402C8
185    $::_TARGET0 riscv dmi_write 0x3C 0xC
186    # PC19
187    $::_TARGET0 riscv dmi_write 0x39 0xF4040298
188    $::_TARGET0 riscv dmi_write 0x3C 0xC
189    # PC18
190    $::_TARGET0 riscv dmi_write 0x39 0xF4040290
191    $::_TARGET0 riscv dmi_write 0x3C 0xC
192    # PC23
193    $::_TARGET0 riscv dmi_write 0x39 0xF40402B8
194    $::_TARGET0 riscv dmi_write 0x3C 0xC
195    # PC24
196    $::_TARGET0 riscv dmi_write 0x39 0xF40402C0
197    $::_TARGET0 riscv dmi_write 0x3C 0xC
198    # PC30
199    $::_TARGET0 riscv dmi_write 0x39 0xF40402F0
200    $::_TARGET0 riscv dmi_write 0x3C 0xC
201    # PC31
202    $::_TARGET0 riscv dmi_write 0x39 0xF40402F8
203    $::_TARGET0 riscv dmi_write 0x3C 0xC
204    # PC02
205    $::_TARGET0 riscv dmi_write 0x39 0xF4040210
206    $::_TARGET0 riscv dmi_write 0x3C 0xC
207    # PC03
208    $::_TARGET0 riscv dmi_write 0x39 0xF4040218
209    $::_TARGET0 riscv dmi_write 0x3C 0xC
210
211    # dramc configuration
212    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
213    $::_TARGET0 riscv dmi_write 0x3C 0x1
214    sleep 10
215    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
216    $::_TARGET0 riscv dmi_write 0x3C 0x2
217    $::_TARGET0 riscv dmi_write 0x39 0xF3050008
218    $::_TARGET0 riscv dmi_write 0x3C 0x30524
219    $::_TARGET0 riscv dmi_write 0x39 0xF305000C
220    $::_TARGET0 riscv dmi_write 0x3C 0x6030524
221    $::_TARGET0 riscv dmi_write 0x39 0xF3050000
222    $::_TARGET0 riscv dmi_write 0x3C 0x10000000
223
224    # 16MB
225    $::_TARGET0 riscv dmi_write 0x39 0xF3050010
226    $::_TARGET0 riscv dmi_write 0x3C 0x40000019
227    $::_TARGET0 riscv dmi_write 0x39 0xF3050014
228    $::_TARGET0 riscv dmi_write 0x3C 0
229    # 16-bit
230    $::_TARGET0 riscv dmi_write 0x39 0xF3050040
231    $::_TARGET0 riscv dmi_write 0x3C 0xf31
232
233    # 133Mhz configuration
234    #$::_TARGET0 riscv dmi_write 0x39 0xF3050044
235    $::_TARGET0 riscv dmi_write 0x3C 0x884e22
236    # 166Mhz configuration
237    $::_TARGET0 riscv dmi_write 0x39 0xF3050044
238    $::_TARGET0 riscv dmi_write 0x3C 0x884e33
239
240    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
241    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
242    $::_TARGET0 riscv dmi_write 0x39 0xF3050048
243    $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
244    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
245    $::_TARGET0 riscv dmi_write 0x3C 0x2020300
246
247    # config delay cell
248    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
249    $::_TARGET0 riscv dmi_write 0x3C 0x3b
250    $::_TARGET0 riscv dmi_write 0x39 0xF3050150
251    $::_TARGET0 riscv dmi_write 0x3C 0x203b
252
253    $::_TARGET0 riscv dmi_write 0x39 0xF3050094
254    $::_TARGET0 riscv dmi_write 0x3C 0
255    $::_TARGET0 riscv dmi_write 0x39 0xF3050098
256    $::_TARGET0 riscv dmi_write 0x3C 0
257
258    # precharge all
259    $::_TARGET0 riscv dmi_write 0x39 0xF3050090
260    $::_TARGET0 riscv dmi_write 0x3C 0x40000000
261    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
262    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
263    sleep 500
264    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
265    $::_TARGET0 riscv dmi_write 0x3C 0x3
266    # auto refresh
267    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
268    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
269    sleep 500
270    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
271    $::_TARGET0 riscv dmi_write 0x3C 0x3
272    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
273    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
274    sleep 500
275    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
276    $::_TARGET0 riscv dmi_write 0x3C 0x3
277
278    # set mode
279    $::_TARGET0 riscv dmi_write 0x39 0xF30500A0
280    $::_TARGET0 riscv dmi_write 0x3C 0x33
281    $::_TARGET0 riscv dmi_write 0x39 0xF305009C
282    $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
283    sleep 500
284    $::_TARGET0 riscv dmi_write 0x39 0xF305003C
285    $::_TARGET0 riscv dmi_write 0x3C 0x3
286
287    $::_TARGET0 riscv dmi_write 0x39 0xF305004C
288    $::_TARGET0 riscv dmi_write 0x3C 0x2020301
289    echo "SDRAM has been initialized"
290}
291
292$_TARGET0 configure -event reset-init {
293    init_clock
294    init_sdram
295}
296
297$_TARGET0 configure -event gdb-attach {
298    reset halt
299}
300