1# Copyright (c) 2023 HPMicro
2# SPDX-License-Identifier: BSD-3-Clause
3flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
4
5proc init_clock {} {
6    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
7    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
8
9    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
10    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
11
12    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
13    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
14
15    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
16    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
17    echo "clocks has been enabled!"
18}
19
20proc init_ddr3 {} {
21# ddr dcdc setup
22    $::_TARGET0 riscv dmi_write 0x39 0xF4104080
23    $::_TARGET0 riscv dmi_write 0x3C 0x10578
24
25# ddr3 setup
26    $::_TARGET0 riscv dmi_write 0x39 0xF40C0180
27    $::_TARGET0 riscv dmi_write 0x3C 0x30000019
28    $::_TARGET0 riscv dmi_write 0x39 0xF400180C
29    $::_TARGET0 riscv dmi_write 0x3C 0x09100401
30
31    $::_TARGET0 riscv dmi_write 0x39 0xF4153000
32    $::_TARGET0 riscv dmi_write 0x3C 0xF0000010
33
34    $::_TARGET0 riscv dmi_write 0x39 0xF30101B0
35    $::_TARGET0 riscv dmi_write 0x3C 0
36
37    $::_TARGET0 riscv dmi_write 0x39 0xF4150040
38    $::_TARGET0 riscv dmi_write 0x3C 0xf004641f
39
40    $::_TARGET0 riscv dmi_write 0x39 0xF4153000
41    $::_TARGET0 riscv dmi_write 0x3C 0xf0000011
42
43    $::_TARGET0 riscv dmi_write 0x39 0xF3013000
44    $::_TARGET0 riscv dmi_write 0x3C 0xf4000000
45
46    $::_TARGET0 riscv dmi_write 0x39 0xF3010490
47    $::_TARGET0 riscv dmi_write 0x3C 1
48
49    $::_TARGET0 riscv dmi_write 0x39 0xF3010000
50    $::_TARGET0 riscv dmi_write 0x3C 0x1040001
51
52    $::_TARGET0 riscv dmi_write 0x39 0xF30100D0
53    $::_TARGET0 riscv dmi_write 0x3C 0x4002004e
54
55    $::_TARGET0 riscv dmi_write 0x39 0xF3010110
56    $::_TARGET0 riscv dmi_write 0x3C 0x05010407
57    $::_TARGET0 riscv dmi_write 0x39 0xF3010190
58    $::_TARGET0 riscv dmi_write 0x3C 0x07040102
59    $::_TARGET0 riscv dmi_write 0x39 0xF3010194
60    $::_TARGET0 riscv dmi_write 0x3C 0x20404
61    $::_TARGET0 riscv dmi_write 0x39 0xF30101A4
62    $::_TARGET0 riscv dmi_write 0x3C 0x20008
63    $::_TARGET0 riscv dmi_write 0x39 0xF3010240
64    $::_TARGET0 riscv dmi_write 0x3C 0x06000600
65
66    $::_TARGET0 riscv dmi_write 0x39 0xF3010200
67    $::_TARGET0 riscv dmi_write 0x3C 0x1F1F1F
68    $::_TARGET0 riscv dmi_write 0x39 0xF3010204
69    $::_TARGET0 riscv dmi_write 0x3C 0x121212
70    $::_TARGET0 riscv dmi_write 0x39 0xF3010208
71    $::_TARGET0 riscv dmi_write 0x3C 0
72    $::_TARGET0 riscv dmi_write 0x39 0xF301020C
73    $::_TARGET0 riscv dmi_write 0x3C 0
74    $::_TARGET0 riscv dmi_write 0x39 0xF3010210
75    $::_TARGET0 riscv dmi_write 0x3C 0x1F1F
76    $::_TARGET0 riscv dmi_write 0x39 0xF3010214
77    $::_TARGET0 riscv dmi_write 0x3C 0x06030303
78    $::_TARGET0 riscv dmi_write 0x39 0xF3010218
79    $::_TARGET0 riscv dmi_write 0x3C 0x0F060606
80
81    $::_TARGET0 riscv dmi_write 0x39 0xF3013000
82    $::_TARGET0 riscv dmi_write 0x3C 0xFC000000
83
84    $::_TARGET0 riscv dmi_write 0x39 0xF4150054
85    $::_TARGET0 riscv dmi_write 0x3C 0xc70
86    $::_TARGET0 riscv dmi_write 0x39 0xF4150058
87    $::_TARGET0 riscv dmi_write 0x3C 0x6
88    $::_TARGET0 riscv dmi_write 0x39 0xF415005c
89    $::_TARGET0 riscv dmi_write 0x3C 0x18
90    $::_TARGET0 riscv dmi_write 0x39 0xF4150048
91    $::_TARGET0 riscv dmi_write 0x3C 0x919c8866
92    $::_TARGET0 riscv dmi_write 0x39 0xF415004c
93    $::_TARGET0 riscv dmi_write 0x3C 0x1a838360
94    $::_TARGET0 riscv dmi_write 0x39 0xF415008c
95    $::_TARGET0 riscv dmi_write 0x3C 0xf06d50
96    $::_TARGET0 riscv dmi_write 0x39 0xF4150050
97    $::_TARGET0 riscv dmi_write 0x3C 0x3002d200
98
99
100    $::_TARGET0 riscv dmi_write 0x39 0xF30101b0
101    $::_TARGET0 riscv dmi_write 0x3C 1
102    sleep 100
103
104    $::_TARGET0 riscv dmi_write 0x39 0xF4150068
105    $::_TARGET0 riscv dmi_write 0x3C 0x930035C7
106    $::_TARGET0 riscv dmi_write 0x39 0xF4150004
107    $::_TARGET0 riscv dmi_write 0x3C 0xFF81
108    sleep 200
109
110    echo "ddr3 has been enabled!"
111}
112
113proc init_dram {} {
114# ddr dcdc setup
115    $::_TARGET0 riscv dmi_write 0x39 0xF4104080
116    $::_TARGET0 riscv dmi_write 0x3C 0x10708
117
118# pll1 setup
119    $::_TARGET0 riscv dmi_write 0x39 0xF40c0180
120    $::_TARGET0 riscv dmi_write 0x3C 0xb0000016
121    $::_TARGET0 riscv dmi_write 0x39 0xF40c0184
122    $::_TARGET0 riscv dmi_write 0x3C 0
123    $::_TARGET0 riscv dmi_write 0x39 0xF40c0188
124    $::_TARGET0 riscv dmi_write 0x3C 0xe4e1c00
125
126#ddr setup
127    $::_TARGET0 riscv dmi_write 0x39 0xF3010000
128    $::_TARGET0 riscv dmi_write 0x3C 0x3040000
129
130    $::_TARGET0 riscv dmi_write 0x39 0xF30101B0
131    $::_TARGET0 riscv dmi_write 0x3C 0
132
133    $::_TARGET0 riscv dmi_write 0x39 0xF4150044
134    $::_TARGET0 riscv dmi_write 0x3C 0x40a
135
136    $::_TARGET0 riscv dmi_write 0x39 0xF4150040
137    $::_TARGET0 riscv dmi_write 0x3C 0xf004641f
138
139    $::_TARGET0 riscv dmi_write 0x39 0xF4153000
140    $::_TARGET0 riscv dmi_write 0x3C 0xf0000011
141
142    $::_TARGET0 riscv dmi_write 0x39 0xF3013000
143    $::_TARGET0 riscv dmi_write 0x3C 0xf4000000
144
145    $::_TARGET0 riscv dmi_write 0x39 0xF3010490
146    $::_TARGET0 riscv dmi_write 0x3C 1
147
148    $::_TARGET0 riscv dmi_write 0x39 0xF3010000
149    $::_TARGET0 riscv dmi_write 0x3C 0x1040000
150    $::_TARGET0 riscv dmi_write 0x39 0xF3010190
151    $::_TARGET0 riscv dmi_write 0x3C 0x07010101
152    $::_TARGET0 riscv dmi_write 0x39 0xF3010194
153    $::_TARGET0 riscv dmi_write 0x3C 0x20404
154    $::_TARGET0 riscv dmi_write 0x39 0xF30101A4
155    $::_TARGET0 riscv dmi_write 0x3C 0x20008
156    $::_TARGET0 riscv dmi_write 0x39 0xF3010240
157    $::_TARGET0 riscv dmi_write 0x3C 0x6000600
158    $::_TARGET0 riscv dmi_write 0x39 0xF3010200
159    $::_TARGET0 riscv dmi_write 0x3C 0x1f1f1f
160    $::_TARGET0 riscv dmi_write 0x39 0xF3010204
161    $::_TARGET0 riscv dmi_write 0x3C 0x70707
162    $::_TARGET0 riscv dmi_write 0x39 0xF3010208
163    $::_TARGET0 riscv dmi_write 0x3C 0
164    $::_TARGET0 riscv dmi_write 0x39 0xF301020c
165    $::_TARGET0 riscv dmi_write 0x3C 0
166    $::_TARGET0 riscv dmi_write 0x39 0xF3010210
167    $::_TARGET0 riscv dmi_write 0x3C 0x1f1f
168    $::_TARGET0 riscv dmi_write 0x39 0xF3010214
169    $::_TARGET0 riscv dmi_write 0x3C 0x6060606
170    $::_TARGET0 riscv dmi_write 0x39 0xF3010218
171    $::_TARGET0 riscv dmi_write 0x3C 0xf0f0606
172
173    $::_TARGET0 riscv dmi_write 0x39 0xF3013000
174    $::_TARGET0 riscv dmi_write 0x3C 0xfc000000
175    $::_TARGET0 riscv dmi_write 0x39 0xF4150020
176    $::_TARGET0 riscv dmi_write 0x3C 0x3000100
177    $::_TARGET0 riscv dmi_write 0x39 0xF4150028
178    $::_TARGET0 riscv dmi_write 0x3C 0x18002356
179    $::_TARGET0 riscv dmi_write 0x39 0xF415002c
180    $::_TARGET0 riscv dmi_write 0x3C 0x0aac4156
181    $::_TARGET0 riscv dmi_write 0x39 0xF4150054
182    $::_TARGET0 riscv dmi_write 0x3C 0xe73
183    $::_TARGET0 riscv dmi_write 0x39 0xF4150058
184    $::_TARGET0 riscv dmi_write 0x3C 0x5
185    $::_TARGET0 riscv dmi_write 0x39 0xF415005c
186    $::_TARGET0 riscv dmi_write 0x3C 0
187    $::_TARGET0 riscv dmi_write 0x39 0xF4150048
188    $::_TARGET0 riscv dmi_write 0x3C 0xf2adfe53
189    $::_TARGET0 riscv dmi_write 0x39 0xF415004c
190    $::_TARGET0 riscv dmi_write 0x3C 0x22820362
191    $::_TARGET0 riscv dmi_write 0x39 0xF4150050
192    $::_TARGET0 riscv dmi_write 0x3C 0x30020100
193    $::_TARGET0 riscv dmi_write 0x39 0xF415008c
194    $::_TARGET0 riscv dmi_write 0x3C 0xf06d50
195
196    $::_TARGET0 riscv dmi_write 0x39 0xF30101b0
197    $::_TARGET0 riscv dmi_write 0x3C 1
198    sleep 100
199
200    $::_TARGET0 riscv dmi_write 0x39 0xF4150068
201    $::_TARGET0 riscv dmi_write 0x3C 0x91003587
202    $::_TARGET0 riscv dmi_write 0x39 0xF4150004
203    $::_TARGET0 riscv dmi_write 0x3C 0xF501
204    sleep 200
205    echo "ddr has been enabled!"
206}
207
208$_TARGET0 configure -event reset-end {
209    init_clock
210    # init_ddr3
211}
212
213$_TARGET0 configure -event reset-init {
214    init_clock
215    init_ddr3
216}
217
218$_TARGET0 configure -event gdb-attach {
219    reset halt
220}
221