1# Copyright (c) 2024 HPMicro
2# SPDX-License-Identifier: BSD-3-Clause
3
4# openocd flash driver argument:
5#   - option0:
6#       [31:28] Flash probe type
7#         0 - SFDP SDR / 1 - SFDP DDR
8#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
9#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
10#         6 - OctaBus DDR (SPI -> OPI DDR)
11#         8 - Xccela DDR (SPI -> OPI DDR)
12#         10 - EcoXiP DDR (SPI -> OPI DDR)
13#       [27:24] Command Pads after Power-on Reset
14#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
15#       [23:20] Command Pads after Configuring FLASH
16#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
17#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
18#         0 - Not needed
19#         1 - QE bit is at bit 6 in Status Register 1
20#         2 - QE bit is at bit1 in Status Register 2
21#         3 - QE bit is at bit7 in Status Register 2
22#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
23#       [15:8] Dummy cycles
24#         0 - Auto-probed / detected / default value
25#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
26#       [7:4] Misc.
27#         0 - Not used
28#         1 - SPI mode
29#         2 - Internal loopback
30#         3 - External DQS
31#       [3:0] Frequency option
32#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
33#   - option1:
34#       [31:20]  Reserved
35#       [19:16] IO voltage
36#         0 - 3V / 1 - 1.8V
37#       [15:12] Pin group
38#         0 - 1st group / 1 - 2nd group
39#       [11:8] Connection selection
40#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
41#       [7:0] Drive Strength
42#         0 - Default value
43
44# xpi0 configs
45#   - flash driver:     hpm_xpi
46#   - flash ctrl index: 0xF3000000
47#   - base address:     0x80000000
48#   - flash size:       0x2000000
49#   - flash option0:    0x7
50flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
51
52proc init_clock {} {
53    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
54    $::_TARGET0 riscv dmi_write 0x3C 0x1
55
56    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
57    $::_TARGET0 riscv dmi_write 0x3C 0x2
58
59    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
60    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
61
62    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
63    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
64
65    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
66    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
67
68    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
69    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
70    echo "clocks has been enabled!"
71}
72
73
74$_TARGET0 configure -event reset-init {
75    init_clock
76}
77
78$_TARGET0 configure -event gdb-attach {
79    reset halt
80}
81