1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef DRV_ENET_H 9 #define DRV_ENET_H 10 11 #include <netif/ethernetif.h> 12 #include "hpm_enet_drv.h" 13 #include "board.h" 14 15 typedef enum { 16 ENET_MAC_ADDR_PARA_ERROR = -1, 17 ENET_MAC_ADDR_FROM_OTP_MAC, 18 ENET_MAC_ADDR_FROM_OTP_UUID, 19 ENET_MAC_ADDR_FROM_MACRO 20 } enet_mac_addr_t; 21 22 typedef struct { 23 uint8_t mac_addr0; 24 uint8_t mac_addr1; 25 uint8_t mac_addr2; 26 uint8_t mac_addr3; 27 uint8_t mac_addr4; 28 uint8_t mac_addr5; 29 } mac_init_t; 30 31 typedef struct { 32 ENET_Type * instance; 33 enet_desc_t desc; 34 enet_mac_config_t mac_config; 35 uint8_t media_interface; 36 uint32_t irq_number; 37 bool int_refclk; 38 uint8_t tx_delay; 39 uint8_t rx_delay; 40 enet_int_config_t int_config; 41 #if __USE_ENET_PTP 42 bool ptp_enable; 43 uint32_t ptp_clk_src; 44 enet_ptp_config_t ptp_config; 45 enet_ptp_ts_update_t ptp_timestamp; 46 #endif 47 } enet_device; 48 49 typedef struct _hpm_enet 50 { 51 const char *name; 52 ENET_Type *base; 53 clock_name_t clock_name; 54 int32_t irq_num; 55 uint8_t inf; 56 struct eth_device *eth_dev; 57 enet_device *enet_dev; 58 enet_buff_config_t *rx_buff_cfg; 59 enet_buff_config_t *tx_buff_cfg; 60 volatile enet_rx_desc_t *dma_rx_desc_tab; 61 volatile enet_tx_desc_t *dma_tx_desc_tab; 62 uint8_t tx_delay; 63 uint8_t rx_delay; 64 bool int_refclk; 65 #if __USE_ENET_PTP 66 bool ptp_enable; 67 uint32_t ptp_clk_src; 68 enet_ptp_config_t *ptp_config; 69 enet_ptp_ts_update_t *ptp_timestamp; 70 #endif 71 } hpm_enet_t; 72 73 #define IS_UUID_INVALID(UUID) (UUID[0] == 0 && \ 74 UUID[1] == 0 && \ 75 UUID[2] == 0 && \ 76 UUID[3] == 0) 77 78 #define IS_MAC_INVALID(MAC) (MAC[0] == 0 && \ 79 MAC[1] == 0 && \ 80 MAC[2] == 0 && \ 81 MAC[3] == 0 && \ 82 MAC[4] == 0 && \ 83 MAC[5] == 0) 84 85 #if ENET_SOC_RGMII_EN 86 #ifndef ENET0_TX_BUFF_COUNT 87 #define ENET0_TX_BUFF_COUNT (50U) 88 #endif 89 90 #ifndef ENET0_RX_BUFF_COUNT 91 #define ENET0_RX_BUFF_COUNT (60U) 92 #endif 93 #else 94 #ifndef ENET0_TX_BUFF_COUNT 95 #define ENET0_TX_BUFF_COUNT (10U) 96 #endif 97 98 #ifndef ENET0_RX_BUFF_COUNT 99 #define ENET0_RX_BUFF_COUNT (20U) 100 #endif 101 #endif 102 103 #ifndef ENET0_RX_BUFF_SIZE 104 #define ENET0_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE 105 #endif 106 107 #ifndef ENET0_TX_BUFF_SIZE 108 #define ENET0_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE 109 #endif 110 111 #ifndef ENET1_TX_BUFF_COUNT 112 #define ENET1_TX_BUFF_COUNT (10U) 113 #endif 114 115 #ifndef ENET1_RX_BUFF_COUNT 116 #define ENET1_RX_BUFF_COUNT (30U) 117 #endif 118 119 #ifndef ENET1_RX_BUFF_SIZE 120 #define ENET1_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE 121 #endif 122 123 #ifndef ENET1_TX_BUFF_SIZE 124 #define ENET1_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE 125 #endif 126 127 #ifndef MAC0_ADDR0 128 #define MAC0_ADDR0 (0x98U) 129 #endif 130 131 #ifndef MAC0_ADDR1 132 #define MAC0_ADDR1 (0x2CU) 133 #endif 134 135 #ifndef MAC0_ADDR2 136 #define MAC0_ADDR2 (0xBCU) 137 #endif 138 139 #ifndef MAC0_ADDR3 140 #define MAC0_ADDR3 (0xB1U) 141 #endif 142 143 #ifndef MAC0_ADDR4 144 #define MAC0_ADDR4 (0x9FU) 145 #endif 146 147 #ifndef MAC0_ADDR5 148 #define MAC0_ADDR5 (0x17U) 149 #endif 150 151 152 #ifndef MAC1_ADDR0 153 #define MAC1_ADDR0 (0x98U) 154 #endif 155 156 #ifndef MAC1_ADDR1 157 #define MAC1_ADDR1 (0x2CU) 158 #endif 159 160 #ifndef MAC1_ADDR2 161 #define MAC1_ADDR2 (0xBCU) 162 #endif 163 164 #ifndef MAC1_ADDR3 165 #define MAC1_ADDR3 (0xB1U) 166 #endif 167 168 #ifndef MAC1_ADDR4 169 #define MAC1_ADDR4 (0x9FU) 170 #endif 171 172 #ifndef MAC1_ADDR5 173 #define MAC1_ADDR5 (0x27U) 174 #endif 175 int rt_hw_eth_init(void); 176 177 #endif /* DRV_ENET_H */ 178 179 /* DRV_GPIO_H */ 180