1 /*
2  * Copyright (c) 2021 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef RISCV_CORE_H
9 #define RISCV_CORE_H
10 
11 #include "hpm_common.h"
12 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16 
17 /**
18  * @brief  write fp csr
19  *
20  * @param v value to be set
21  */
22 #define write_fcsr(v) __asm volatile("fscsr %0" : : "r"(v))
23 
24 /**
25  * @brief clear bits in csr
26  *
27  * @param csr_num specific csr
28  * @param bit bits to be cleared
29  */
30 #define clear_csr(csr_num, bit) __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit))
31 
32 /**
33  * @brief read and clear bits in csr
34  *
35  * @param csr_num specific csr
36  * @param bit bits to be cleared
37  *
38  * @return csr value before cleared
39  */
40 #define read_clear_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })
41 
42 /**
43  * @brief read and set bits in csr
44  *
45  * @param csr_num specific csr
46  * @param bit bits to be set
47  *
48  * @return csr value before set
49  */
50 #define read_set_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; })
51 
52 /**
53  * @brief set bits in csr
54  *
55  * @param csr_num specific csr
56  * @param bit bits to be set
57  */
58 #define set_csr(csr_num, bit) __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit))
59 
60 /**
61  * @brief write value to csr
62  *
63  * @param csr_num specific csr
64  * @param v value to be written
65  */
66 #define write_csr(csr_num, v) __asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v))
67 
68 /**
69  * @brief read value of specific csr
70  *
71  * @param csr_num specific csr
72  *
73  * @return csr value
74  */
75 #define read_csr(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; })
76 
77 /**
78  * @brief read fp csr
79  *
80  * @return fp csr value
81  */
82 #define read_fcsr() ({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; })
83 
84 /**
85  * @brief execute fence.i
86  *
87  */
88 #define fencei() __asm volatile("fence.i")
89 
90 /**
91  * @brief execute fence rw
92  *
93  */
94 #define fencerw() __asm volatile("fence rw, rw")
95 
96 /**
97  * @brief execute fence iorw
98  *
99  */
100 #define fenceiorw() __asm volatile("fence iorw, iorw")
101 
102 /**
103  * @brief enable fpu
104  */
105 #define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)
106 
107 /**
108  * @brief disable fpu
109  */
110 #define disable_fpu() read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)
111 
112 /**
113  * @brief clear fcsr
114  */
115 #define clear_fcsr() write_fcsr(0)
116 
117 #ifdef __cplusplus
118 }
119 #endif
120 
121 
122 #endif /* RISCV_CORE_H */
123