1 /* 2 * Copyright (c) 2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LAN8720_REGS_H 10 #define HPM_LAN8720_REGS_H 11 12 typedef enum { 13 LAN8720_BMCR = 0, /* 0x0: Basic Mode Control Register */ 14 LAN8720_BMSR = 1, /* 0x1: Basic Mode Status Register */ 15 LAN8720_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ 16 LAN8720_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ 17 LAN8720_SMR = 18, /* 0x12: Special Modes Register */ 18 LAN8720_SECR = 26, /* 0x1A: Symbol Error Counter Register */ 19 LAN8720_ISFR = 29, /* 0x1D: Interrupt Source Flag Register */ 20 LAN8720_IMR = 30, /* 0x1E: Interrupt Mask Register */ 21 LAN8720_PSCSR = 31, /* 0x1F: PHY Special Control/Status Register */ 22 } LAN8720_REG_Type; 23 24 25 /* Bitfield definition for register: BMCR */ 26 /* 27 * RESET (RW/SC) 28 * 29 * 1 = software reset. Bit is self-clearing. When setting this bit do not set other 30 * bits in this register. The configuration is set from the register bit values, and not 31 * from the mode pins. 32 */ 33 #define LAN8720_BMCR_RESET_MASK (0x8000U) 34 #define LAN8720_BMCR_RESET_SHIFT (15U) 35 #define LAN8720_BMCR_RESET_SET(x) (((uint16_t)(x) << LAN8720_BMCR_RESET_SHIFT) & LAN8720_BMCR_RESET_MASK) 36 #define LAN8720_BMCR_RESET_GET(x) (((uint16_t)(x) & LAN8720_BMCR_RESET_MASK) >> LAN8720_BMCR_RESET_SHIFT) 37 38 /* 39 * LOOPBACK (RW) 40 * 41 * 0 = normal operation 42 * 1 = loopback mode 43 */ 44 #define LAN8720_BMCR_LOOPBACK_MASK (0x4000U) 45 #define LAN8720_BMCR_LOOPBACK_SHIFT (14U) 46 #define LAN8720_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << LAN8720_BMCR_LOOPBACK_SHIFT) & LAN8720_BMCR_LOOPBACK_MASK) 47 #define LAN8720_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & LAN8720_BMCR_LOOPBACK_MASK) >> LAN8720_BMCR_LOOPBACK_SHIFT) 48 49 /* 50 * SPEED (RW) 51 * 52 * 0 = 10Mbps 53 * 1 = 100Mbps 54 * Ignored if Auto-negotiation is enabled (0.12 = 1). 55 */ 56 #define LAN8720_BMCR_SPEED_MASK (0x2000U) 57 #define LAN8720_BMCR_SPEED_SHIFT (13U) 58 #define LAN8720_BMCR_SPEED_SET(x) (((uint16_t)(x) << LAN8720_BMCR_SPEED_SHIFT) & LAN8720_BMCR_SPEED_MASK) 59 #define LAN8720_BMCR_SPEED_GET(x) (((uint16_t)(x) & LAN8720_BMCR_SPEED_MASK) >> LAN8720_BMCR_SPEED_SHIFT) 60 61 /* 62 * ANE (RW) 63 * 64 * Auto-Negotiation Enable 65 * 0 = disable auto-negotiate process 66 * 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 67 */ 68 #define LAN8720_BMCR_ANE_MASK (0x1000U) 69 #define LAN8720_BMCR_ANE_SHIFT (12U) 70 #define LAN8720_BMCR_ANE_SET(x) (((uint16_t)(x) << LAN8720_BMCR_ANE_SHIFT) & LAN8720_BMCR_ANE_MASK) 71 #define LAN8720_BMCR_ANE_GET(x) (((uint16_t)(x) & LAN8720_BMCR_ANE_MASK) >> LAN8720_BMCR_ANE_SHIFT) 72 73 /* 74 * PWD (RW) 75 * 76 * 0 = normal operation 77 * 1 = General power down mode 78 * The Auto-Negotiation Enable must be cleared before setting the Power 79 * Down. 80 */ 81 #define LAN8720_BMCR_PWD_MASK (0x800U) 82 #define LAN8720_BMCR_PWD_SHIFT (11U) 83 #define LAN8720_BMCR_PWD_SET(x) (((uint16_t)(x) << LAN8720_BMCR_PWD_SHIFT) & LAN8720_BMCR_PWD_MASK) 84 #define LAN8720_BMCR_PWD_GET(x) (((uint16_t)(x) & LAN8720_BMCR_PWD_MASK) >> LAN8720_BMCR_PWD_SHIFT) 85 86 /* 87 * ISOLATE (RW) 88 * 89 * 0 = normal operation 90 * 1 = electrical isolation of PHY from the RMII 91 */ 92 #define LAN8720_BMCR_ISOLATE_MASK (0x400U) 93 #define LAN8720_BMCR_ISOLATE_SHIFT (10U) 94 #define LAN8720_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << LAN8720_BMCR_ISOLATE_SHIFT) & LAN8720_BMCR_ISOLATE_MASK) 95 #define LAN8720_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & LAN8720_BMCR_ISOLATE_MASK) >> LAN8720_BMCR_ISOLATE_SHIFT) 96 97 /* 98 * RESTART_AN (RW/SC) 99 * 100 * 0 = normal operation 101 * 1 = restart auto-negotiate process 102 * Bit is self-clearing. 103 */ 104 #define LAN8720_BMCR_RESTART_AN_MASK (0x200U) 105 #define LAN8720_BMCR_RESTART_AN_SHIFT (9U) 106 #define LAN8720_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << LAN8720_BMCR_RESTART_AN_SHIFT) & LAN8720_BMCR_RESTART_AN_MASK) 107 #define LAN8720_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & LAN8720_BMCR_RESTART_AN_MASK) >> LAN8720_BMCR_RESTART_AN_SHIFT) 108 109 /* 110 * DUPLEX (RW) 111 * 112 * 0 = half duplex 113 * 1 = full duplex 114 * Ignored if Auto-Negotiation is enabled (0.12 = 1). 115 */ 116 #define LAN8720_BMCR_DUPLEX_MASK (0x100U) 117 #define LAN8720_BMCR_DUPLEX_SHIFT (8U) 118 #define LAN8720_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << LAN8720_BMCR_DUPLEX_SHIFT) & LAN8720_BMCR_DUPLEX_MASK) 119 #define LAN8720_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & LAN8720_BMCR_DUPLEX_MASK) >> LAN8720_BMCR_DUPLEX_SHIFT) 120 121 /* Bitfield definition for register: BMSR */ 122 /* 123 * 100BASE_T4 (RO) 124 * 125 * 0 = no T4 ability 126 * 1 = T4 able 127 */ 128 #define LAN8720_BMSR_100BASE_T4_MASK (0x8000U) 129 #define LAN8720_BMSR_100BASE_T4_SHIFT (15U) 130 #define LAN8720_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T4_MASK) >> LAN8720_BMSR_100BASE_T4_SHIFT) 131 132 /* 133 * 100BASE_TX_FULL (RO) 134 * 135 * 0 = no TX full duplex ability 136 * 1 = TX with full duplex 137 */ 138 #define LAN8720_BMSR_100BASE_TX_FULL_MASK (0x4000U) 139 #define LAN8720_BMSR_100BASE_TX_FULL_SHIFT (14U) 140 #define LAN8720_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_TX_FULL_MASK) >> LAN8720_BMSR_100BASE_TX_FULL_SHIFT) 141 142 /* 143 * 100BASE_TX_HALF (RO) 144 * 145 * 0 = no TX half duplex ability 146 * 1 = TX with half duplex 147 */ 148 #define LAN8720_BMSR_100BASE_TX_HALF_MASK (0x2000U) 149 #define LAN8720_BMSR_100BASE_TX_HALF_SHIFT (13U) 150 #define LAN8720_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_TX_HALF_MASK) >> LAN8720_BMSR_100BASE_TX_HALF_SHIFT) 151 152 /* 153 * 10BASE_T_FULL (RO) 154 * 155 * 0 = no 10Mbps with full duplex ability 156 * 1 = 10Mbps with full duplex 157 */ 158 #define LAN8720_BMSR_10BASE_T_FULL_MASK (0x1000U) 159 #define LAN8720_BMSR_10BASE_T_FULL_SHIFT (12U) 160 #define LAN8720_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_10BASE_T_FULL_MASK) >> LAN8720_BMSR_10BASE_T_FULL_SHIFT) 161 162 /* 163 * 10BASE_T_HALF (RO) 164 * 165 * 0 = no 10Mbps with half duplex ability 166 * 1 = 10Mbps with half duplex 167 */ 168 #define LAN8720_BMSR_10BASE_T_HALF_MASK (0x800U) 169 #define LAN8720_BMSR_10BASE_T_HALF_SHIFT (11U) 170 #define LAN8720_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_10BASE_T_HALF_MASK) >> LAN8720_BMSR_10BASE_T_HALF_SHIFT) 171 172 /* 173 * 100BASE_T2_FULL (RO) 174 * 175 * 0 = PHY not able to perform full duplex 100BASE-T2 176 * 1 = PHY able to perform full duplex 100BASE-T2 177 */ 178 #define LAN8720_BMSR_100BASE_T2_FULL_MASK (0x400U) 179 #define LAN8720_BMSR_100BASE_T2_FULL_SHIFT (10U) 180 #define LAN8720_BMSR_100BASE_T2_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T2_FULL_MASK) >> LAN8720_BMSR_100BASE_T2_FULL_SHIFT) 181 182 /* 183 * 100BASE_T2_HALF (RO) 184 * 185 * 0 = PHY not able to perform half duplex 100BASE-T2 186 * 1 = PHY able to perform half duplex 100BASE-T2 187 */ 188 #define LAN8720_BMSR_100BASE_T2_HALF_MASK (0x200U) 189 #define LAN8720_BMSR_100BASE_T2_HALF_SHIFT (9U) 190 #define LAN8720_BMSR_100BASE_T2_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T2_HALF_MASK) >> LAN8720_BMSR_100BASE_T2_HALF_SHIFT) 191 192 /* 193 * EXTENDED_STATUS (RO) 194 * 195 * 0 = no extended status information in register 15 196 * 1 = extended status information in register 15 197 */ 198 #define LAN8720_BMSR_EXTENDED_STATUS_MASK (0x100U) 199 #define LAN8720_BMSR_EXTENDED_STATUS_SHIFT (8U) 200 #define LAN8720_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & LAN8720_BMSR_EXTENDED_STATUS_MASK) >> LAN8720_BMSR_EXTENDED_STATUS_SHIFT) 201 202 /* 203 * AUTO_NEGOTIATION_COMPLETE (RO) 204 * 205 * 0 = auto-negotiate process not completed 206 * 1 = auto-negotiate process completed 207 */ 208 #define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) 209 #define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) 210 #define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) 211 212 /* 213 * REMOTE_FAULT (RC) 214 * 215 * 1 = remote fault condition detected 216 * 0 = no remote fault 217 */ 218 #define LAN8720_BMSR_REMOTE_FAULT_MASK (0x10U) 219 #define LAN8720_BMSR_REMOTE_FAULT_SHIFT (4U) 220 #define LAN8720_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & LAN8720_BMSR_REMOTE_FAULT_MASK) >> LAN8720_BMSR_REMOTE_FAULT_SHIFT) 221 222 /* 223 * AUTO_NEGOTIATION_ABILITY (RO) 224 * 225 * 0 = unable to perform auto-negotiation function 226 * 1 = able to perform auto-negotiation function 227 */ 228 #define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) 229 #define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) 230 #define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) 231 232 /* 233 * LINK_STATUS (RO) 234 * 235 * 0 = link is down 236 * 1 = link is up 237 */ 238 #define LAN8720_BMSR_LINK_STATUS_MASK (0x4U) 239 #define LAN8720_BMSR_LINK_STATUS_SHIFT (2U) 240 #define LAN8720_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & LAN8720_BMSR_LINK_STATUS_MASK) >> LAN8720_BMSR_LINK_STATUS_SHIFT) 241 242 /* 243 * JABBER_DETECT (RO) 244 * 245 * 0 = no jabber condition detected 246 * 1 = jabber condition detected 247 */ 248 #define LAN8720_BMSR_JABBER_DETECT_MASK (0x2U) 249 #define LAN8720_BMSR_JABBER_DETECT_SHIFT (1U) 250 #define LAN8720_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & LAN8720_BMSR_JABBER_DETECT_MASK) >> LAN8720_BMSR_JABBER_DETECT_SHIFT) 251 252 /* 253 * EXTENDED_CAPABILITY (RO) 254 * 255 * 0 = does not support extended capabilities registers 256 * 1 = supports extended capabilities registers 257 */ 258 #define LAN8720_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) 259 #define LAN8720_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) 260 #define LAN8720_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & LAN8720_BMSR_EXTENDED_CAPABILITY_MASK) >> LAN8720_BMSR_EXTENDED_CAPABILITY_SHIFT) 261 262 /* Bitfield definition for register: PHYID1 */ 263 /* 264 * OUI_MSB (RO) 265 * 266 * Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier 267 * (OUI), respectively. 268 */ 269 #define LAN8720_PHYID1_OUI_MSB_MASK (0xFFFFU) 270 #define LAN8720_PHYID1_OUI_MSB_SHIFT (0U) 271 #define LAN8720_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & LAN8720_PHYID1_OUI_MSB_MASK) >> LAN8720_PHYID1_OUI_MSB_SHIFT) 272 273 /* Bitfield definition for register: PHYID2 */ 274 /* 275 * OUI_LSB (RO) 276 * 277 * Assigned to the 19th through 24th bits of the OUI. 278 */ 279 #define LAN8720_PHYID2_OUI_LSB_MASK (0xFC00U) 280 #define LAN8720_PHYID2_OUI_LSB_SHIFT (10U) 281 #define LAN8720_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_OUI_LSB_MASK) >> LAN8720_PHYID2_OUI_LSB_SHIFT) 282 283 /* 284 * MODEL_NUMBER (RO) 285 * 286 * Six-bit manufacturer’s model number. 287 */ 288 #define LAN8720_PHYID2_MODEL_NUMBER_MASK (0x3F0U) 289 #define LAN8720_PHYID2_MODEL_NUMBER_SHIFT (4U) 290 #define LAN8720_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_MODEL_NUMBER_MASK) >> LAN8720_PHYID2_MODEL_NUMBER_SHIFT) 291 292 /* 293 * REVISION_NUMBER (RO) 294 * 295 * Four-bit manufacturer’s revision number. 296 */ 297 #define LAN8720_PHYID2_REVISION_NUMBER_MASK (0xFU) 298 #define LAN8720_PHYID2_REVISION_NUMBER_SHIFT (0U) 299 #define LAN8720_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_REVISION_NUMBER_MASK) >> LAN8720_PHYID2_REVISION_NUMBER_SHIFT) 300 301 /* Bitfield definition for register: SMR */ 302 /* 303 * MODE (R/W) 304 * 305 * Transceiver mode of operation 306 */ 307 #define LAN8720_SMR_MODE_MASK (0xE0U) 308 #define LAN8720_SMR_MODE_SHIFT (5U) 309 #define LAN8720_SMR_MODE_SET(x) (((uint16_t)(x) << LAN8720_SMR_MODE_SHIFT) & LAN8720_SMR_MODE_MASK) 310 #define LAN8720_SMR_MODE_GET(x) (((uint16_t)(x) & LAN8720_SMR_MODE_MASK) >> LAN8720_SMR_MODE_SHIFT) 311 312 /* 313 * PHYAD (R/W) 314 * 315 * PHY Address. The PHY Address is used for the SMI address and for initial- 316 * ization of the Cipher (Scrambler) key. 317 */ 318 #define LAN8720_SMR_PHYAD_MASK (0x1FU) 319 #define LAN8720_SMR_PHYAD_SHIFT (0U) 320 #define LAN8720_SMR_PHYAD_SET(x) (((uint16_t)(x) << LAN8720_SMR_PHYAD_SHIFT) & LAN8720_SMR_PHYAD_MASK) 321 #define LAN8720_SMR_PHYAD_GET(x) (((uint16_t)(x) & LAN8720_SMR_PHYAD_MASK) >> LAN8720_SMR_PHYAD_SHIFT) 322 323 /* Bitfield definition for register: SECR */ 324 /* 325 * SYM_ERR_CNT (RO) 326 * 327 * The symbol error counter increments whenever an invalid code symbol is 328 * received (including IDLE symbols) in 100BASE-TX mode. The counter is 329 * incremented only once per packet, even when the received packet contains 330 * more than one symbol error. This counter increments up to 65,536 (2^16) and 331 * rolls over to 0 after reaching the maximum value. 332 * Note: This register is cleared on reset, but is not cleared by reading the 333 * register. This register does not increment in 10BASE-T mode. 334 */ 335 #define LAN8720_SECR_SYM_ERR_CNT_MASK (0xFFFFU) 336 #define LAN8720_SECR_SYM_ERR_CNT_SHIFT (0U) 337 #define LAN8720_SECR_SYM_ERR_CNT_GET(x) (((uint16_t)(x) & LAN8720_SECR_SYM_ERR_CNT_MASK) >> LAN8720_SECR_SYM_ERR_CNT_SHIFT) 338 339 /* Bitfield definition for register: ISFR */ 340 /* 341 * INT7 (RO) 342 * 343 * 0 = not source of interrupt 344 * 1 = ENERGYON generated 345 */ 346 #define LAN8720_ISFR_INT7_MASK (0x80U) 347 #define LAN8720_ISFR_INT7_SHIFT (7U) 348 #define LAN8720_ISFR_INT7_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT7_MASK) >> LAN8720_ISFR_INT7_SHIFT) 349 350 /* 351 * INT6 (RO) 352 * 353 * 0 = not source of interrupt 354 * 1 = Auto-Negotiation complete 355 */ 356 #define LAN8720_ISFR_INT6_MASK (0x40U) 357 #define LAN8720_ISFR_INT6_SHIFT (6U) 358 #define LAN8720_ISFR_INT6_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT6_MASK) >> LAN8720_ISFR_INT6_SHIFT) 359 360 /* 361 * INT5 (RO) 362 * 363 * 0 = not source of interrupt 364 * 1 = Remote Fault Detected 365 */ 366 #define LAN8720_ISFR_INT5_MASK (0x20U) 367 #define LAN8720_ISFR_INT5_SHIFT (5U) 368 #define LAN8720_ISFR_INT5_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT5_MASK) >> LAN8720_ISFR_INT5_SHIFT) 369 370 /* 371 * INT4 (RO) 372 * 373 * 0 = not source of interrupt 374 * 1 = Link Down (link status negated) 375 */ 376 #define LAN8720_ISFR_INT4_MASK (0x10U) 377 #define LAN8720_ISFR_INT4_SHIFT (4U) 378 #define LAN8720_ISFR_INT4_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT4_MASK) >> LAN8720_ISFR_INT4_SHIFT) 379 380 /* 381 * INT3 (RO) 382 * 383 * 0 = not source of interrupt 384 * 1 = Auto-Negotiation LP Acknowledge 385 */ 386 #define LAN8720_ISFR_INT3_MASK (0x8U) 387 #define LAN8720_ISFR_INT3_SHIFT (3U) 388 #define LAN8720_ISFR_INT3_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT3_MASK) >> LAN8720_ISFR_INT3_SHIFT) 389 390 /* 391 * INT2 (RO) 392 * 393 * 0 = not source of interrupt 394 * 1 = Parallel Detection Fault 395 */ 396 #define LAN8720_ISFR_INT2_MASK (0x4U) 397 #define LAN8720_ISFR_INT2_SHIFT (2U) 398 #define LAN8720_ISFR_INT2_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT2_MASK) >> LAN8720_ISFR_INT2_SHIFT) 399 400 /* 401 * INT1 (RO) 402 * 403 * 0 = not source of interrupt 404 * 1 = Auto-Negotiation Page Received 405 */ 406 #define LAN8720_ISFR_INT1_MASK (0x2U) 407 #define LAN8720_ISFR_INT1_SHIFT (1U) 408 #define LAN8720_ISFR_INT1_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT1_MASK) >> LAN8720_ISFR_INT1_SHIFT) 409 410 /* Bitfield definition for register: IMR */ 411 /* 412 * MASK (R/W) 413 * 414 * 0 = interrupt source is masked 415 * 1 = interrupt source is enabled 416 */ 417 #define LAN8720_IMR_MASK_MASK (0xFEU) 418 #define LAN8720_IMR_MASK_SHIFT (1U) 419 #define LAN8720_IMR_MASK_SET(x) (((uint16_t)(x) << LAN8720_IMR_MASK_SHIFT) & LAN8720_IMR_MASK_MASK) 420 #define LAN8720_IMR_MASK_GET(x) (((uint16_t)(x) & LAN8720_IMR_MASK_MASK) >> LAN8720_IMR_MASK_SHIFT) 421 422 /* Bitfield definition for register: PSCSR */ 423 /* 424 * AUTODONE (RO) 425 * 426 * 0 = Auto-negotiation is not done or disabled (or not active) 427 * 1 = Auto-negotiation is done 428 */ 429 #define LAN8720_PSCSR_AUTODONE_MASK (0x1000U) 430 #define LAN8720_PSCSR_AUTODONE_SHIFT (12U) 431 #define LAN8720_PSCSR_AUTODONE_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_AUTODONE_MASK) >> LAN8720_PSCSR_AUTODONE_SHIFT) 432 433 /* 434 * DUPLEX (RO) 435 * 436 * 0: Half duplex 437 * 1: Full duplex 438 */ 439 #define LAN8720_PSCSR_DUPLEX_MASK (0x10U) 440 #define LAN8720_PSCSR_DUPLEX_SHIFT (4U) 441 #define LAN8720_PSCSR_DUPLEX_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_DUPLEX_MASK) >> LAN8720_PSCSR_DUPLEX_SHIFT) 442 443 /* 444 * SPEED (RO) 445 * 446 * HCDSPEED value: 447 * 01 = 10BASE-T 448 * 10 = 100BASE-TX 449 */ 450 #define LAN8720_PSCSR_SPEED_MASK (0xCU) 451 #define LAN8720_PSCSR_SPEED_SHIFT (2U) 452 #define LAN8720_PSCSR_SPEED_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_SPEED_MASK) >> LAN8720_PSCSR_SPEED_SHIFT) 453 454 455 456 457 #endif /* HPM_LAN8720_REGS_H */