1 /* 2 * Copyright (c) 2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_PPI_H 9 #define _HPM_PPI_H 10 11 /*--------------------------------------------------------------------- 12 * Includes 13 *--------------------------------------------------------------------- 14 */ 15 #include "hpm_ppi_drv.h" 16 17 /** 18 * @brief ppi async sram config structure 19 * 20 */ 21 typedef struct { 22 uint32_t base_address; /**< external SRAM base address, should be 1MB aligned */ 23 uint32_t size_in_byte; /**< external SRAM size in byte */ 24 ppi_port_size_t port_size; /**< port size */ 25 bool ad_mux_mode; /**< addr and data mux mode */ 26 bool cs_valid_polarity; /**< cs valid polarity */ 27 bool dm_valid_polarity; /**< dm valid polarity */ 28 bool addr_valid_polarity; /**< addr valid polarity */ 29 uint8_t adv_ctrl_pin; /**< adv ctrl pin number, 0 - 7 */ 30 uint8_t rel_ctrl_pin; /**< rel ctrl pin number, 0 - 7 */ 31 uint8_t wel_ctrl_pin; /**< wel ctrl pin number, 0 - 7 */ 32 uint8_t as_in_ns; /**< address setup time */ 33 uint8_t ah_in_ns; /**< address hold time */ 34 uint8_t rel_in_ns; /**< RE low time */ 35 uint8_t reh_in_ns; /**< RE high time */ 36 uint8_t wel_in_ns; /**< WE low time */ 37 uint8_t weh_in_ns; /**< WE high time */ 38 } ppi_async_sram_config_t; 39 40 41 #if defined(__cplusplus) 42 extern "C" { 43 #endif /* __cplusplus */ 44 45 /** 46 * @brief config async sram 47 * 48 * @param[in] ppi PPI base address 49 * @param[in] cs_index cs index, value: 0 - 3 50 * @param[in] cmd_index cmd start index 51 * @param[in] config async sram config structure pointer, @ref ppi_async_sram_config_t 52 */ 53 void ppi_config_async_sram(PPI_Type *ppi, uint8_t cs_index, uint8_t cmd_start_index, ppi_async_sram_config_t *config); 54 55 #if defined(__cplusplus) 56 } 57 #endif /* __cplusplus */ 58 #endif /* _HPM_PPI_H */