1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_ENET_DRV_H 9 #define HPM_ENET_DRV_H 10 11 /*--------------------------------------------------------------------- 12 * Includes 13 *--------------------------------------------------------------------- 14 */ 15 #include "hpm_common.h" 16 #include "hpm_enet_regs.h" 17 #include "hpm_soc_feature.h" 18 #include "hpm_enet_soc_drv.h" 19 20 /** 21 * @brief Enet driver APIs 22 * @defgroup enet_interface Enet driver APIs 23 * @ingroup communication_interfaces 24 * @{ 25 */ 26 27 /*--------------------------------------------------------------------- 28 * Macro Constant Declarations 29 *--------------------------------------------------------------------- 30 */ 31 #define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ 32 #define ENET_EXTRA (2U) /**< Extra bytes in some cases */ 33 #define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ 34 #define ENET_CRC (4U) /**< Ethernet CRC */ 35 #define ENET_MIN_PAYLOAD (46U) /**< Minimum Ethernet payload size */ 36 #define ENET_MAX_PAYLOAD (1500U) /**< Maximum Ethernet payload size */ 37 #define ENET_MAX_FRAME_SIZE (1524U) /**< ENET_HEADER + ENET_EXTRA + VLAN_TAG + MAX_ENET_PAYLOAD + ENET_CRC */ 38 #define ENET_JUMBO_FRAME_PAYLOAD (9000U) /**< Jumbo frame payload size */ 39 #define ENET_MAC (6) /**< Ethernet MAC size */ 40 #define ENET_ERROR (0) /**< ENET error */ 41 #define ENET_SUCCESS (1) /**< ENET success */ 42 43 #define ENET_ADJ_FREQ_BASE_ADDEND (0x80000000UL) /**< PTP base adjustment addend */ 44 #define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ 45 46 #define ENET_PPS_CMD_MASK (0x07UL) /**< Enet PPS CMD Mask */ 47 #define ENET_PPS_CMD_OFS_FAC (3U) /**< Enet PPS CMD OFS Factor */ 48 49 #ifndef ENET_RETRY_CNT 50 #define ENET_RETRY_CNT (10000UL) /**< Enet retry count for PTP */ 51 #endif 52 53 /*--------------------------------------------------------------------- 54 * Typedef Enum Declarations 55 *--------------------------------------------------------------------- 56 */ 57 58 /** @brief interrupt enable type */ 59 typedef enum { 60 enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, 61 enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK, 62 enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK, 63 enet_transmit_int_en = ENET_DMA_INTR_EN_TIE_MASK 64 } enet_interrupt_enable_t; 65 66 /** @brief interrupt mask type */ 67 typedef enum { 68 enet_lpi_int_mask = ENET_INTR_MASK_LPIIM_MASK, 69 enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK 70 } enet_interrupt_mask_t; 71 72 73 /** @brief Programmable burst length selections */ 74 typedef enum { 75 enet_pbl_1 = 1, 76 enet_pbl_2 = 2, 77 enet_pbl_4 = 4, 78 enet_pbl_8 = 8, 79 enet_pbl_16 = 16, 80 enet_pbl_32 = 32 81 } enet_pbl_t; 82 83 /** @brief Checksum insertion control selections */ 84 typedef enum { 85 enet_cic_disable = 0, 86 enet_cic_ip = 1, 87 enet_cic_ip_no_pseudoheader = 2, 88 enet_cic_ip_pseudoheader = 3 89 } enet_cic_insertion_control_t; 90 91 /** @brief VLAN insertion control selections */ 92 typedef enum { 93 enet_vlic_disable = 0, 94 enet_vlic_remove_vlan_tag = 1, 95 enet_vlic_insert_vlan_tag = 2, 96 enet_vlic_replace_vlan_tag = 3 97 } enet_vlan_insertion_control_t; 98 99 /** @brief SA insertion or replacement control selections for any selective frames */ 100 typedef enum { 101 enet_saic_disable = 0, 102 enet_saic_insert_mac0 = 1, 103 enet_saic_replace_mac0 = 2, 104 enet_saic_insert_mac1 = 5, 105 enet_saic_replace_mac1 = 6 106 } enet_saic_insertion_replacement_control_t; 107 108 /** @brief SA insertion or replacement control selections for all transmit frames */ 109 typedef enum { 110 enet_sarc_disable = 0, 111 enet_sarc_insert_mac0 = 2, 112 enet_sarc_replace_mac0 = 3, 113 enet_sarc_insert_mac1 = 6, 114 enet_sarc_replace_mac1 = 7 115 } enet_sarc_insertion_replacement_control_t; 116 117 /** @brief PHY operation selections */ 118 typedef enum { 119 enet_phy_op_read = 0, 120 enet_phy_op_write 121 } enet_phy_op_t; 122 123 124 /** @brief PHY status */ 125 typedef enum { 126 enet_gmii_idle = 0, 127 enet_gmii_busy 128 } enet_gmii_status_t; 129 130 /** @brief CSR clock range and MDC clock selections */ 131 /** @note The suggested range of CSR clock is approximately 132 * between the frequency range 1.0MHz-2.5MHz. 133 * You can achieve higher frequency of the MDC clock than the frequency limit of 2.5MHz(specified in the IEEE Std 802.3) 134 * and program a clock divider of lower value. Program the value which is no less than enet_csr_60m_to_100m_mdc_csr_div_4 135 * only if the interfacing chips support faster MDC clocks. 136 */ 137 typedef enum { 138 enet_csr_60m_to_100m_mdc_csr_div_42 = 0, /**< CSR clock range: 60-100MHz <==> MDC clock: CSR clock / 42 */ 139 enet_csr_100m_to_150m_mdc_csr_div_62, /**< CSR clock range: 100-150MHz <==> MDC clock: CSR clock / 62 */ 140 enet_csr_20m_to_35m_mdc_csr_div_16, /**< CSR clock range: 20-35MHz <==> MDC clock: CSR clock / 16 */ 141 enet_csr_35m_to_60m_mdc_csr_div_26, /**< CSR clock range: 35-60MHz <==> MDC clock: CSR clock / 26 */ 142 enet_csr_150m_to_250m_mdc_csr_div_102, /**< CSR clock range: 150-250MHz <==> MDC clock: CSR clock / 102 */ 143 enet_csr_250m_to_300m_mdc_csr_div_124, /**< CSR clock range: 250-300MHz <==> MDC clock: CSR clock / 124 */ 144 145 enet_csr_60m_to_100m_mdc_csr_div_4 = 8, /**< CSR clock / 4 */ 146 enet_csr_60m_to_100m_mdc_csr_div_6, /**< CSR clock / 6 */ 147 enet_csr_60m_to_100m_mdc_csr_div_8, /**< CSR clock / 8 */ 148 enet_csr_60m_to_100m_mdc_csr_div_10, /**< CSR clock / 10 */ 149 enet_csr_60m_to_100m_mdc_csr_div_12, /**< CSR clock / 12 */ 150 enet_csr_60m_to_100m_mdc_csr_div_14, /**< CSR clock / 14 */ 151 enet_csr_60m_to_100m_mdc_csr_div_16, /**< CSR clock / 16 */ 152 enet_csr_60m_to_100m_mdc_csr_div_18 /**< CSR clock / 18 */ 153 } enet_csr_clk_range_t; 154 155 /** @brief enet interface selections */ 156 typedef enum { 157 enet_inf_mii = 0, 158 enet_inf_rmii = 4, 159 enet_inf_rgmii = 1 160 } enet_inf_type_t; 161 162 /** @brief enet line speed */ 163 typedef enum { 164 enet_line_speed_1000mbps = 0, 165 enet_line_speed_10mbps = 2, 166 enet_line_speed_100mbps = 3 167 } enet_line_speed_t; 168 169 /** @brief enet duplex mode */ 170 typedef enum { 171 enet_half_duplex = 0, 172 enet_full_duplex 173 } enet_duplex_mode_t; 174 175 /** @brief enet timestamp update methods */ 176 typedef enum { 177 enet_ptp_time_coarse_update = 0, 178 enet_ptp_time_fine_update 179 } enet_ptp_time_update_method_t; 180 181 /** @brief PTP versions */ 182 typedef enum { 183 enet_ptp_v1 = 0, 184 enet_ptp_v2 185 } enet_ptp_version_t; 186 187 /** @brief PTP frame types */ 188 typedef enum { 189 enet_ptp_frame_ipv4 = 0, 190 enet_ptp_frame_ipv6, 191 enet_ptp_frame_ethernet 192 } enet_ptp_frame_type_t; 193 194 /** @brief PTP message type for snapshots */ 195 typedef enum { 196 enet_ts_ss_ptp_msg_0 = 0, /* SYNC, Follow_Up, Delay_Req, Delay_Resp */ 197 enet_ts_ss_ptp_msg_1 = 1, /* SYNC */ 198 enet_ts_ss_ptp_msg_2 = 3, /* Delay_Req */ 199 enet_ts_ss_ptp_msg_3 = 4, /* SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up */ 200 enet_ts_ss_ptp_msg_4 = 5, /* SYNC, Pdelay_Req, Pdelay_Resp */ 201 enet_ts_ss_ptp_msg_5 = 7, /* Delay_Req, Pdelay_Req, Pdelay_Resp */ 202 enet_ts_ss_ptp_msg_6 = 8, /* SYNC, Delay_Req */ 203 enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ 204 } enet_ts_ss_ptp_msg_t; 205 206 /** @brief PTP timer rollover modes */ 207 typedef enum { 208 enet_ts_bin_rollover_control = 0, /* timestamp rolls over after 0x7fffffff */ 209 enet_ts_dig_rollover_control /* timestamp rolls over after 0x3b9ac9ff */ 210 } enet_ts_rollover_control_t; 211 212 /** @brief PPS indexes */ 213 typedef enum { 214 enet_pps_0 = -1, 215 enet_pps_1 = 0, 216 enet_pps_2 = 1, 217 enet_pps_3 = 2 218 } enet_pps_idx_t; 219 220 /** @brief PPS0 control for output frequency selections */ 221 typedef enum { 222 enet_pps_ctrl_pps = 0, 223 enet_pps_ctrl_bin_2hz_digital_1hz, 224 enet_pps_ctrl_bin_4hz_digital_2hz, 225 enet_pps_ctrl_bin_8hz_digital_4hz, 226 enet_pps_ctrl_bin_16hz_digital_8hz, 227 enet_pps_ctrl_bin_32hz_digital_16hz, 228 enet_pps_ctrl_bin_64hz_digital_32hz, 229 enet_pps_ctrl_bin_128hz_digital_64hz, 230 enet_pps_ctrl_bin_256hz_digital_128hz, 231 enet_pps_ctrl_bin_512hz_digital_256hz, 232 enet_pps_ctrl_bin_1024hz_digital_512hz, 233 enet_pps_ctrl_bin_2048hz_digital_1024hz, 234 enet_pps_ctrl_bin_4096hz_digital_2048hz, 235 enet_pps_ctrl_bin_8192hz_digital_4096hz, 236 enet_pps_ctrl_bin_16384hz_digital_8192hz, 237 enet_pps_ctrl_bin_32768hz_digital_16384hz 238 } enet_pps_ctrl_t; 239 240 /** @brief PPS0 commands */ 241 typedef enum { 242 enet_pps_cmd_no_command = 0, 243 enet_pps_cmd_start_single_pulse, 244 enet_pps_cmd_start_pulse_train, 245 enet_pps_cmd_cancel_start, 246 enet_pps_cmd_stop_pulse_train_at_time, 247 enet_pps_cmd_stop_pulse_train_immediately, 248 enet_pps_cmd_cancel_stop_pulse_train 249 } enet_pps_cmd_t; 250 251 /*--------------------------------------------------------------------- 252 * Typedef Struct Declarations 253 *--------------------------------------------------------------------- 254 */ 255 /** @brief enet buffer config struct */ 256 typedef struct { 257 uint32_t buffer; 258 uint32_t count; 259 uint16_t size; 260 } enet_buff_config_t; 261 262 /** @brief enet mac config struct */ 263 typedef struct { 264 uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; 265 uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; 266 uint8_t valid_max_count; 267 uint8_t dma_pbl; 268 uint8_t sarc; 269 } enet_mac_config_t; 270 271 /** @brief transmission descriptor struct */ 272 typedef struct { 273 union { 274 uint32_t tdes0; 275 struct { 276 uint32_t db: 1; /**< * Deferred Bit*/ 277 uint32_t uf: 1; /**< * Underflow Error */ 278 uint32_t ed: 1; /**< * Excessive Deferral */ 279 uint32_t cc: 4; /**< * Collision Count */ 280 uint32_t vf: 1; /**< * VLAN Frame */ 281 uint32_t ec: 1; /**< * Excessive Collision */ 282 uint32_t lc: 1; /**< * Late Collision */ 283 uint32_t nc: 1; /**< * No Carrier */ 284 uint32_t loc: 1; /**< * Loss of Carrier */ 285 uint32_t ipe: 1; /**< * IP Payload Error */ 286 uint32_t ff: 1; /**< * Frame Flushed */ 287 uint32_t jt: 1; /**< * Jabber Timeout */ 288 uint32_t es: 1; /**< * Error Summary */ 289 uint32_t ihe: 1; /**< * IP Header Error */ 290 uint32_t ttss: 1; /**< * Transmit Timestamp Status */ 291 uint32_t vlic: 2; /**< * VLAN Insertion Control */ 292 uint32_t tch: 1; /**< * Second Address Chained */ 293 uint32_t ter: 1; /**< * Transmit End of Ring */ 294 uint32_t cic: 2; /**< * Checksum Insertion Control */ 295 uint32_t crcr: 1; /**< * CRC Replacement Control */ 296 uint32_t ttse: 1; /**< * Transmit Timestamp Enable */ 297 uint32_t dp: 1; /**< * Disable Pad */ 298 uint32_t dc: 1; /**< * Disable CRC */ 299 uint32_t fs: 1; /**< * First Segment */ 300 uint32_t ls: 1; /**< * Last Segment */ 301 uint32_t ic: 1; /**< * Interrupt on Completion */ 302 uint32_t own: 1; /**< * Own Bit */ 303 } tdes0_bm; 304 }; 305 306 union { 307 uint32_t tdes1; 308 struct { 309 uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ 310 uint32_t reserved: 3; /**< Reserved */ 311 uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ 312 uint32_t saic : 3; /**< SA Insertion Control */ 313 } tdes1_bm; 314 }; 315 316 union { 317 uint32_t tdes2; 318 struct { 319 uint32_t buffer1; /**< Buffer 1 Address */ 320 } tdes2_bm; 321 }; 322 323 union { 324 uint32_t tdes3; 325 union { 326 uint32_t buffer2; /**< Buffer 2 Address */ 327 uint32_t next_desc; /**< Next Descriptor Address */ 328 } tdes3_bm; 329 }; 330 331 #if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN 332 struct { 333 uint32_t reserved; 334 } tdes4_bm; 335 336 struct { 337 uint32_t reserved; 338 } tdes5_bm; 339 340 struct { 341 uint32_t ttsl; /**< Transmit Frame Timestamp Low */ 342 } tdes6_bm; 343 344 struct { 345 uint32_t ttsh; /**< Transmit Frame Timestamp High */ 346 } tdes7_bm; 347 #endif 348 } enet_tx_desc_t; 349 350 /** @brief reception descriptor struct */ 351 typedef struct { 352 union { 353 uint32_t rdes0; 354 355 struct { 356 uint32_t ex_sta_rx_addr : 1; /**< Extended Status Available or Rx MAC Address*/ 357 uint32_t ce : 1; /**< CRC Error */ 358 uint32_t dbe : 1; /**< Dribble Bit Error */ 359 uint32_t re : 1; /**< Receive Error */ 360 uint32_t rwt : 1; /**< Receive Watchdog Timeout */ 361 uint32_t ft : 1; /**< Frame Type */ 362 uint32_t lc : 1; /**< Late Collision */ 363 uint32_t ts_ip_gf : 1; /**< Timestamp Available, IP Checksum Error or Giant Frame*/ 364 uint32_t ls : 1; /**< Last Descriptor */ 365 uint32_t fs : 1; /**< First Descriptor */ 366 uint32_t vlan : 1; /**< VLAN Tag */ 367 uint32_t oe : 1; /**< Overflow Error */ 368 uint32_t le : 1; /**< Length Error */ 369 uint32_t saf : 1; /**< Source Address Filter Fail */ 370 uint32_t dse : 1; /**< Descriptor Error */ 371 uint32_t es : 1; /**< Error Summary */ 372 uint32_t fl : 14; /**< Frame Length */ 373 uint32_t afm : 1; /**< Destination Address Filter Fail */ 374 uint32_t own : 1; /**< Own Bit */ 375 } rdes0_bm; 376 }; 377 378 union { 379 uint32_t rdes1; 380 struct { 381 uint32_t rbs1 : 13; /**< Receive Buffer 1 Size */ 382 uint32_t reserved0: 1; /**< Reserved */ 383 uint32_t rch : 1; /**< Second Address Chained */ 384 uint32_t rer : 1; /**< Receive End of Ring */ 385 uint32_t rbs2 : 13; /**< Receive Buffer 2 Size */ 386 uint32_t reserved1: 2; /**< Reserved */ 387 uint32_t dic : 1; /**< Disable Interrupt on Completion */ 388 } rdes1_bm; 389 }; 390 391 union { 392 uint32_t rdes2; 393 struct { 394 uint32_t buffer1; /**< Buffer 1 Address */ 395 } rdes2_bm; 396 }; 397 398 union { 399 uint32_t rdes3; 400 union { 401 uint32_t buffer2; /**< Buffer 2 Address */ 402 uint32_t next_desc; /**< Next Descriptor Address */ 403 } rdes3_bm; 404 }; 405 406 #if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN 407 union { 408 uint32_t rdes4; 409 struct { 410 uint32_t ip_payload_type : 3; /**< IP Payload Type */ 411 uint32_t ip_header_err : 1; /**< IP Header Error */ 412 uint32_t ip_payload_err : 1; /**< IP Payload Error */ 413 uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ 414 uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ 415 uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ 416 uint32_t msg_type : 4; /**< Message Type */ 417 uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ 418 uint32_t ptp_version : 1; /**< PTP Version */ 419 uint32_t ts_dp : 1; /**< Timestamp Dropped */ 420 uint32_t reserved0 : 1; /**< Reserved */ 421 uint32_t av_pkt_recv : 1; /**< AV Packet Received */ 422 uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ 423 uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ 424 uint32_t reserved1 : 3; /**< Reserved */ 425 uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ 426 uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ 427 uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ 428 uint32_t reserved2 : 4; /**< Reserved */ 429 } rdes4_bm; 430 }; 431 432 struct { 433 uint32_t reserved; 434 } rdes5_bm; 435 436 struct { 437 uint32_t rtsl; /**< Receive Frame Timestamp Low */ 438 } rdes6_bm; 439 440 struct { 441 uint32_t rtsh; /**< Receive Frame Timestamp High */ 442 } rdes7_bm; 443 #endif 444 } enet_rx_desc_t; 445 446 /** @brief enet frame struct */ 447 typedef struct{ 448 uint32_t length; 449 uint32_t buffer; 450 enet_rx_desc_t *rx_desc; 451 } enet_frame_t; 452 453 /** @brief enet reception frame info struct */ 454 typedef struct { 455 enet_rx_desc_t *fs_rx_desc; 456 enet_rx_desc_t *ls_rx_desc; 457 uint32_t seg_count; 458 } enet_rx_frame_info_t; 459 460 /** @brief enet control config struct for transmission */ 461 typedef struct { 462 bool enable_ioc; /* interrupt on completion */ 463 bool disable_crc; /* disable CRC */ 464 bool disable_pad; /* disable Pad */ 465 bool enable_ttse; /* enable transmit timestamp */ 466 bool enable_crcr; /* CRC replacement control */ 467 uint8_t cic; /* checksum insertion control */ 468 uint8_t vlic; /* VLAN insertion control */ 469 uint8_t saic; /* SA insertion control */ 470 } enet_tx_control_config_t; 471 472 /** @brief enet description struct */ 473 typedef struct { 474 enet_tx_desc_t *tx_desc_list_head; 475 enet_rx_desc_t *rx_desc_list_head; 476 enet_tx_desc_t *tx_desc_list_cur; 477 enet_rx_desc_t *rx_desc_list_cur; 478 enet_buff_config_t tx_buff_cfg; 479 enet_buff_config_t rx_buff_cfg; 480 enet_rx_frame_info_t rx_frame_info; 481 enet_tx_control_config_t tx_control_config; 482 } enet_desc_t; 483 484 /** @brief PTP system timestamp struct */ 485 typedef struct { 486 uint32_t sec; 487 uint32_t nsec; 488 } enet_ptp_ts_system_t; 489 490 /** @brief PTP update timestamp struct */ 491 typedef struct { 492 uint32_t sec; 493 uint32_t nsec; 494 uint8_t sign; 495 } enet_ptp_ts_update_t; 496 497 /** @brief PTP target timestamp struct */ 498 typedef struct { 499 uint32_t sec; 500 uint32_t nsec; 501 } enet_ptp_ts_target_t; 502 503 /** @brief PTP config strcut */ 504 typedef struct { 505 uint8_t ssinc; 506 uint8_t timestamp_rollover_mode; 507 uint8_t update_method; 508 uint32_t addend; 509 } enet_ptp_config_t; 510 511 /** @brief PTP PPS command output config strcut */ 512 typedef struct { 513 uint32_t pps_interval; 514 uint32_t pps_width; 515 uint32_t target_sec; 516 uint32_t target_nsec; 517 } enet_pps_cmd_config_t; 518 519 /** @brief Enet interrupt config struct */ 520 typedef struct { 521 uint32_t int_enable; /* DMA_INTR_EN */ 522 uint32_t int_mask; /* INTR MASK */ 523 uint32_t mmc_intr_rx; 524 uint32_t mmc_intr_mask_rx; 525 uint32_t mmc_intr_tx; 526 uint32_t mmc_intr_mask_tx; 527 } enet_int_config_t; 528 529 /* 530 * @brief Bit definition of TDES1 531 */ 532 #define ENET_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /**< Transmit Buffer2 Size */ 533 #define ENET_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /**< Transmit Buffer1 Size */ 534 535 #if defined __cplusplus 536 extern "C" { 537 #endif /* __cplusplus */ 538 /*--------------------------------------------------------------------- 539 * Exported Functions 540 *--------------------------------------------------------------------- 541 */ 542 /** 543 * @brief Get a default control config for tranmission 544 * 545 * @param[in] ptr An Ethernet peripheral base address 546 * @param[in] config A pointer to a control config structure for tranmission 547 */ 548 void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config); 549 550 /** 551 * @brief Get a default interrupt config 552 * 553 * @param[in] ptr An Ethernet peripheral base address 554 * @param[in] config A pointer to a interrupt config structure 555 */ 556 void enet_get_default_interrupt_config(ENET_Type *ptr, enet_int_config_t *config); 557 558 /** 559 * @brief Get interrupt status 560 * 561 * @param[in] ptr An Ethernet peripheral base address 562 * @return A result of interrupt status 563 */ 564 uint32_t enet_get_interrupt_status(ENET_Type *ptr); 565 566 /** 567 * @brief Mask the specified mmc interrupt evenets of received frames 568 * 569 * @param[in] ptr An Ethernet peripheral base address 570 * @param[in] mask A mask of the specified evenets 571 */ 572 void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask); 573 574 /** 575 * @brief Mask the specified mmc interrupt evenets of transmitted frames 576 * 577 * @param[in] ptr An Ethernet peripheral base address 578 * @param[in] mask A mask of the specified evenets 579 */ 580 void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask); 581 582 /** 583 * @brief Get a staus of mmc receive interrupt events 584 * 585 * @param[in] ptr An Ethernet peripheral base address 586 * @return A result of interrupt status 587 */ 588 uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr); 589 /** 590 * @brief et a staus of mmc transmission interrupt events 591 * 592 * @param[in] ptr An Ethernet peripheral base address 593 * @return A result of interrupt status 594 */ 595 uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr); 596 597 /** 598 * @brief Initialize controller 599 * 600 * @param[in] ptr An Ethernet peripheral base address 601 * @param[in] inf_type the specified interface 602 * @param[in] desc A pointer to descriptor config 603 * @param[in] cfg A pointer to mac config 604 * @param[in] int_config A pointer to the masks of the specified enabled interrupts and the specified masked interrupts 605 * @return A result of the specified controller initialization 606 */ 607 hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); 608 609 /** 610 * @brief Set port line speed 611 * 612 * @param[in] ptr An Ethernet peripheral base address 613 * @param[in] speed An enum variable of @ref enet_line_speed_t 614 */ 615 void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed); 616 617 /** 618 * @brief Set duplex mode 619 * 620 * @param[in] ptr An Ethernet peripheral base address 621 * @param[in] mode An enum variable of @ref enet_duplex_mode_t 622 */ 623 void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode); 624 625 /** 626 * @brief Read phy 627 * 628 * @param[in] ptr An Ethernet peripheral base address 629 * @param[in] phy_addr the specified address of phy 630 * @param[in] addr the specified address of register 631 * @retval A value corresponding to the specified register address 632 */ 633 uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); 634 635 /** 636 * @brief Write phy 637 * 638 * @param[in] ptr An Ethernet peripheral base address 639 * @param[in] phy_addr a specified address of phy 640 * @param[in] addr a specified address of the register 641 * @param[in] data a specified data to be written 642 */ 643 void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); 644 645 /** 646 * @brief Resume reception process 647 * 648 * @param[in] ptr An Ethernet peripheral base address 649 * 650 */ 651 void enet_rx_resume(ENET_Type *ptr); 652 653 /** 654 * @brief Check if there is a received frame 655 * 656 * @param[out] parent_rx_desc_list_cur a parent pointer to the current reception description list 657 * @param[in] rx_frame_info A pointer to the information of the reception frames 658 * @retval A result of reception frame. 659 * 1 means that a reception of frame is successful. 660 * 0 means that a reception of frame is unsuccessful. 661 */ 662 uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); 663 664 /** 665 * @brief get a received frame 666 * 667 * @param[out] parent_rx_desc_list_cur A parent pointer to the current reception description list 668 * @param[in] rx_frame_info A pointer to the information of the reception frames 669 * @retval A struct of the current reception frame 670 */ 671 enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); 672 673 /** 674 * @brief get a received frame from interrupt 675 * 676 * @param[out] parent_rx_desc_list_cur the parent pointer to the current reception description list 677 * @param[in] rx_frame_info A pointer to the information of the reception frames 678 * @param[in] rx_desc_count A total count of the reception descriptors 679 * @retval A struct of the current reception frame 680 */ 681 enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); 682 683 /** 684 * @brief prepare for the transmission descriptors (It will be deprecated.) 685 * 686 * @param[in] ptr An Ethernet peripheral base address 687 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 688 * @param[in] frame_length the length of the transmission 689 * @param[in] tx_buff_size the size of the transmission buffer 690 * @retval a result of the transmission preparation. 691 * 1 means that the preparation is successful. 692 * 0 means that the preparation is unsuccessful. 693 */ 694 uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); 695 696 /** 697 * @brief prepare for the transmission descriptors 698 * 699 * @param[in] ptr An Ethernet peripheral base address 700 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 701 * @param[in] config a pointer to the control configuration for the transmission frames 702 * @param[in] frame_length the length of the transmission 703 * @param[in] tx_buff_size the size of the transmission buffer 704 * @retval a result of the transmission preparation. 705 * 1 means that the preparation is successful. 706 * 0 means that the preparation is unsuccessful. 707 */ 708 uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size); 709 710 /** 711 * @brief prepare for the transmission descriptors with a timestamp record 712 * 713 * @param[in] ptr An Ethernet peripheral base address 714 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 715 * @param[in] config a pointer to the control configuration for the transmission frames 716 * @param[in] frame_length the length of the transmission 717 * @param[in] tx_buff_size the size of the transmission buffer 718 * @param[out] timestamp a pointer to the timestamp record of a transmitted frame 719 * @retval a result of the transmission preparation. 720 * 1 means that the preparation is successful. 721 * 0 means that the preparation is unsuccessful. 722 */ 723 uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr, 724 enet_tx_desc_t **parent_tx_desc_list_cur, 725 enet_tx_control_config_t *config, 726 uint16_t frame_length, uint16_t tx_buff_size, 727 enet_ptp_ts_system_t *timestamp); 728 729 /** 730 * @brief Initialize DMA transmission descriptors in chain mode 731 * 732 * @param[in] ptr An Ethernet peripheral base address 733 * @param[in] desc A pointer to transmission descriptors 734 */ 735 void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); 736 737 /** 738 * @brief Initialize DMA reception descriptors in chain mode 739 * 740 * @param[in] ptr An Ethernet peripheral base address 741 * @param[in] desc A pointer to reception descriptors 742 */ 743 void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); 744 745 /** 746 * @brief Flush DMA 747 * 748 * @param[in] ptr An Ethernet peripheral base address 749 */ 750 void enet_dma_flush(ENET_Type *ptr); 751 752 /** 753 * @brief Initialize a PTP timer 754 * 755 * @param[in] ptr An Ethernet peripheral base address 756 * @param[in] config A pointer to an enet_ptp_config struct instance 757 */ 758 void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config); 759 760 /** 761 * @brief Set a timestamp to the PTP timer 762 * 763 * @param[in] ptr An Ethernet peripheral base address 764 * @param[in] timestamp A pointer to a update timestamp structure instance 765 */ 766 void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp); 767 768 /** 769 * @brief Get a timestamp from the PTP timer 770 * 771 * @param[in] ptr An Ethernet peripheral base address 772 * @param[out] timestamp A pointer to a system timestamp structure instance 773 */ 774 void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp); 775 776 /** 777 * @brief Update a timestamp to the PTP timer 778 * 779 * @param[in] ptr An Ethernet peripheral base address 780 * @param[in] timeoffset A pointer to a update timestamp structure instance 781 */ 782 void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset); 783 784 /** 785 * @brief Adjust the count frequency of the PTP timer 786 * 787 * @param[in] ptr An Ethernet peripheral base address 788 * @param[in] adj An adjustment value for the count frequency of the PTP timer 789 */ 790 void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj); 791 792 /** 793 * @brief Set the PTP version 794 * 795 * @param[in] ptr An Ethernet peripheral base address 796 * @param[in] ptp_ver An enum value indicating the PTP protocol 797 */ 798 void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver); 799 800 /** 801 * @brief Enable the specified ptp frame type for MAC process 802 * 803 * @param[in] ptr An Ethernet peripheral base address 804 * @param[in] ptp_frame_type An enum value indicating the transport protocol of PTP frames 805 * @param[in] enable A value to enable or disable the transport protocol of PTP frames which is specified by ptp_frame_type parameter 806 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 807 */ 808 hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable); 809 810 /** 811 * @brief Set the ptp message type for snapshots 812 * 813 * @param[in] ptr An Ethernet peripheral base address 814 * @param[in] ts_ss_ptp_msg An enum value indicating the specified ptp message type for snapshots 815 */ 816 void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg); 817 818 /** 819 * @brief Set the pps0 control output 820 * 821 * @param[in] ptr An Ethernet peripheral base address 822 * @param[in] freq An enum value indicating the specified pps frequency 823 */ 824 void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq); 825 826 /** 827 * @brief Set a pps command for ppsx 828 * 829 * @param[in] ptr An Ethernet peripheral base address 830 * @param[in] cmd An enum value indicating the specified pps command 831 * @param[in] idx An enum value indicating the index of pps instance 832 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 833 */ 834 hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx); 835 836 /** 837 * @brief Set a pps config for ppsx 838 * 839 * @param[in] ptr An Ethernet peripheral base address 840 * @param[in] cmd_cfg An enum value indicating the specified pps config 841 * @param[in] idx An enum value indicating the index of pps instance 842 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 843 */ 844 hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx); 845 846 #if defined __cplusplus 847 } 848 #endif /* __cplusplus */ 849 850 /** @} */ 851 #endif /* HPM_ENET_DRV_H */ 852