1 /*
2 * Copyright (c) 2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_RDC_DRV_H
9 #define HPM_RDC_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_rdc_regs.h"
13 #include "hpm_soc_feature.h"
14
15 /**
16 * @brief RDC driver APIs
17 * @defgroup rdc_interface RDC driver APIs
18 * @ingroup rdc_interfaces
19 * @{
20 */
21
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 /**
27 * @name Initialization and Deinitialization
28 * @{
29 */
30
31
32 /**
33 * @brief Rdc output precision, use n points to form an excitation signal period.
34 *
35 */
36 typedef enum rdc_output_precision {
37 rdc_output_precision_4_point = 0,
38 rdc_output_precision_8_point = 1,
39 rdc_output_precision_16_point = 2,
40 rdc_output_precision_32_point = 3,
41 rdc_output_precision_64_point = 4,
42 rdc_output_precision_128_point = 5,
43 rdc_output_precision_256_point = 6,
44 rdc_output_precision_512_point = 7,
45 rdc_output_precision_1024_point = 8,
46 } rdc_output_precision_t;
47
48 /**
49 * @brief Pwm output period in samples
50 *
51 */
52 typedef enum rdc_output_pwm_period {
53 rdc_output_pwm_period_1_sample = 0,
54 rdc_output_pwm_period_2_sample,
55 rdc_output_pwm_period_3_sample,
56 rdc_output_pwm_period_4_sample,
57 rdc_output_pwm_period_5_sample,
58 rdc_output_pwm_period_6_sample,
59 rdc_output_pwm_period_7_sample,
60 rdc_output_pwm_period_8_sample,
61 rdc_output_pwm_period_9_sample,
62 rdc_output_pwm_period_10_sample,
63 rdc_output_pwm_period_11_sample,
64 rdc_output_pwm_period_12_sample,
65 rdc_output_pwm_period_13_sample,
66 rdc_output_pwm_period_14_sample,
67 rdc_output_pwm_period_15_sample,
68 rdc_output_pwm_period_16_sample,
69 } rdc_output_pwm_period_t;
70
71
72
73 /**
74 * @brief Rdc output mode
75 *
76 */
77 typedef enum rdc_output_mode {
78 rdc_output_dac,
79 rdc_output_pwm
80 } rdc_output_mode_t;
81
82 /**
83 * @brief Synchronize output trig adc position
84 *
85 */
86 typedef enum rdc_sync_out_src {
87 rdc_sync_out_exc_0_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(0),
88 rdc_sync_out_exc_90_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(1),
89 rdc_sync_out_exc_180_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(2),
90 rdc_sync_out_exc_270_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(3),
91 rdc_sync_out_max = RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK,
92 rdc_sync_out_min = RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK,
93 } rdc_sync_out_src_t;
94
95 /**
96 * @brief Select reference point of rectify signal
97 *
98 */
99 typedef enum rdc_rectify_signal {
100 rdc_rectify_signal_exc_0_ph = 0,
101 rdc_rectify_signal_exc_90_ph = 1,
102 rdc_rectify_signal_exc_180_ph = 2,
103 rdc_rectify_signal_exc_270_ph = 3,
104 rdc_rectify_signal_external = 4,
105 rdc_rectify_signal_external_invert = 5,
106 } rdc_rectify_signal_t;
107
108 /**
109 * @brief Time stamp selection for accumulation
110 *
111 */
112 typedef enum rdc_acc_stamp_time {
113 rdc_acc_stamp_end_of_acc = 0, /**< End of accumulation */
114 rdc_acc_stamp_start_of_acc = 1, /**< Start of accumulation */
115 rdc_acc_stamp_center_of_acc = 2, /**< Center of accumulation */
116 } rdc_acc_stamp_time_t;
117
118 /**
119 * @brief Rdc trigger out channel 0 or channel 1
120 *
121 */
122 typedef enum rdc_output_trig_chn {
123 trigger_out_0 = 0,
124 trigger_out_1 = 1
125 } rdc_output_trig_chn_t;
126
127
128 /**
129 * @brief Rdc input channel
130 *
131 */
132 typedef enum rdc_input_acc_chn {
133 rdc_acc_chn_i = 0,
134 rdc_acc_chn_q = 1
135 } rdc_input_acc_chn_t;
136
137 typedef enum rdc_input_max_min_value_source {
138 rdc_value_at_adc = 0,
139 rdc_value_at_iir = 1
140 } rdc_input_max_min_value_source_t;
141
142 /**
143 * @brief Rdc status flags
144 *
145 */
146 typedef enum rdc_interrupt_stat {
147 acc_vld_i_stat = RDC_INT_EN_ACC_VLD_I_EN_MASK,
148 acc_vld_q_stat = RDC_INT_EN_ACC_VLD_Q_EN_MASK,
149 rising_delay_i_stat = RDC_INT_EN_RISING_DELAY_I_EN_MASK,
150 falling_delay_i_stat = RDC_INT_EN_FALLING_DELAY_I_EN_MASK,
151 rising_delay_q_stat = RDC_INT_EN_RISING_DELAY_Q_EN_MASK,
152 falling_delay_q_stat = RDC_INT_EN_FALLING_DELAY_Q_EN_MASK,
153 sample_rising_i_stat = RDC_INT_EN_SAMPLE_RISING_I_EN_MASK,
154 sample_falling_i_stat = RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK,
155 sample_rising_q_stat = RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK,
156 sample_falling_q_stat = RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK,
157 acc_vld_i_ovh_stat = RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK,
158 acc_vld_q_ovh_stat = RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK,
159 acc_vld_i_ovl_stat = RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK,
160 acc_vld_q_ovl_stat = RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK,
161 acc_amp_ovh_stat = RDC_INT_EN_ACC_AMP_OVH_EN_MASK,
162 acc_amp_ovl_stat = RDC_INT_EN_ACC_AMP_OVL_EN_MASK,
163 } rdc_interrupt_stat_t;
164
165 /**
166 * @brief Rdc output configuration
167 *
168 */
169 typedef struct rdc_output_cfg {
170 rdc_output_mode_t mode; /**< pwm or dac */
171 uint32_t excitation_period_cycle; /**< The period of the excitation signal, in cycles */
172 rdc_output_precision_t excitation_precision; /**< Excitation signal precision */
173 rdc_output_pwm_period_t pwm_period; /**< Pwm period in samples */
174 bool output_swap; /**< Swap output of PWM and DAC */
175 int32_t amp_offset; /**< Offset for excitation, signed value*/
176 uint16_t amp_man; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */
177 uint16_t amp_exp; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */
178 bool pwm_dither_enable; /**< Enable dither of pwm */
179 bool pwm_exc_p_low_active; /**< Polarity of exc_p signal */
180 bool pwm_exc_n_low_active; /**< Polarity of exc_n signal */
181 bool trig_by_hw; /**< Hardware triggered excitation signal generation. Software triggering is required after shutdown */
182 uint32_t hw_trig_delay; /**< Trigger in delay timming in bus cycle from rising edge of trigger signal */
183 uint8_t dac_chn_i_sel; /**< Output channel selection for i_channel */
184 uint8_t dac_chn_q_sel; /**< Output channel selection for q_channel */
185 uint8_t pwm_deadzone_p; /**< Exc_p dead zone in clock cycle before swap */
186 uint8_t pwm_deadzone_n; /**< Exc_n dead zone in clock cycle before swap */
187 } rdc_output_cfg_t;
188
189
190 /**
191 * @brief Rdc input configuration
192 *
193 */
194 typedef struct rdc_input_cfg {
195 rdc_rectify_signal_t rectify_signal_sel; /**< Select reference point of rectify signal */
196 #if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
197 bool acc_fast; /**< every adc value can be as one accumulate value, */
198 rdc_input_max_min_value_source_t max_min_value_position; /**< max min value position */
199 #endif
200 uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change, Only acc_fast is zero, this bit is available */
201 rdc_acc_stamp_time_t acc_stamp; /**< Time stamp selection for accumulation */
202 uint32_t acc_input_chn_i; /**< Input channel selection for i_channel */
203 uint32_t acc_input_port_i; /**< Input port selection for i_channel */
204 uint32_t acc_input_chn_q; /**< Input channel selection for q_channel */
205 uint32_t acc_input_port_q; /**< Input port selection for q_channel */
206 } rdc_input_cfg_t;
207
208 /**
209 * @brief Accumulated configuration information
210 *
211 */
212 typedef struct rdc_acc_cfg {
213 struct {
214 uint16_t continue_edge_num: 3; /**< Filtering val: 1 - 8 */
215 uint16_t edge_distance: 6; /**< Minimum distance between two edges 0-63 */
216 };
217 #if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
218 bool enable_i_thrs_data_for_acc; /**< enable thrs data for accumulate */
219 bool enable_q_thrs_data_for_acc; /**< enable thrs data for accumulate */
220 #endif
221 uint8_t right_shift_without_sign; /**< Right shift without sign bit */
222 bool error_data_remove; /**< Toxic accumulation data be removed */
223 uint32_t exc_carrier_period; /**< The num in clock cycle for period of excitation 0-NULL others-cycles */
224 uint32_t sync_delay_i; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */
225 uint32_t sync_delay_q; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */
226 uint32_t amp_max; /**< The maximum of acc amplitude */
227 uint32_t amp_min; /**< The minimum of acc amplitude */
228 } rdc_acc_cfg_t;
229
230 #if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
231 /**
232 * @brief IIR Filter Configuration
233 *
234 */
235 typedef struct rdc_iir_cfg {
236 float b; /**< IIR parameter for b branch */
237 float a1; /**< IIR parameter a1 for a1 branch*/
238 float a2; /**< IIR parameter a1 for a2 branch*/
239 bool enable_lowpass; /**< IIR in lowpass mode */
240 } rdc_iir_cfg_t;
241 #endif
242
243 /** @} */
244
245 /**
246 * @name RDC Control
247 * @{
248 */
249
250 /**
251 * @brief Rdc output configuration, can be configured pwm output or dac output
252 *
253 * @param ptr @ref RDC_Type base
254 * @param cfg @ref rdc_output_cfg_t
255 */
256 void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg);
257
258 /**
259 * @brief Rdc input configuration, configuration of adc signal source and calculation parameters
260 *
261 * @param ptr @ref RDC_Type base
262 * @param cfg @ref rdc_input_cfg_t
263 */
264 void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg);
265
266 /**
267 * @brief Configuration accumulate time, support on the fly change
268 *
269 * @param ptr @ref RDC_Type base
270 * @param len accumulate time 0-255
271 */
rdc_set_acc_len(RDC_Type * ptr,uint8_t len)272 static inline void rdc_set_acc_len(RDC_Type *ptr, uint8_t len)
273 {
274 ptr->RDC_CTL = (ptr->RDC_CTL & (~RDC_RDC_CTL_ACC_LEN_MASK))
275 | RDC_RDC_CTL_ACC_LEN_SET(len);
276 }
277
278 /**
279 * @brief Enable accumulate calculation function
280 *
281 * @param ptr @ref RDC_Type base
282 */
rdc_acc_enable(RDC_Type * ptr)283 static inline void rdc_acc_enable(RDC_Type *ptr)
284 {
285 ptr->RDC_CTL |= RDC_RDC_CTL_ACC_EN_MASK;
286 }
287
288 /**
289 * @brief Disable accumulate calculation function
290 *
291 * @param ptr @ref RDC_Type base
292 */
rdc_acc_disable(RDC_Type * ptr)293 static inline void rdc_acc_disable(RDC_Type *ptr)
294 {
295 ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK;
296 }
297
298 #if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
299 /**
300 * @brief Enable IIR for adc input
301 *
302 * @param ptr @ref RDC_Type base
303 */
rdc_irr_enable(RDC_Type * ptr)304 static inline void rdc_irr_enable(RDC_Type *ptr)
305 {
306 ptr->RDC_CTL |= RDC_RDC_CTL_IIR_EN_MASK;
307 }
308
309 /**
310 * @brief Disable IIR for adc input
311 *
312 * @param ptr @ref RDC_Type base
313 */
rdc_irr_disable(RDC_Type * ptr)314 static inline void rdc_irr_disable(RDC_Type *ptr)
315 {
316 ptr->RDC_CTL &= ~RDC_RDC_CTL_IIR_EN_MASK;
317 }
318
319 /**
320 * @brief enable i thrs data for accumulate
321 *
322 * @param ptr @ref RDC_Type base
323 */
rdc_enable_i_channel_thrs_data_for_acc(RDC_Type * ptr)324 static inline void rdc_enable_i_channel_thrs_data_for_acc(RDC_Type *ptr)
325 {
326 ptr->THRS_I |= RDC_THRS_I_THRS4ACC_MASK;
327 }
328
329 /**
330 * @brief disable i thrs data for accumulate
331 *
332 * @param ptr @ref RDC_Type base
333 */
rdc_disable_i_channel_thrs_data_for_acc(RDC_Type * ptr)334 static inline void rdc_disable_i_channel_thrs_data_for_acc(RDC_Type *ptr)
335 {
336 ptr->THRS_I &= ~RDC_THRS_I_THRS4ACC_MASK;
337 }
338
339 /**
340 * @brief enable q thrs data for accumulate
341 *
342 * @param ptr @ref RDC_Type base
343 */
rdc_enable_q_channel_thrs_data_for_acc(RDC_Type * ptr)344 static inline void rdc_enable_q_channel_thrs_data_for_acc(RDC_Type *ptr)
345 {
346 ptr->THRS_Q |= RDC_THRS_Q_THRS4ACC_MASK;
347 }
348
349 /**
350 * @brief disable q thrs data for accumulate
351 *
352 * @param ptr @ref RDC_Type base
353 */
rdc_disable_q_channel_thrs_data_for_acc(RDC_Type * ptr)354 static inline void rdc_disable_q_channel_thrs_data_for_acc(RDC_Type *ptr)
355 {
356 ptr->THRS_Q &= ~RDC_THRS_Q_THRS4ACC_MASK;
357 }
358
359 #endif
360
361 /**
362 * @brief Get the accumulate value
363 *
364 * @param ptr @ref RDC_Type base
365 * @param chn @ref rdc_input_acc_chn_t
366 * @return uint32_t accumulate value
367 */
368 uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn);
369
370 /**
371 * @brief Output trigger configuration
372 * Lead time for trigger out0 or out1 from center of low level , this is a signed value
373 * @param ptr @ref RDC_Type base
374 * @param chn @ref rdc_output_trig_chn_t
375 * @param offset lead_time
376 */
377 void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset);
378
379 /**
380 * @brief Enable output trigger configuration
381 *
382 * @param ptr @ref RDC_Type base
383 * @param chn @ref rdc_output_trig_chn_t
384 */
385 void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn);
386
387 /**
388 * @brief Disable rdc output trigger configuration
389 *
390 * @param ptr @ref RDC_Type base
391 * @param chn @ref rdc_output_trig_chn_t
392 */
393 void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn);
394
395 /**
396 * @brief Select output synchornize signal
397 *
398 * @param ptr @ref RDC_Type base
399 * @param sel @ref rdc_sync_out_src_t
400 */
rdc_sync_output_trig_adc_cfg(RDC_Type * ptr,rdc_sync_out_src_t sel)401 static inline void rdc_sync_output_trig_adc_cfg(RDC_Type *ptr, rdc_sync_out_src_t sel)
402 {
403 ptr->SYNC_OUT_CTRL = sel;
404 }
405
406 /**
407 * @brief Enable rdc excite signal
408 *
409 * @param ptr @ref RDC_Type base
410 */
rdc_exc_enable(RDC_Type * ptr)411 static inline void rdc_exc_enable(RDC_Type *ptr)
412 {
413 ptr->RDC_CTL |= RDC_RDC_CTL_EXC_EN_MASK;
414 }
415
416 /**
417 * @brief Disable rdc excite signal
418 *
419 * @param ptr @ref RDC_Type base
420 */
rdc_exc_disable(RDC_Type * ptr)421 static inline void rdc_exc_disable(RDC_Type *ptr)
422 {
423 ptr->RDC_CTL &= ~RDC_RDC_CTL_EXC_EN_MASK;
424 }
425
426 /**
427 * @brief Software triggered excitation signal output
428 *
429 * @param ptr @ref RDC_Type base
430 */
rdc_output_trig_sw(RDC_Type * ptr)431 static inline void rdc_output_trig_sw(RDC_Type *ptr)
432 {
433 ptr->RDC_CTL |= RDC_RDC_CTL_EXC_START_MASK;
434 }
435
436 /**
437 * @brief Get I-phase maximum
438 *
439 * @param ptr @ref RDC_Type base
440 * @retval - other max value
441 * - -1 illegal data
442 */
443 int32_t rdc_get_i_maxval(RDC_Type *ptr);
444
445 /**
446 * @brief Clear Maximum
447 *
448 * @param ptr @ref RDC_Type base
449 */
rdc_clear_i_maxval(RDC_Type * ptr)450 static inline void rdc_clear_i_maxval(RDC_Type *ptr)
451 {
452 ptr->MAX_I = 0;
453 }
454
455 /**
456 * @brief Get I-phase minimum
457 *
458 * @param ptr @ref RDC_Type base
459 * @retval - other max value
460 * - -1 illegal data
461 */
462 int32_t rdc_get_i_minval(RDC_Type *ptr);
463
464 /**
465 * @brief Clear I-phase minimum
466 *
467 * @param ptr @ref RDC_Type base
468 */
rdc_clear_i_minval(RDC_Type * ptr)469 static inline void rdc_clear_i_minval(RDC_Type *ptr)
470 {
471 ptr->MIN_I = 0;
472 }
473
474 /**
475 * @brief Set Acc sync delay
476 *
477 * @param ptr @ref RDC_Type base
478 * @param chn @ref rdc_input_acc_chn_t
479 * @param delay delay tick
480 */
481 void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay);
482
483 /**
484 * @brief Delay bettween the delyed trigger and
485 * the first pwm pulse in clock cycle
486 *
487 * @param ptr @ref RDC_Type base
488 * @retval delay tick
489 */
rdc_get_sync_output_delay(RDC_Type * ptr)490 static inline uint32_t rdc_get_sync_output_delay(RDC_Type *ptr)
491 {
492 return RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(ptr->SYNC_OUT_CTRL);
493 }
494
495 /**
496 * @brief Get Q-phase maximum
497 *
498 * @param ptr @ref RDC_Type base
499 * @retval - other max value
500 * - -1 illegal data
501 */
502 int32_t rdc_get_q_maxval(RDC_Type *ptr);
503
504 /**
505 * @brief Clear Q-phase maxval
506 *
507 * @param ptr @ref RDC_Type base
508 */
rdc_clear_q_maxval(RDC_Type * ptr)509 static inline void rdc_clear_q_maxval(RDC_Type *ptr)
510 {
511 ptr->MAX_Q = 0;
512 }
513
514 /**
515 * @brief Get Q-phase Minval
516 *
517 * @param ptr @ref RDC_Type base
518 * @retval - other max value
519 * - -1 illegal data
520 */
521 int32_t rdc_get_q_minval(RDC_Type *ptr);
522
523 /**
524 * @brief Clear Q-phase Minval
525 *
526 * @param ptr @ref RDC_Type base
527 */
rdc_clear_q_minval(RDC_Type * ptr)528 static inline void rdc_clear_q_minval(RDC_Type *ptr)
529 {
530 ptr->MIN_Q = 0;
531 }
532
533 /**
534 * @brief The offset setting for edge detection of the i_channel or q_channel
535 *
536 * @param ptr @ref RDC_Type base
537 * @param chn @ref rdc_input_acc_chn_t
538 * @param offset offset value
539 */
540 void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset);
541
542 /**
543 * @brief RDC set accumulate configuration
544 *
545 * @param ptr @ref RDC_Type base
546 * @param cfg @ref rdc_acc_cfg_t
547 */
548 void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg);
549
550 /**
551 * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data
552 *
553 * @param ptr @ref RDC_Type base
554 * @retval clock cycle
555 */
rdc_get_rise_delay_i(RDC_Type * ptr)556 static inline uint32_t rdc_get_rise_delay_i(RDC_Type *ptr)
557 {
558 return RDC_RISE_DELAY_I_RISE_DELAY_GET(ptr->RISE_DELAY_I);
559 }
560
561 /**
562 * @brief Get delay in clock cycle between excitation synchrnous signal and fall edge of i_channel data
563 *
564 * @param ptr @ref RDC_Type base
565 * @retval clock cycle
566 */
rdc_get_fall_delay_i(RDC_Type * ptr)567 static inline uint32_t rdc_get_fall_delay_i(RDC_Type *ptr)
568 {
569 return RDC_FALL_DELAY_I_FALL_DELAY_GET(ptr->FALL_DELAY_I);
570 }
571
572 /**
573 * @brief Get sample value on rising edge of rectify signal
574 *
575 * @param ptr @ref RDC_Type base
576 * @retval clock cycle
577 */
rdc_get_sample_rise_i(RDC_Type * ptr)578 static inline uint32_t rdc_get_sample_rise_i(RDC_Type *ptr)
579 {
580 return RDC_SAMPLE_RISE_I_VALUE_GET(ptr->SAMPLE_RISE_I);
581 }
582
583 /**
584 * @brief Get sample value on falling edge of rectify signal
585 *
586 * @param ptr @ref RDC_Type base
587 * @retval clock cycle
588 */
rdc_get_sample_fall_i(RDC_Type * ptr)589 static inline uint32_t rdc_get_sample_fall_i(RDC_Type *ptr)
590 {
591 return RDC_SAMPLE_FALL_I_VALUE_GET(ptr->SAMPLE_FALL_I);
592 }
593
594 /**
595 * @brief Get sample number during the positive of rectify signal
596 *
597 * @param ptr @ref RDC_Type base
598 * @retval counter
599 */
rdc_get_acc_cnt_positive_i(RDC_Type * ptr)600 static inline uint32_t rdc_get_acc_cnt_positive_i(RDC_Type *ptr)
601 {
602 return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I);
603 }
604
605 /**
606 * @brief Get sample number during the negtive of rectify signal
607 *
608 * @param ptr @ref RDC_Type base
609 * @retval counter
610 */
rdc_get_acc_cnt_negative_i(RDC_Type * ptr)611 static inline uint32_t rdc_get_acc_cnt_negative_i(RDC_Type *ptr)
612 {
613 return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I);
614 }
615
616 /**
617 * @brief Get Negative sample counter during positive rectify signal
618 *
619 * @param ptr @ref RDC_Type base
620 * @retval counter
621 */
rdc_get_sign_cnt_poitive_i(RDC_Type * ptr)622 static inline uint32_t rdc_get_sign_cnt_poitive_i(RDC_Type *ptr)
623 {
624 return RDC_SIGN_CNT_I_CNT_POS_GET(ptr->SIGN_CNT_I);
625 }
626
627 /**
628 * @brief Get Positive sample counter during negative rectify signal
629 *
630 * @param ptr @ref RDC_Type base
631 * @retval counter
632 */
rdc_get_sign_cnt_negative_i(RDC_Type * ptr)633 static inline uint32_t rdc_get_sign_cnt_negative_i(RDC_Type *ptr)
634 {
635 return RDC_SIGN_CNT_I_CNT_NEG_GET(ptr->SIGN_CNT_I);
636 }
637
638 /**
639 * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data
640 *
641 * @param ptr @ref RDC_Type base
642 * @retval cycles
643 */
rdc_get_rise_delay_q(RDC_Type * ptr)644 static inline uint32_t rdc_get_rise_delay_q(RDC_Type *ptr)
645 {
646 return RDC_RISE_DELAY_Q_RISE_DELAY_GET(ptr->RISE_DELAY_Q);
647 }
648
649 /**
650 * @brief Get delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data
651 *
652 * @param ptr @ref RDC_Type base
653 * @retval cycles
654 */
rdc_get_fall_delay_q(RDC_Type * ptr)655 static inline uint32_t rdc_get_fall_delay_q(RDC_Type *ptr)
656 {
657 return RDC_FALL_DELAY_Q_FALL_DELAY_GET(ptr->FALL_DELAY_Q);
658 }
659
660 /**
661 * @brief Get q channel sample value on rising edge of rectify signal
662 *
663 * @param ptr @ref RDC_Type base
664 * @retval cycles
665 */
rdc_get_sample_rise_q(RDC_Type * ptr)666 static inline uint32_t rdc_get_sample_rise_q(RDC_Type *ptr)
667 {
668 return RDC_SAMPLE_RISE_Q_VALUE_GET(ptr->SAMPLE_RISE_Q);
669 }
670
671 /**
672 * @brief Get q channel sample value on falling edge of rectify signal
673 *
674 * @param ptr @ref RDC_Type base
675 * @retval cycles
676 */
rdc_get_sample_fall_q(RDC_Type * ptr)677 static inline uint32_t rdc_get_sample_fall_q(RDC_Type *ptr)
678 {
679 return RDC_SAMPLE_FALL_Q_VALUE_GET(ptr->SAMPLE_FALL_Q);
680 }
681
682 /**
683 * @brief Get q channel sample number during the positive of rectify signal
684 *
685 * @param ptr @ref RDC_Type base
686 * @retval number
687 */
rdc_get_acc_cnt_positive_q(RDC_Type * ptr)688 static inline uint32_t rdc_get_acc_cnt_positive_q(RDC_Type *ptr)
689 {
690 return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q);
691 }
692
693 /**
694 * @brief Get q channel sample number during the negtive of rectify signal
695 *
696 * @param ptr @ref RDC_Type base
697 * @retval number
698 */
rdc_get_acc_cnt_negative_q(RDC_Type * ptr)699 static inline uint32_t rdc_get_acc_cnt_negative_q(RDC_Type *ptr)
700 {
701 return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q);
702 }
703
704 /**
705 * @brief Get q channel negative sample counter during positive rectify signal
706 *
707 * @param ptr @ref RDC_Type base
708 * @retval counter
709 */
rdc_get_sign_cnt_poitive_q(RDC_Type * ptr)710 static inline uint32_t rdc_get_sign_cnt_poitive_q(RDC_Type *ptr)
711 {
712 return RDC_SIGN_CNT_Q_CNT_POS_GET(ptr->SIGN_CNT_Q);
713 }
714
715 /**
716 * @brief Get q channel sample number during the negtive of rectify signal
717 *
718 * @param ptr @ref RDC_Type base
719 * @retval counter
720 */
rdc_get_sign_cnt_negative_q(RDC_Type * ptr)721 static inline uint32_t rdc_get_sign_cnt_negative_q(RDC_Type *ptr)
722 {
723 return RDC_SIGN_CNT_Q_CNT_NEG_GET(ptr->SIGN_CNT_Q);
724 }
725
726 /**
727 * @brief Enables configured interrupts
728 *
729 * @param ptr @ref RDC_Type base
730 * @param status @ref rdc_interrupt_stat_t
731 */
rdc_interrupt_config(RDC_Type * ptr,uint32_t status)732 static inline void rdc_interrupt_config(RDC_Type *ptr, uint32_t status)
733 {
734 ptr->INT_EN |= status;
735 }
736
737 /**
738 * @brief Clear interrupts configured
739 *
740 * @param ptr @ref RDC_Type base
741 * @param status @ref rdc_interrupt_stat_t
742 */
rdc_interrupt_reset_config(RDC_Type * ptr,uint32_t status)743 static inline void rdc_interrupt_reset_config(RDC_Type *ptr, uint32_t status)
744 {
745 ptr->INT_EN &= ~status;
746 }
747
748 /**
749 * @brief Enable rdc interrupt
750 *
751 * @param ptr @ref RDC_Type base
752 */
rdc_interrupt_enable(RDC_Type * ptr)753 static inline void rdc_interrupt_enable(RDC_Type *ptr)
754 {
755 ptr->INT_EN |= RDC_INT_EN_INT_EN_MASK;
756 }
757
758 /**
759 * @brief Disable rdc interrupt
760 *
761 * @param ptr @ref RDC_Type base
762 */
rdc_interrupt_disable(RDC_Type * ptr)763 static inline void rdc_interrupt_disable(RDC_Type *ptr)
764 {
765 ptr->INT_EN &= ~RDC_INT_EN_INT_EN_MASK;
766 }
767
768 /**
769 * @brief Clear interrupt flag bits
770 *
771 * @param ptr @ref RDC_Type base
772 * @param mask @ref rdc_interrupt_stat_t
773 */
rdc_interrupt_clear_flag_bits(RDC_Type * ptr,uint32_t mask)774 static inline void rdc_interrupt_clear_flag_bits(RDC_Type *ptr, uint32_t mask)
775 {
776 ptr->ADC_INT_STATE &= mask;
777 }
778
779 /**
780 * @brief Get the interrupt status object
781 *
782 * @param ptr @ref RDC_Type base
783 * @return @ref rdc_interrupt_stat_t
784 */
get_interrupt_status(RDC_Type * ptr)785 static inline uint32_t get_interrupt_status(RDC_Type *ptr)
786 {
787 return ptr->ADC_INT_STATE;
788 }
789
790 /** @} */
791
792 #ifdef __cplusplus
793 }
794 #endif
795
796 /** @} */
797 #endif /* HPM_ADC12_DRV_H */
798