1 /*
2 * Copyright (c) 2024 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #include "hpm_ppi_drv.h"
9
ppi_config_clk_pin(PPI_Type * ppi,ppi_clk_pin_config_t * config)10 void ppi_config_clk_pin(PPI_Type *ppi, ppi_clk_pin_config_t *config)
11 {
12 uint32_t tmp;
13
14 tmp = PPI_CLKPIN_CFG_CYCLE_SET(config->cycle_num)
15 | PPI_CLKPIN_CFG_HIGH_SET(config->high_num)
16 | PPI_CLKPIN_CFG_LOW_SET(config->low_num)
17 | PPI_CLKPIN_CFG_INVERT_SET(config->revert)
18 | PPI_CLKPIN_CFG_AON_SET(config->mode)
19 | PPI_CLKPIN_CFG_EN_MASK;
20
21 ppi->CLKPIN_CFG = tmp;
22 }
23
ppi_config_cs_pin(PPI_Type * ppi,uint8_t index,ppi_cs_pin_config_t * config)24 void ppi_config_cs_pin(PPI_Type *ppi, uint8_t index, ppi_cs_pin_config_t *config)
25 {
26 uint32_t tmp;
27 uint8_t shift;
28
29 assert(index < 4);
30 assert((config->addr_start_high_12bits >= 0xF80) && (config->addr_start_high_12bits <= 0xFFF));
31 assert((config->addr_end_high_12bits >= 0xF80) && (config->addr_end_high_12bits <= 0xFFF));
32
33 tmp = PPI_CS_CFG0_ADDR_START_SET(config->addr_start_high_12bits) | PPI_CS_CFG0_ADDR_END_SET(config->addr_end_high_12bits);
34 ppi->CS[index].CFG0 = tmp;
35
36 if (config->port_size == ppi_port_size_16bits) {
37 shift = 1;
38 } else if (config->port_size == ppi_port_size_32bits) {
39 shift = 2;
40 } else {
41 shift = 0;
42 }
43 tmp = PPI_CS_CFG1_ADDR_MASK_SET(config->addr_mask) | PPI_CS_CFG1_ADDR_SHIFT_SET(shift);
44 ppi->CS[index].CFG1 = tmp;
45
46 tmp = PPI_CS_CFG3_RCMD_END1_SET(config->rcmd_end1)
47 | PPI_CS_CFG3_RCMD_START1_SET(config->rcmd_start1)
48 | PPI_CS_CFG3_RCMD_END0_SET(config->rcmd_end0)
49 | PPI_CS_CFG3_RCMD_START0_SET(config->rcmd_start0);
50 ppi->CS[index].CFG3 = tmp;
51
52 tmp = PPI_CS_CFG4_WCMD_END1_SET(config->wcmd_end1)
53 | PPI_CS_CFG4_WCMD_START1_SET(config->wcmd_start1)
54 | PPI_CS_CFG4_WCMD_END0_SET(config->wcmd_end0)
55 | PPI_CS_CFG4_WCMD_START0_SET(config->wcmd_start0);
56 ppi->CS[index].CFG4 = tmp;
57
58 tmp = PPI_CS_CFG2_CS_SYNC_EN_SET(config->sync_clk_en)
59 | PPI_CS_CFG2_SYNC_CLK_SEL_SET(config->sync_clk_sel)
60 | PPI_CS_CFG2_INTER_CMD_DLY_SET(config->interval_cycle)
61 #if defined(HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS) && HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS
62 | PPI_CS_CFG2_DM_POLARITY_SET(config->dm_polarity)
63 #endif
64 | PPI_CS_CFG2_PORT_SIZE_SET(config->port_size)
65 | PPI_CS_CFG2_ENABLE_MASK;
66 ppi->CS[index].CFG2 = tmp;
67 }
68
ppi_config_cmd(PPI_Type * ppi,uint8_t index,ppi_cmd_config_t * config)69 void ppi_config_cmd(PPI_Type *ppi, uint8_t index, ppi_cmd_config_t *config)
70 {
71 uint32_t tmp;
72
73 assert(index < 64);
74
75 tmp = PPI_CMD_CMD_CFG_CS_VAL_SET(config->cs_pin_value)
76 | PPI_CMD_CMD_CFG_CLK_GATE_SET(config->clk_output)
77 | PPI_CMD_CMD_CFG_CYCLE_NUM_SET(config->cmd_cycle);
78 ppi->CMD[index].CMD_CFG = tmp;
79
80 tmp = PPI_CMD_AD_CFG_DIR3_SET(config->ad_pin_dir[3])
81 | PPI_CMD_AD_CFG_AD_SEL3_SET(config->ad_func_sel[3])
82 | PPI_CMD_AD_CFG_BYTE_SEL3_SET(config->byte_sel[3])
83 | PPI_CMD_AD_CFG_DIR2_SET(config->ad_pin_dir[2])
84 | PPI_CMD_AD_CFG_AD_SEL2_SET(config->ad_func_sel[2])
85 | PPI_CMD_AD_CFG_BYTE_SEL2_SET(config->byte_sel[2])
86 | PPI_CMD_AD_CFG_DIR1_SET(config->ad_pin_dir[1])
87 | PPI_CMD_AD_CFG_AD_SEL1_SET(config->ad_func_sel[1])
88 | PPI_CMD_AD_CFG_BYTE_SEL1_SET(config->byte_sel[1])
89 | PPI_CMD_AD_CFG_DIR0_SET(config->ad_pin_dir[0])
90 | PPI_CMD_AD_CFG_AD_SEL0_SET(config->ad_func_sel[0])
91 | PPI_CMD_AD_CFG_BYTE_SEL0_SET(config->byte_sel[0]);
92 ppi->CMD[index].AD_CFG = tmp;
93
94 tmp = PPI_CMD_CTRL_CFG_IO_CFG7_SET(config->ctrl_pin_value[7])
95 | PPI_CMD_CTRL_CFG_IO_CFG6_SET(config->ctrl_pin_value[6])
96 | PPI_CMD_CTRL_CFG_IO_CFG5_SET(config->ctrl_pin_value[5])
97 | PPI_CMD_CTRL_CFG_IO_CFG4_SET(config->ctrl_pin_value[4])
98 | PPI_CMD_CTRL_CFG_IO_CFG3_SET(config->ctrl_pin_value[3])
99 | PPI_CMD_CTRL_CFG_IO_CFG2_SET(config->ctrl_pin_value[2])
100 | PPI_CMD_CTRL_CFG_IO_CFG1_SET(config->ctrl_pin_value[1])
101 | PPI_CMD_CTRL_CFG_IO_CFG0_SET(config->ctrl_pin_value[0]);
102 ppi->CMD[index].CTRL_CFG = tmp;
103 }
104