1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SOC_H
10 #define HPM_SOC_H
11 
12 
13 /* List of external IRQs */
14 #define IRQn_GPIO0_A                   1       /* GPIO0_A IRQ */
15 #define IRQn_GPIO0_B                   2       /* GPIO0_B IRQ */
16 #define IRQn_GPIO0_X                   3       /* GPIO0_X IRQ */
17 #define IRQn_GPIO0_Y                   4       /* GPIO0_Y IRQ */
18 #define IRQn_GPTMR0                    5       /* GPTMR0 IRQ */
19 #define IRQn_GPTMR1                    6       /* GPTMR1 IRQ */
20 #define IRQn_GPTMR2                    7       /* GPTMR2 IRQ */
21 #define IRQn_GPTMR3                    8       /* GPTMR3 IRQ */
22 #define IRQn_UART0                     13      /* UART0 IRQ */
23 #define IRQn_UART1                     14      /* UART1 IRQ */
24 #define IRQn_UART2                     15      /* UART2 IRQ */
25 #define IRQn_UART3                     16      /* UART3 IRQ */
26 #define IRQn_UART4                     17      /* UART4 IRQ */
27 #define IRQn_UART5                     18      /* UART5 IRQ */
28 #define IRQn_UART6                     19      /* UART6 IRQ */
29 #define IRQn_UART7                     20      /* UART7 IRQ */
30 #define IRQn_I2C0                      21      /* I2C0 IRQ */
31 #define IRQn_I2C1                      22      /* I2C1 IRQ */
32 #define IRQn_I2C2                      23      /* I2C2 IRQ */
33 #define IRQn_I2C3                      24      /* I2C3 IRQ */
34 #define IRQn_SPI0                      25      /* SPI0 IRQ */
35 #define IRQn_SPI1                      26      /* SPI1 IRQ */
36 #define IRQn_SPI2                      27      /* SPI2 IRQ */
37 #define IRQn_SPI3                      28      /* SPI3 IRQ */
38 #define IRQn_TSNS                      29      /* TSNS IRQ */
39 #define IRQn_MBX0A                     30      /* MBX0A IRQ */
40 #define IRQn_MBX0B                     31      /* MBX0B IRQ */
41 #define IRQn_EWDG0                     32      /* EWDG0 IRQ */
42 #define IRQn_EWDG1                     33      /* EWDG1 IRQ */
43 #define IRQn_HDMA                      34      /* HDMA IRQ */
44 #define IRQn_MCAN0                     35      /* MCAN0 IRQ */
45 #define IRQn_MCAN1                     36      /* MCAN1 IRQ */
46 #define IRQn_MCAN2                     37      /* MCAN2 IRQ */
47 #define IRQn_MCAN3                     38      /* MCAN3 IRQ */
48 #define IRQn_PTPC                      39      /* PTPC IRQ */
49 #define IRQn_PWM0                      40      /* PWM0 IRQ */
50 #define IRQn_QEI0                      41      /* QEI0 IRQ */
51 #define IRQn_SEI0                      42      /* SEI0 IRQ */
52 #define IRQn_MMC0                      43      /* MMC0 IRQ */
53 #define IRQn_TRGMUX0                   44      /* TRGMUX0 IRQ */
54 #define IRQn_PWM1                      45      /* PWM1 IRQ */
55 #define IRQn_QEI1                      46      /* QEI1 IRQ */
56 #define IRQn_SEI1                      47      /* SEI1 IRQ */
57 #define IRQn_MMC1                      48      /* MMC1 IRQ */
58 #define IRQn_TRGMUX1                   49      /* TRGMUX1 IRQ */
59 #define IRQn_RDC                       50      /* RDC IRQ */
60 #define IRQn_USB0                      51      /* USB0 IRQ */
61 #define IRQn_XPI0                      52      /* XPI0 IRQ */
62 #define IRQn_SDP                       53      /* SDP IRQ */
63 #define IRQn_PSEC                      54      /* PSEC IRQ */
64 #define IRQn_SECMON                    55      /* SECMON IRQ */
65 #define IRQn_RNG                       56      /* RNG IRQ */
66 #define IRQn_FUSE                      57      /* FUSE IRQ */
67 #define IRQn_ADC0                      58      /* ADC0 IRQ */
68 #define IRQn_ADC1                      59      /* ADC1 IRQ */
69 #define IRQn_DAC0                      60      /* DAC0 IRQ */
70 #define IRQn_DAC1                      61      /* DAC1 IRQ */
71 #define IRQn_ACMP_0                    62      /* ACMP_0 IRQ */
72 #define IRQn_ACMP_1                    63      /* ACMP_1 IRQ */
73 #define IRQn_SYSCTL                    64      /* SYSCTL IRQ */
74 #define IRQn_PGPIO                     65      /* PGPIO IRQ */
75 #define IRQn_PTMR                      66      /* PTMR IRQ */
76 #define IRQn_PUART                     67      /* PUART IRQ */
77 #define IRQn_PEWDG                     68      /* PEWDG IRQ */
78 #define IRQn_BROWNOUT                  69      /* BROWNOUT IRQ */
79 #define IRQn_PAD_WAKEUP                70      /* PAD_WAKEUP IRQ */
80 #define IRQn_DEBUG0                    71      /* DEBUG0 IRQ */
81 #define IRQn_DEBUG1                    72      /* DEBUG1 IRQ */
82 
83 #include "hpm_common.h"
84 
85 #include "hpm_gpio_regs.h"
86 /* Address of GPIO instances */
87 /* FGPIO base address */
88 #define HPM_FGPIO_BASE (0xC0000UL)
89 /* FGPIO base pointer */
90 #define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE)
91 /* GPIO0 base address */
92 #define HPM_GPIO0_BASE (0xF00D0000UL)
93 /* GPIO0 base pointer */
94 #define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE)
95 /* PGPIO base address */
96 #define HPM_PGPIO_BASE (0xF411C000UL)
97 /* PGPIO base pointer */
98 #define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE)
99 
100 /* Address of DM instances */
101 /* DM base address */
102 #define HPM_DM_BASE (0x30000000UL)
103 
104 #include "hpm_plic_regs.h"
105 /* Address of PLIC instances */
106 /* PLIC base address */
107 #define HPM_PLIC_BASE (0xE4000000UL)
108 /* PLIC base pointer */
109 #define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE)
110 
111 #include "hpm_mchtmr_regs.h"
112 /* Address of MCHTMR instances */
113 /* MCHTMR base address */
114 #define HPM_MCHTMR_BASE (0xE6000000UL)
115 /* MCHTMR base pointer */
116 #define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE)
117 
118 #include "hpm_plic_sw_regs.h"
119 /* Address of PLICSW instances */
120 /* PLICSW base address */
121 #define HPM_PLICSW_BASE (0xE6400000UL)
122 /* PLICSW base pointer */
123 #define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE)
124 
125 #include "hpm_gptmr_regs.h"
126 /* Address of GPTMR instances */
127 /* GPTMR0 base address */
128 #define HPM_GPTMR0_BASE (0xF0000000UL)
129 /* GPTMR0 base pointer */
130 #define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE)
131 /* GPTMR1 base address */
132 #define HPM_GPTMR1_BASE (0xF0004000UL)
133 /* GPTMR1 base pointer */
134 #define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE)
135 /* GPTMR2 base address */
136 #define HPM_GPTMR2_BASE (0xF0008000UL)
137 /* GPTMR2 base pointer */
138 #define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE)
139 /* GPTMR3 base address */
140 #define HPM_GPTMR3_BASE (0xF000C000UL)
141 /* GPTMR3 base pointer */
142 #define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE)
143 /* PTMR base address */
144 #define HPM_PTMR_BASE (0xF4120000UL)
145 /* PTMR base pointer */
146 #define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE)
147 
148 #include "hpm_uart_regs.h"
149 /* Address of UART instances */
150 /* UART0 base address */
151 #define HPM_UART0_BASE (0xF0040000UL)
152 /* UART0 base pointer */
153 #define HPM_UART0 ((UART_Type *) HPM_UART0_BASE)
154 /* UART1 base address */
155 #define HPM_UART1_BASE (0xF0044000UL)
156 /* UART1 base pointer */
157 #define HPM_UART1 ((UART_Type *) HPM_UART1_BASE)
158 /* UART2 base address */
159 #define HPM_UART2_BASE (0xF0048000UL)
160 /* UART2 base pointer */
161 #define HPM_UART2 ((UART_Type *) HPM_UART2_BASE)
162 /* UART3 base address */
163 #define HPM_UART3_BASE (0xF004C000UL)
164 /* UART3 base pointer */
165 #define HPM_UART3 ((UART_Type *) HPM_UART3_BASE)
166 /* UART4 base address */
167 #define HPM_UART4_BASE (0xF0050000UL)
168 /* UART4 base pointer */
169 #define HPM_UART4 ((UART_Type *) HPM_UART4_BASE)
170 /* UART5 base address */
171 #define HPM_UART5_BASE (0xF0054000UL)
172 /* UART5 base pointer */
173 #define HPM_UART5 ((UART_Type *) HPM_UART5_BASE)
174 /* UART6 base address */
175 #define HPM_UART6_BASE (0xF0058000UL)
176 /* UART6 base pointer */
177 #define HPM_UART6 ((UART_Type *) HPM_UART6_BASE)
178 /* UART7 base address */
179 #define HPM_UART7_BASE (0xF005C000UL)
180 /* UART7 base pointer */
181 #define HPM_UART7 ((UART_Type *) HPM_UART7_BASE)
182 /* PUART base address */
183 #define HPM_PUART_BASE (0xF4124000UL)
184 /* PUART base pointer */
185 #define HPM_PUART ((UART_Type *) HPM_PUART_BASE)
186 
187 #include "hpm_i2c_regs.h"
188 /* Address of I2C instances */
189 /* I2C0 base address */
190 #define HPM_I2C0_BASE (0xF0060000UL)
191 /* I2C0 base pointer */
192 #define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE)
193 /* I2C1 base address */
194 #define HPM_I2C1_BASE (0xF0064000UL)
195 /* I2C1 base pointer */
196 #define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE)
197 /* I2C2 base address */
198 #define HPM_I2C2_BASE (0xF0068000UL)
199 /* I2C2 base pointer */
200 #define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE)
201 /* I2C3 base address */
202 #define HPM_I2C3_BASE (0xF006C000UL)
203 /* I2C3 base pointer */
204 #define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE)
205 
206 #include "hpm_spi_regs.h"
207 /* Address of SPI instances */
208 /* SPI0 base address */
209 #define HPM_SPI0_BASE (0xF0070000UL)
210 /* SPI0 base pointer */
211 #define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE)
212 /* SPI1 base address */
213 #define HPM_SPI1_BASE (0xF0074000UL)
214 /* SPI1 base pointer */
215 #define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE)
216 /* SPI2 base address */
217 #define HPM_SPI2_BASE (0xF0078000UL)
218 /* SPI2 base pointer */
219 #define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE)
220 /* SPI3 base address */
221 #define HPM_SPI3_BASE (0xF007C000UL)
222 /* SPI3 base pointer */
223 #define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE)
224 
225 #include "hpm_crc_regs.h"
226 /* Address of CRC instances */
227 /* CRC base address */
228 #define HPM_CRC_BASE (0xF0080000UL)
229 /* CRC base pointer */
230 #define HPM_CRC ((CRC_Type *) HPM_CRC_BASE)
231 
232 #include "hpm_tsns_regs.h"
233 /* Address of TSNS instances */
234 /* TSNS base address */
235 #define HPM_TSNS_BASE (0xF0090000UL)
236 /* TSNS base pointer */
237 #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE)
238 
239 #include "hpm_mbx_regs.h"
240 /* Address of MBX instances */
241 /* MBX0A base address */
242 #define HPM_MBX0A_BASE (0xF00A0000UL)
243 /* MBX0A base pointer */
244 #define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE)
245 /* MBX0B base address */
246 #define HPM_MBX0B_BASE (0xF00A4000UL)
247 /* MBX0B base pointer */
248 #define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE)
249 
250 #include "hpm_ewdg_regs.h"
251 /* Address of EWDG instances */
252 /* EWDG0 base address */
253 #define HPM_EWDG0_BASE (0xF00B0000UL)
254 /* EWDG0 base pointer */
255 #define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE)
256 /* EWDG1 base address */
257 #define HPM_EWDG1_BASE (0xF00B4000UL)
258 /* EWDG1 base pointer */
259 #define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE)
260 /* PEWDG base address */
261 #define HPM_PEWDG_BASE (0xF4128000UL)
262 /* PEWDG base pointer */
263 #define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE)
264 
265 #include "hpm_dmamux_regs.h"
266 /* Address of DMAMUX instances */
267 /* DMAMUX base address */
268 #define HPM_DMAMUX_BASE (0xF00C4000UL)
269 /* DMAMUX base pointer */
270 #define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE)
271 
272 #include "hpm_dmav2_regs.h"
273 /* Address of DMAV2 instances */
274 /* HDMA base address */
275 #define HPM_HDMA_BASE (0xF00C8000UL)
276 /* HDMA base pointer */
277 #define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE)
278 
279 #include "hpm_gpiom_regs.h"
280 /* Address of GPIOM instances */
281 /* GPIOM base address */
282 #define HPM_GPIOM_BASE (0xF00D8000UL)
283 /* GPIOM base pointer */
284 #define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE)
285 
286 #include "hpm_mcan_regs.h"
287 /* Address of MCAN instances */
288 /* MCAN0 base address */
289 #define HPM_MCAN0_BASE (0xF0280000UL)
290 /* MCAN0 base pointer */
291 #define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE)
292 /* MCAN1 base address */
293 #define HPM_MCAN1_BASE (0xF0284000UL)
294 /* MCAN1 base pointer */
295 #define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE)
296 /* MCAN2 base address */
297 #define HPM_MCAN2_BASE (0xF0288000UL)
298 /* MCAN2 base pointer */
299 #define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE)
300 /* MCAN3 base address */
301 #define HPM_MCAN3_BASE (0xF028C000UL)
302 /* MCAN3 base pointer */
303 #define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE)
304 
305 #include "hpm_ptpc_regs.h"
306 /* Address of PTPC instances */
307 /* PTPC base address */
308 #define HPM_PTPC_BASE (0xF02FC000UL)
309 /* PTPC base pointer */
310 #define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE)
311 
312 #include "hpm_qeiv2_regs.h"
313 /* Address of QEIV2 instances */
314 /* QEI0 base address */
315 #define HPM_QEI0_BASE (0xF0300000UL)
316 /* QEI0 base pointer */
317 #define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE)
318 /* QEI1 base address */
319 #define HPM_QEI1_BASE (0xF0304000UL)
320 /* QEI1 base pointer */
321 #define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE)
322 
323 #include "hpm_qeo_regs.h"
324 /* Address of QEO instances */
325 /* QEO0 base address */
326 #define HPM_QEO0_BASE (0xF0308000UL)
327 /* QEO0 base pointer */
328 #define HPM_QEO0 ((QEO_Type *) HPM_QEO0_BASE)
329 /* QEO1 base address */
330 #define HPM_QEO1_BASE (0xF030C000UL)
331 /* QEO1 base pointer */
332 #define HPM_QEO1 ((QEO_Type *) HPM_QEO1_BASE)
333 
334 #include "hpm_mmc_regs.h"
335 /* Address of MMC instances */
336 /* MMC0 base address */
337 #define HPM_MMC0_BASE (0xF0310000UL)
338 /* MMC0 base pointer */
339 #define HPM_MMC0 ((MMC_Type *) HPM_MMC0_BASE)
340 /* MMC1 base address */
341 #define HPM_MMC1_BASE (0xF0314000UL)
342 /* MMC1 base pointer */
343 #define HPM_MMC1 ((MMC_Type *) HPM_MMC1_BASE)
344 
345 #include "hpm_pwm_regs.h"
346 /* Address of PWM instances */
347 /* PWM0 base address */
348 #define HPM_PWM0_BASE (0xF0318000UL)
349 /* PWM0 base pointer */
350 #define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE)
351 /* PWM1 base address */
352 #define HPM_PWM1_BASE (0xF031C000UL)
353 /* PWM1 base pointer */
354 #define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE)
355 
356 #include "hpm_rdc_regs.h"
357 /* Address of RDC instances */
358 /* RDC base address */
359 #define HPM_RDC_BASE (0xF0320000UL)
360 /* RDC base pointer */
361 #define HPM_RDC ((RDC_Type *) HPM_RDC_BASE)
362 
363 #include "hpm_plb_regs.h"
364 /* Address of PLB instances */
365 /* PLB base address */
366 #define HPM_PLB_BASE (0xF0324000UL)
367 /* PLB base pointer */
368 #define HPM_PLB ((PLB_Type *) HPM_PLB_BASE)
369 
370 #include "hpm_synt_regs.h"
371 /* Address of SYNT instances */
372 /* SYNT base address */
373 #define HPM_SYNT_BASE (0xF0328000UL)
374 /* SYNT base pointer */
375 #define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE)
376 
377 #include "hpm_sei_regs.h"
378 /* Address of SEI instances */
379 /* SEI base address */
380 #define HPM_SEI_BASE (0xF032C000UL)
381 /* SEI base pointer */
382 #define HPM_SEI ((SEI_Type *) HPM_SEI_BASE)
383 
384 #include "hpm_trgm_regs.h"
385 /* Address of TRGM instances */
386 /* TRGM0 base address */
387 #define HPM_TRGM0_BASE (0xF033C000UL)
388 /* TRGM0 base pointer */
389 #define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE)
390 
391 #include "hpm_usb_regs.h"
392 /* Address of USB instances */
393 /* USB0 base address */
394 #define HPM_USB0_BASE (0xF300C000UL)
395 /* USB0 base pointer */
396 #define HPM_USB0 ((USB_Type *) HPM_USB0_BASE)
397 
398 /* Address of ROMC instances */
399 /* ROMC base address */
400 #define HPM_ROMC_BASE (0xF3014000UL)
401 
402 #include "hpm_sdp_regs.h"
403 /* Address of SDP instances */
404 /* SDP base address */
405 #define HPM_SDP_BASE (0xF3040000UL)
406 /* SDP base pointer */
407 #define HPM_SDP ((SDP_Type *) HPM_SDP_BASE)
408 
409 #include "hpm_sec_regs.h"
410 /* Address of SEC instances */
411 /* SEC base address */
412 #define HPM_SEC_BASE (0xF3044000UL)
413 /* SEC base pointer */
414 #define HPM_SEC ((SEC_Type *) HPM_SEC_BASE)
415 
416 #include "hpm_mon_regs.h"
417 /* Address of MON instances */
418 /* MON base address */
419 #define HPM_MON_BASE (0xF3048000UL)
420 /* MON base pointer */
421 #define HPM_MON ((MON_Type *) HPM_MON_BASE)
422 
423 #include "hpm_rng_regs.h"
424 /* Address of RNG instances */
425 /* RNG base address */
426 #define HPM_RNG_BASE (0xF304C000UL)
427 /* RNG base pointer */
428 #define HPM_RNG ((RNG_Type *) HPM_RNG_BASE)
429 
430 #include "hpm_otp_regs.h"
431 /* Address of OTP instances */
432 /* OTP base address */
433 #define HPM_OTP_BASE (0xF3050000UL)
434 /* OTP base pointer */
435 #define HPM_OTP ((OTP_Type *) HPM_OTP_BASE)
436 
437 #include "hpm_keym_regs.h"
438 /* Address of KEYM instances */
439 /* KEYM base address */
440 #define HPM_KEYM_BASE (0xF3054000UL)
441 /* KEYM base pointer */
442 #define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE)
443 
444 #include "hpm_adc16_regs.h"
445 /* Address of ADC16 instances */
446 /* ADC0 base address */
447 #define HPM_ADC0_BASE (0xF3080000UL)
448 /* ADC0 base pointer */
449 #define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE)
450 /* ADC1 base address */
451 #define HPM_ADC1_BASE (0xF3084000UL)
452 /* ADC1 base pointer */
453 #define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE)
454 
455 #include "hpm_dac_regs.h"
456 /* Address of DAC instances */
457 /* DAC0 base address */
458 #define HPM_DAC0_BASE (0xF3090000UL)
459 /* DAC0 base pointer */
460 #define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE)
461 /* DAC1 base address */
462 #define HPM_DAC1_BASE (0xF3094000UL)
463 /* DAC1 base pointer */
464 #define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE)
465 
466 #include "hpm_opamp_regs.h"
467 /* Address of OPAMP instances */
468 /* OPAMP0 base address */
469 #define HPM_OPAMP0_BASE (0xF30A0000UL)
470 /* OPAMP0 base pointer */
471 #define HPM_OPAMP0 ((OPAMP_Type *) HPM_OPAMP0_BASE)
472 /* OPAMP1 base address */
473 #define HPM_OPAMP1_BASE (0xF30A4000UL)
474 /* OPAMP1 base pointer */
475 #define HPM_OPAMP1 ((OPAMP_Type *) HPM_OPAMP1_BASE)
476 
477 #include "hpm_acmp_regs.h"
478 /* Address of ACMP instances */
479 /* ACMP base address */
480 #define HPM_ACMP_BASE (0xF30B0000UL)
481 /* ACMP base pointer */
482 #define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE)
483 
484 #include "hpm_sysctl_regs.h"
485 /* Address of SYSCTL instances */
486 /* SYSCTL base address */
487 #define HPM_SYSCTL_BASE (0xF4000000UL)
488 /* SYSCTL base pointer */
489 #define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE)
490 
491 #include "hpm_ioc_regs.h"
492 /* Address of IOC instances */
493 /* IOC base address */
494 #define HPM_IOC_BASE (0xF4040000UL)
495 /* IOC base pointer */
496 #define HPM_IOC ((IOC_Type *) HPM_IOC_BASE)
497 /* PIOC base address */
498 #define HPM_PIOC_BASE (0xF4118000UL)
499 /* PIOC base pointer */
500 #define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE)
501 
502 #include "hpm_pllctlv2_regs.h"
503 /* Address of PLLCTLV2 instances */
504 /* PLLCTLV2 base address */
505 #define HPM_PLLCTLV2_BASE (0xF40C0000UL)
506 /* PLLCTLV2 base pointer */
507 #define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE)
508 
509 #include "hpm_ppor_regs.h"
510 /* Address of PPOR instances */
511 /* PPOR base address */
512 #define HPM_PPOR_BASE (0xF4100000UL)
513 /* PPOR base pointer */
514 #define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE)
515 
516 #include "hpm_pcfg_regs.h"
517 /* Address of PCFG instances */
518 /* PCFG base address */
519 #define HPM_PCFG_BASE (0xF4104000UL)
520 /* PCFG base pointer */
521 #define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE)
522 
523 #include "hpm_pgpr_regs.h"
524 /* Address of PGPR instances */
525 /* PGPR0 base address */
526 #define HPM_PGPR0_BASE (0xF4110000UL)
527 /* PGPR0 base pointer */
528 #define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE)
529 /* PGPR1 base address */
530 #define HPM_PGPR1_BASE (0xF4114000UL)
531 /* PGPR1 base pointer */
532 #define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE)
533 
534 #include "hpm_pdgo_regs.h"
535 /* Address of PDGO instances */
536 /* PDGO base address */
537 #define HPM_PDGO_BASE (0xF4134000UL)
538 /* PDGO base pointer */
539 #define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE)
540 
541 
542 #include "riscv/riscv_core.h"
543 #include "hpm_csr_regs.h"
544 #include "hpm_interrupt.h"
545 #include "hpm_misc.h"
546 #include "hpm_dmamux_src.h"
547 #include "hpm_trgmmux_src.h"
548 #include "hpm_iomux.h"
549 #include "hpm_pmic_iomux.h"
550 #endif /* HPM_SOC_H */
551