1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_TRGMMUX_SRC_H 10 #define HPM_TRGMMUX_SRC_H 11 12 /* trgm0_input mux definitions */ 13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) 14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) 15 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x2UL) 16 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x3UL) 17 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x4UL) 18 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x5UL) 19 #define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x6UL) 20 #define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x7UL) 21 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x8UL) 22 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x9UL) 23 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0xAUL) 24 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0xBUL) 25 #define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0xCUL) 26 #define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0xDUL) 27 #define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0xEUL) 28 #define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0xFUL) 29 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x10UL) 30 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x11UL) 31 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x12UL) 32 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x13UL) 33 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x14UL) 34 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x15UL) 35 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x16UL) 36 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x17UL) 37 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x18UL) 38 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x19UL) 39 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x1AUL) 40 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x1BUL) 41 #define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_0 (0x1CUL) 42 #define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_1 (0x1DUL) 43 #define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_0 (0x1EUL) 44 #define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_1 (0x1FUL) 45 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_0 (0x20UL) 46 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_1 (0x21UL) 47 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_2 (0x22UL) 48 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_3 (0x23UL) 49 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_4 (0x24UL) 50 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_5 (0x25UL) 51 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_6 (0x26UL) 52 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_7 (0x27UL) 53 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_0 (0x28UL) 54 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_1 (0x29UL) 55 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_2 (0x2AUL) 56 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_3 (0x2BUL) 57 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_4 (0x2CUL) 58 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_5 (0x2DUL) 59 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_6 (0x2EUL) 60 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_7 (0x2FUL) 61 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x30UL) 62 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x31UL) 63 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x32UL) 64 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x33UL) 65 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x34UL) 66 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x35UL) 67 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x36UL) 68 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x37UL) 69 #define HPM_TRGM0_INPUT_SRC_PWM1_CH8REF (0x38UL) 70 #define HPM_TRGM0_INPUT_SRC_PWM1_CH9REF (0x39UL) 71 #define HPM_TRGM0_INPUT_SRC_PWM1_CH10REF (0x3AUL) 72 #define HPM_TRGM0_INPUT_SRC_PWM1_CH11REF (0x3BUL) 73 #define HPM_TRGM0_INPUT_SRC_PWM1_CH12REF (0x3CUL) 74 #define HPM_TRGM0_INPUT_SRC_PWM1_CH13REF (0x3DUL) 75 #define HPM_TRGM0_INPUT_SRC_PWM1_CH14REF (0x3EUL) 76 #define HPM_TRGM0_INPUT_SRC_PWM1_CH15REF (0x3FUL) 77 #define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x40UL) 78 #define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x41UL) 79 #define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x42UL) 80 #define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x43UL) 81 #define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x44UL) 82 #define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x45UL) 83 #define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x46UL) 84 #define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x47UL) 85 #define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x48UL) 86 #define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x49UL) 87 #define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x4AUL) 88 #define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x4BUL) 89 #define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x4CUL) 90 #define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x4DUL) 91 #define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x4EUL) 92 #define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x4FUL) 93 #define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x50UL) 94 #define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x51UL) 95 #define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x52UL) 96 #define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x53UL) 97 #define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x54UL) 98 #define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x55UL) 99 #define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x56UL) 100 #define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x57UL) 101 #define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x58UL) 102 #define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x59UL) 103 #define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x5AUL) 104 #define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x5BUL) 105 #define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x5CUL) 106 #define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x5DUL) 107 #define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x5EUL) 108 #define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x5FUL) 109 #define HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 (0x60UL) 110 #define HPM_TRGM0_INPUT_SRC_RDC_TRGO_1 (0x61UL) 111 #define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0x62UL) 112 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x63UL) 113 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x64UL) 114 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x65UL) 115 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x66UL) 116 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x67UL) 117 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x68UL) 118 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x69UL) 119 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x6AUL) 120 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x6BUL) 121 #define HPM_TRGM0_INPUT_SRC_PWM0_FAULT0 (0x6CUL) 122 #define HPM_TRGM0_INPUT_SRC_PWM0_FAULT1 (0x6DUL) 123 #define HPM_TRGM0_INPUT_SRC_PWM1_FAULT0 (0x6EUL) 124 #define HPM_TRGM0_INPUT_SRC_PWM1_FAULT1 (0x6FUL) 125 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x70UL) 126 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x71UL) 127 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN2 (0x72UL) 128 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN3 (0x73UL) 129 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN4 (0x74UL) 130 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN5 (0x75UL) 131 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN6 (0x76UL) 132 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN7 (0x77UL) 133 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0x78UL) 134 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0x79UL) 135 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN2 (0x7AUL) 136 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN3 (0x7BUL) 137 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN4 (0x7CUL) 138 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN5 (0x7DUL) 139 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN6 (0x7EUL) 140 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN7 (0x7FUL) 141 142 /* trgm0_output mux definitions */ 143 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_0 (0x0UL) 144 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_1 (0x1UL) 145 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_2 (0x2UL) 146 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_3 (0x3UL) 147 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_4 (0x4UL) 148 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_5 (0x5UL) 149 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_6 (0x6UL) 150 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_7 (0x7UL) 151 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_0 (0x8UL) 152 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_1 (0x9UL) 153 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_2 (0xAUL) 154 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_3 (0xBUL) 155 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_4 (0xCUL) 156 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_5 (0xDUL) 157 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_6 (0xEUL) 158 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_7 (0xFUL) 159 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x10UL) 160 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x11UL) 161 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x12UL) 162 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x13UL) 163 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x14UL) 164 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x15UL) 165 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x16UL) 166 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x17UL) 167 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x18UL) 168 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x19UL) 169 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x1AUL) 170 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x1BUL) 171 #define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN (0x1CUL) 172 #define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN (0x1DUL) 173 #define HPM_TRGM0_OUTPUT_SRC_DAC0_BUFTRG (0x1EUL) 174 #define HPM_TRGM0_OUTPUT_SRC_DAC1_BUFTRG (0x1FUL) 175 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x20UL) 176 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x21UL) 177 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x22UL) 178 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x23UL) 179 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x24UL) 180 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x25UL) 181 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x26UL) 182 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x27UL) 183 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x28UL) 184 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x29UL) 185 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x2AUL) 186 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x2BUL) 187 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x2CUL) 188 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x2DUL) 189 #define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP (0x2EUL) 190 #define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP (0x2FUL) 191 #define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x30UL) 192 #define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x31UL) 193 #define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x32UL) 194 #define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x33UL) 195 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x34UL) 196 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x35UL) 197 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x36UL) 198 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x37UL) 199 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x38UL) 200 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x39UL) 201 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x3AUL) 202 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x3BUL) 203 #define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN0 (0x3CUL) 204 #define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN1 (0x3DUL) 205 #define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN0 (0x3EUL) 206 #define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN1 (0x3FUL) 207 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x40UL) 208 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x41UL) 209 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x42UL) 210 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x43UL) 211 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x44UL) 212 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x45UL) 213 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x46UL) 214 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x47UL) 215 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x48UL) 216 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x49UL) 217 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x4AUL) 218 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x4BUL) 219 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x4CUL) 220 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x4DUL) 221 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x4EUL) 222 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x4FUL) 223 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x50UL) 224 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x51UL) 225 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x52UL) 226 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x53UL) 227 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x54UL) 228 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x55UL) 229 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x56UL) 230 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x57UL) 231 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x58UL) 232 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x59UL) 233 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x5AUL) 234 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x5BUL) 235 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x5CUL) 236 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x5DUL) 237 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x5EUL) 238 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x5FUL) 239 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x60UL) 240 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x61UL) 241 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x62UL) 242 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x63UL) 243 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x64UL) 244 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x65UL) 245 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x66UL) 246 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x67UL) 247 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN8 (0x68UL) 248 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN9 (0x69UL) 249 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN10 (0x6AUL) 250 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN11 (0x6BUL) 251 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN12 (0x6CUL) 252 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN13 (0x6DUL) 253 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN14 (0x6EUL) 254 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN15 (0x6FUL) 255 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0x70UL) 256 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x71UL) 257 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0x72UL) 258 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x73UL) 259 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x74UL) 260 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x75UL) 261 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCI (0x76UL) 262 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCSYNCI (0x77UL) 263 #define HPM_TRGM0_OUTPUT_SRC_PWM1_SYNCI (0x78UL) 264 #define HPM_TRGM0_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x79UL) 265 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI0 (0x7AUL) 266 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI1 (0x7BUL) 267 #define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN0 (0x7CUL) 268 #define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN1 (0x7DUL) 269 #define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0x7EUL) 270 #define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x7FUL) 271 #define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x80UL) 272 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x81UL) 273 #define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x82UL) 274 #define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0x83UL) 275 #define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0x84UL) 276 #define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0x85UL) 277 #define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0x86UL) 278 #define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0x87UL) 279 #define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0x88UL) 280 281 /* trgm0_filter mux definitions */ 282 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) 283 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) 284 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) 285 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) 286 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) 287 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) 288 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) 289 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) 290 #define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) 291 #define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) 292 #define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) 293 #define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) 294 #define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) 295 #define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) 296 #define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) 297 #define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) 298 #define HPM_TRGM0_FILTER_SRC_TRGM_IN0 (0x10UL) 299 #define HPM_TRGM0_FILTER_SRC_TRGM_IN1 (0x11UL) 300 #define HPM_TRGM0_FILTER_SRC_TRGM_IN2 (0x12UL) 301 #define HPM_TRGM0_FILTER_SRC_TRGM_IN3 (0x13UL) 302 #define HPM_TRGM0_FILTER_SRC_TRGM_IN4 (0x14UL) 303 #define HPM_TRGM0_FILTER_SRC_TRGM_IN5 (0x15UL) 304 #define HPM_TRGM0_FILTER_SRC_TRGM_IN6 (0x16UL) 305 #define HPM_TRGM0_FILTER_SRC_TRGM_IN7 (0x17UL) 306 #define HPM_TRGM0_FILTER_SRC_PWM0_FAULT0 (0x18UL) 307 #define HPM_TRGM0_FILTER_SRC_PWM0_FAULT1 (0x19UL) 308 #define HPM_TRGM0_FILTER_SRC_PWM1_FAULT0 (0x1AUL) 309 #define HPM_TRGM0_FILTER_SRC_PWM1_FAULT1 (0x1BUL) 310 311 /* trgm0_dma mux definitions */ 312 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) 313 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) 314 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) 315 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) 316 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) 317 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) 318 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) 319 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) 320 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) 321 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) 322 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) 323 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) 324 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) 325 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) 326 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) 327 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) 328 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) 329 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) 330 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) 331 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) 332 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) 333 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) 334 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) 335 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) 336 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) 337 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) 338 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) 339 #define HPM_TRGM0_DMA_SRC_PWM1_CMP0 (0x1BUL) 340 #define HPM_TRGM0_DMA_SRC_PWM1_CMP1 (0x1CUL) 341 #define HPM_TRGM0_DMA_SRC_PWM1_CMP2 (0x1DUL) 342 #define HPM_TRGM0_DMA_SRC_PWM1_CMP3 (0x1EUL) 343 #define HPM_TRGM0_DMA_SRC_PWM1_CMP4 (0x1FUL) 344 #define HPM_TRGM0_DMA_SRC_PWM1_CMP5 (0x20UL) 345 #define HPM_TRGM0_DMA_SRC_PWM1_CMP6 (0x21UL) 346 #define HPM_TRGM0_DMA_SRC_PWM1_CMP7 (0x22UL) 347 #define HPM_TRGM0_DMA_SRC_PWM1_CMP8 (0x23UL) 348 #define HPM_TRGM0_DMA_SRC_PWM1_CMP9 (0x24UL) 349 #define HPM_TRGM0_DMA_SRC_PWM1_CMP10 (0x25UL) 350 #define HPM_TRGM0_DMA_SRC_PWM1_CMP11 (0x26UL) 351 #define HPM_TRGM0_DMA_SRC_PWM1_CMP12 (0x27UL) 352 #define HPM_TRGM0_DMA_SRC_PWM1_CMP13 (0x28UL) 353 #define HPM_TRGM0_DMA_SRC_PWM1_CMP14 (0x29UL) 354 #define HPM_TRGM0_DMA_SRC_PWM1_CMP15 (0x2AUL) 355 #define HPM_TRGM0_DMA_SRC_PWM1_CMP16 (0x2BUL) 356 #define HPM_TRGM0_DMA_SRC_PWM1_CMP17 (0x2CUL) 357 #define HPM_TRGM0_DMA_SRC_PWM1_CMP18 (0x2DUL) 358 #define HPM_TRGM0_DMA_SRC_PWM1_CMP19 (0x2EUL) 359 #define HPM_TRGM0_DMA_SRC_PWM1_CMP20 (0x2FUL) 360 #define HPM_TRGM0_DMA_SRC_PWM1_CMP21 (0x30UL) 361 #define HPM_TRGM0_DMA_SRC_PWM1_CMP22 (0x31UL) 362 #define HPM_TRGM0_DMA_SRC_PWM1_CMP23 (0x32UL) 363 #define HPM_TRGM0_DMA_SRC_PWM1_RLD (0x33UL) 364 #define HPM_TRGM0_DMA_SRC_PWM1_HALFRLD (0x34UL) 365 #define HPM_TRGM0_DMA_SRC_PWM1_XRLD (0x35UL) 366 #define HPM_TRGM0_DMA_SRC_QEI0 (0x36UL) 367 #define HPM_TRGM0_DMA_SRC_QEI1 (0x37UL) 368 #define HPM_TRGM0_DMA_SRC_MMC0 (0x38UL) 369 #define HPM_TRGM0_DMA_SRC_MMC1 (0x39UL) 370 #define HPM_TRGM0_DMA_SRC_SEI0 (0x3AUL) 371 #define HPM_TRGM0_DMA_SRC_SEI1 (0x3BUL) 372 #define HPM_TRGM0_DMA_SRC_TRGM0 (0x3CUL) 373 #define HPM_TRGM0_DMA_SRC_TRGM1 (0x3DUL) 374 375 376 377 #endif /* HPM_TRGMMUX_SRC_H */ 378