1 /* 2 * Copyright (c) 2022-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 #ifndef HPM_CLOCK_DRV_H 8 #define HPM_CLOCK_DRV_H 9 10 #include "hpm_common.h" 11 #include "hpm_sysctl_drv.h" 12 #include "hpm_csr_drv.h" 13 14 #define CLOCK_DIV_INVALID (~0UL) 15 16 /** 17 * @brief Error codes for clock driver 18 */ 19 enum { 20 status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), 21 status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), 22 status_clk_invalid = MAKE_STATUS(status_group_clk, 2), 23 status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), 24 status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), 25 status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), 26 status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), 27 status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), 28 status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), 29 status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), 30 status_clk_fixed = MAKE_STATUS(status_group_clk, 10), 31 32 }; 33 34 35 36 /** 37 * @brief Clock source group definitions 38 */ 39 #define CLK_SRC_GROUP_COMMON (0U) 40 #define CLK_SRC_GROUP_ADC (1U) 41 #define CLK_SRC_GROUP_WDG (3U) 42 #define CLK_SRC_GROUP_PMIC (4U) 43 #define CLK_SRC_GROUP_AHB (5U) 44 #define CLK_SRC_GROUP_AXI (6U) 45 #define CLK_SRC_GROUP_DAC (7U) 46 #define CLK_SRC_GROUP_CPU0 (9U) 47 #define CLK_SRC_GROUP_SRC (10U) 48 #define CLK_SRC_GROUP_PWDG (11U) 49 #define CLK_SRC_GROUP_INVALID (15U) 50 51 #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) 52 #define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) 53 #define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) 54 55 #define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) 56 57 /** 58 * @brief Clock source definitions 59 */ 60 typedef enum _clock_sources { 61 clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), 62 clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), 63 clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), 64 clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), 65 clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), 66 clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), 67 clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), 68 clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), 69 clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), 70 71 clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), 72 clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), 73 clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), 74 clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), 75 76 clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), 77 clk_dac_src_ana4 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), 78 clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), 79 80 clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), 81 clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), 82 83 clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), 84 clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), 85 86 clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), 87 } clk_src_t; 88 89 90 #define RESOURCE_INVALID (0xFFFFU) 91 #define RESOURCE_SHARED_CPU0 (0xFFFDU) 92 93 /* Clock NAME related Macros */ 94 #define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) 95 #define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) 96 #define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) 97 #define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) 98 99 /** 100 * @brief Peripheral Clock Type Description 101 */ 102 typedef enum _clock_name { 103 clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), 104 clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), 105 clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_CPU0, clock_node_cpu1), 106 clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), 107 clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), 108 clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), 109 clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), 110 clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), 111 clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), 112 clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), 113 clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), 114 clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), 115 clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), 116 clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), 117 clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), 118 clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), 119 clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), 120 clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), 121 clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), 122 clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), 123 clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), 124 clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), 125 clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), 126 clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), 127 clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), 128 clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), 129 clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), 130 clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), 131 clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), 132 clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), 133 clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), 134 clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), 135 clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), 136 137 clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), 138 clock_axi = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AXI, clock_node_axi), 139 clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_AXI, clock_node_axi), 140 clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_AXI, clock_node_axi), 141 clock_ahbp = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_AHB, clock_node_ahb), 142 143 clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), 144 clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), 145 clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), 146 clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), 147 clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), 148 clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), 149 clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), 150 clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), 151 clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), 152 clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), 153 clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), 154 clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI, 3), 155 clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI, 4), 156 clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), 157 clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), 158 clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), 159 clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 3), 160 clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 4), 161 clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), 162 clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 6), 163 clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 7), 164 clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 8), 165 clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 9), 166 clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), 167 clock_synt = MAKE_CLOCK_NAME(sysctl_resource_synt, CLK_SRC_GROUP_AHB, 11), 168 clock_sdm0 = MAKE_CLOCK_NAME(sysctl_resource_sdm0, CLK_SRC_GROUP_AHB, 13), 169 clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AHB, 14), 170 clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), 171 clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU0, 1), 172 clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 2), 173 174 175 /* For ADC, there are 2-stage clock source and divider configurations */ 176 clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), 177 clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), 178 clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), 179 clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), 180 clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), 181 clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), 182 183 /* For DAC, there are 2-stage clock source and divider configurations */ 184 clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), 185 clock_ana4 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana4), 186 clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), 187 clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), 188 189 /* Clock sources */ 190 clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), 191 clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), 192 clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), 193 clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), 194 clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), 195 clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), 196 clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 6), 197 clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 7), 198 } clock_name_t; 199 200 extern uint32_t hpm_core_clock; 201 202 #ifdef __cplusplus 203 extern "C" { 204 #endif 205 206 /** 207 * @brief Get specified IP frequency 208 * @param[in] clock_name IP clock name 209 * 210 * @return IP clock frequency in Hz 211 */ 212 uint32_t clock_get_frequency(clock_name_t clock_name); 213 214 /** 215 * @brief Get Clock frequency for selected clock source 216 * @param [in] source clock source 217 * @return clock frequency for selected clock source 218 */ 219 uint32_t get_frequency_for_source(clock_source_t source); 220 221 /** 222 * @brief Get the IP clock source 223 * Note: This API return the direct clock source 224 * @param [in] clock_name clock name 225 * @return IP clock source 226 */ 227 clk_src_t clock_get_source(clock_name_t clock_name); 228 229 /** 230 * @brief Get the IP clock divider 231 * Note:This API return the direct clock divider 232 * @param [in] clock_name clock name 233 * @return IP clock divider 234 */ 235 uint32_t clock_get_divider(clock_name_t clock_name); 236 237 /** 238 * @brief Set ADC clock source 239 * @param[in] clock_name ADC clock name 240 * @param[in] src ADC clock source 241 * 242 * @return #status_success Setting ADC clock source is successful 243 * #status_clk_invalid Invalid ADC clock 244 * #status_clk_src_invalid Invalid ADC clock source 245 */ 246 hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); 247 248 /** 249 * @brief Set DAC clock source 250 * @param[in] clock_name DAC clock name 251 * @param[in] src DAC clock source 252 * 253 * @return #status_success Setting DAC clock source is successful 254 * #status_clk_invalid Invalid DAC clock 255 * #status_clk_src_invalid Invalid DAC clock source 256 */ 257 hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); 258 259 /** 260 * @brief Set the WDG clock source 261 * @param [in] clock_name WDG clock name 262 * @param [in] src WDG clock source 263 * 264 * @retval status_success Setting WDG clock source is successful 265 * @retval status_invalid_argument Invalid WDG or invalid clock source 266 */ 267 hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); 268 269 /** 270 * @brief Set the IP clock source and divider 271 * @param[in] clock_name clock name 272 * @param[in] src clock source 273 * @param[in] div clock divider, valid range (1 - 256) 274 * 275 * @return #status_success Setting Clock source and divider is successful. 276 * #status_clk_src_invalid clock source is invalid. 277 * #status_clk_fixed clock source and divider is a fixed value 278 * #status_clk_shared_ahb Clock is shared with the AHB clock 279 * #status_clk_shared_axi0 Clock is shared with the AXI0 clock 280 * #status_clk_shared_axi1 CLock is shared with the AXI1 clock 281 * #status_clk_shared_axi2 Clock is shared with the AXI2 clock 282 * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock 283 * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock 284 */ 285 hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); 286 287 /** 288 * @brief Enable IP clock 289 * @param[in] clock_name IP clock name 290 */ 291 void clock_enable(clock_name_t clock_name); 292 293 /** 294 * @brief Disable IP clock 295 * @param[in] clock_name IP clock name 296 */ 297 void clock_disable(clock_name_t clock_name); 298 299 /** 300 * @brief Add IP to specified group 301 * @param[in] clock_name IP clock name 302 * @param[in] group resource group index, valid value: 0/1/2/3 303 */ 304 void clock_add_to_group(clock_name_t clock_name, uint32_t group); 305 306 /** 307 * @brief Remove IP from specified group 308 * @param[in] clock_name IP clock name 309 * @param[in] group resource group index, valid value: 0/1/2/3 310 */ 311 void clock_remove_from_group(clock_name_t clock_name, uint32_t group); 312 313 /** 314 * @brief Check IP in specified group 315 * @param[in] clock_name IP clock name 316 * @param[in] group resource group index, valid value: 0/1/2/3 317 * @return true if in group, false if not in group 318 */ 319 bool clock_check_in_group(clock_name_t clock_name, uint32_t group); 320 321 /** 322 * @brief Disconnect the clock group from specified CPU 323 * @param[in] group clock group index, value value is 0/1/2/3 324 * @param[in] cpu CPU index, valid value is 0/1 325 */ 326 void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); 327 328 /** 329 * @brief Disconnect the clock group from specified CPU 330 * @param[in] group clock group index, value value is 0/1/2/3 331 * @param[in] cpu CPU index, valid value is 0/1 332 */ 333 void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); 334 335 /** 336 * @brief Delay specified microseconds 337 * 338 * @param [in] us expected delay interval in microseconds 339 */ 340 void clock_cpu_delay_us(uint32_t us); 341 342 /** 343 * @brief Delay specified milliseconds 344 * 345 * @param [in] ms expected delay interval in milliseconds 346 */ 347 void clock_cpu_delay_ms(uint32_t ms); 348 349 /** 350 * @brief Update the Core clock frequency 351 */ 352 void clock_update_core_clock(void); 353 354 355 #ifdef __cplusplus 356 } 357 #endif 358 359 #endif /* HPM_CLOCK_DRV_H */ 360