1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYNT_H
10 #define HPM_SYNT_H
11 
12 typedef struct {
13     __RW uint32_t GCR;                         /* 0x0: Global control register */
14     __RW uint32_t RLD;                         /* 0x4: Counter reload register */
15     __R  uint8_t  RESERVED0[4];                /* 0x8 - 0xB: Reserved */
16     __R  uint32_t CNT;                         /* 0xC: Counter */
17     __R  uint8_t  RESERVED1[16];               /* 0x10 - 0x1F: Reserved */
18     __RW uint32_t CMP[4];                      /* 0x20 - 0x2C: Comparator */
19 } SYNT_Type;
20 
21 
22 /* Bitfield definition for register: GCR */
23 /*
24  * CRST (RW)
25  *
26  * 1- Reset counter
27  */
28 #define SYNT_GCR_CRST_MASK (0x2U)
29 #define SYNT_GCR_CRST_SHIFT (1U)
30 #define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK)
31 #define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT)
32 
33 /*
34  * CEN (RW)
35  *
36  * 1- Enable counter
37  */
38 #define SYNT_GCR_CEN_MASK (0x1U)
39 #define SYNT_GCR_CEN_SHIFT (0U)
40 #define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK)
41 #define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT)
42 
43 /* Bitfield definition for register: RLD */
44 /*
45  * RLD (RW)
46  *
47  * counter reload value
48  */
49 #define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL)
50 #define SYNT_RLD_RLD_SHIFT (0U)
51 #define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK)
52 #define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT)
53 
54 /* Bitfield definition for register: CNT */
55 /*
56  * CNT (RO)
57  *
58  * counter
59  */
60 #define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL)
61 #define SYNT_CNT_CNT_SHIFT (0U)
62 #define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT)
63 
64 /* Bitfield definition for register array: CMP */
65 /*
66  * CMP (RW)
67  *
68  * comparator value, the output will assert when counter count to this value
69  */
70 #define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL)
71 #define SYNT_CMP_CMP_SHIFT (0U)
72 #define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK)
73 #define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT)
74 
75 
76 
77 /* CMP register group index macro definition */
78 #define SYNT_CMP_0 (0UL)
79 #define SYNT_CMP_1 (1UL)
80 #define SYNT_CMP_2 (2UL)
81 #define SYNT_CMP_3 (3UL)
82 
83 
84 #endif /* HPM_SYNT_H */
85