1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_TRGMMUX_SRC_H 10 #define HPM_TRGMMUX_SRC_H 11 12 /* trgm0_input mux definitions */ 13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) 14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) 15 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) 16 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) 17 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) 18 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) 19 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) 20 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) 21 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) 22 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) 23 #define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) 24 #define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) 25 #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) 26 #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) 27 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) 28 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) 29 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) 30 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) 31 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) 32 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) 33 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) 34 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) 35 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) 36 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) 37 #define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) 38 #define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) 39 #define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) 40 #define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) 41 #define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) 42 #define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) 43 #define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) 44 #define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) 45 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) 46 #define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) 47 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) 48 #define HPM_TRGM0_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) 49 #define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) 50 #define HPM_TRGM0_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) 51 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) 52 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) 53 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) 54 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) 55 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) 56 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) 57 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) 58 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) 59 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) 60 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) 61 #define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) 62 #define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) 63 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) 64 65 /* trgm1_input mux definitions */ 66 #define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) 67 #define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) 68 #define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) 69 #define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) 70 #define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) 71 #define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) 72 #define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) 73 #define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) 74 #define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) 75 #define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) 76 #define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) 77 #define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) 78 #define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) 79 #define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) 80 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) 81 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) 82 #define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) 83 #define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) 84 #define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) 85 #define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) 86 #define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) 87 #define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) 88 #define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) 89 #define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) 90 #define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) 91 #define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) 92 #define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) 93 #define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) 94 #define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) 95 #define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) 96 #define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) 97 #define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) 98 #define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) 99 #define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) 100 #define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) 101 #define HPM_TRGM1_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) 102 #define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) 103 #define HPM_TRGM1_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) 104 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) 105 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) 106 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH0 (0x2CUL) 107 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH1 (0x2DUL) 108 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH2 (0x2EUL) 109 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH3 (0x2FUL) 110 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) 111 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) 112 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) 113 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) 114 #define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) 115 #define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) 116 #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) 117 118 /* trgm0_output mux definitions */ 119 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) 120 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) 121 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) 122 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) 123 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) 124 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) 125 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) 126 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) 127 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) 128 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) 129 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) 130 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) 131 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) 132 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) 133 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) 134 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) 135 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) 136 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) 137 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) 138 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) 139 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) 140 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) 141 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) 142 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) 143 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) 144 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) 145 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) 146 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) 147 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) 148 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) 149 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) 150 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) 151 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) 152 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) 153 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) 154 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) 155 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) 156 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) 157 #define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) 158 #define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) 159 #define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) 160 #define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) 161 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) 162 #define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) 163 #define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) 164 #define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) 165 #define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) 166 #define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) 167 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI2A (0x30UL) 168 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI2B (0x31UL) 169 #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI2C (0x32UL) 170 #define HPM_TRGM0_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) 171 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) 172 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) 173 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) 174 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) 175 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) 176 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) 177 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) 178 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) 179 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) 180 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) 181 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) 182 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) 183 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) 184 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) 185 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) 186 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) 187 188 /* trgm1_output mux definitions */ 189 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) 190 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) 191 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) 192 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) 193 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) 194 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) 195 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) 196 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) 197 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) 198 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) 199 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) 200 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) 201 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) 202 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) 203 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) 204 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) 205 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) 206 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) 207 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) 208 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) 209 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) 210 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) 211 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) 212 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) 213 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) 214 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) 215 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) 216 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) 217 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) 218 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) 219 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) 220 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) 221 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) 222 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) 223 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) 224 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) 225 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) 226 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) 227 #define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) 228 #define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) 229 #define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) 230 #define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) 231 #define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) 232 #define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) 233 #define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) 234 #define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) 235 #define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) 236 #define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) 237 #define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI3A (0x30UL) 238 #define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI3B (0x31UL) 239 #define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI3C (0x32UL) 240 #define HPM_TRGM1_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) 241 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) 242 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) 243 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) 244 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) 245 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) 246 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) 247 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) 248 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) 249 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) 250 #define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) 251 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) 252 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) 253 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) 254 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) 255 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) 256 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) 257 258 /* trgm0_filter mux definitions */ 259 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) 260 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) 261 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) 262 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) 263 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) 264 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) 265 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) 266 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) 267 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) 268 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) 269 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) 270 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) 271 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) 272 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) 273 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) 274 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) 275 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) 276 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) 277 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) 278 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) 279 280 /* trgm1_filter mux definitions */ 281 #define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) 282 #define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) 283 #define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) 284 #define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) 285 #define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) 286 #define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) 287 #define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) 288 #define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) 289 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) 290 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) 291 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) 292 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) 293 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) 294 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) 295 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) 296 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) 297 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) 298 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) 299 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) 300 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) 301 302 /* trgm0_dma mux definitions */ 303 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) 304 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) 305 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) 306 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) 307 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) 308 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) 309 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) 310 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) 311 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) 312 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) 313 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) 314 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) 315 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) 316 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) 317 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) 318 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) 319 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) 320 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) 321 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) 322 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) 323 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) 324 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) 325 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) 326 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) 327 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) 328 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) 329 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) 330 #define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) 331 #define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) 332 333 /* trgm1_dma mux definitions */ 334 #define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) 335 #define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) 336 #define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) 337 #define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) 338 #define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) 339 #define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) 340 #define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) 341 #define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) 342 #define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) 343 #define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) 344 #define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) 345 #define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) 346 #define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) 347 #define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) 348 #define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) 349 #define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) 350 #define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) 351 #define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) 352 #define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) 353 #define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) 354 #define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) 355 #define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) 356 #define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) 357 #define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) 358 #define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) 359 #define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) 360 #define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) 361 #define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) 362 #define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) 363 364 365 366 #endif /* HPM_TRGMMUX_SRC_H */ 367