1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_BACC_H 10 #define HPM_BACC_H 11 12 typedef struct { 13 __RW uint32_t CONFIG; /* 0x0: Access timing for access */ 14 __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ 15 __RW uint32_t PRE_TIME; /* 0x8: Timing gap before rising edge */ 16 __RW uint32_t POST_TIME; /* 0xC: Timing gap after rising edge */ 17 } BACC_Type; 18 19 20 /* Bitfield definition for register: CONFIG */ 21 /* 22 * FAST_WRITE (RW) 23 * 24 * Use fast write 25 * 0: Write normally 26 * 1: boost write 27 */ 28 #define BACC_CONFIG_FAST_WRITE_MASK (0x20000000UL) 29 #define BACC_CONFIG_FAST_WRITE_SHIFT (29U) 30 #define BACC_CONFIG_FAST_WRITE_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_WRITE_SHIFT) & BACC_CONFIG_FAST_WRITE_MASK) 31 #define BACC_CONFIG_FAST_WRITE_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_WRITE_MASK) >> BACC_CONFIG_FAST_WRITE_SHIFT) 32 33 /* 34 * FAST_READ (RW) 35 * 36 * Use fast read 37 * 0: Read normally 38 * 1: boost read 39 */ 40 #define BACC_CONFIG_FAST_READ_MASK (0x10000000UL) 41 #define BACC_CONFIG_FAST_READ_SHIFT (28U) 42 #define BACC_CONFIG_FAST_READ_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_READ_SHIFT) & BACC_CONFIG_FAST_READ_MASK) 43 #define BACC_CONFIG_FAST_READ_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_READ_MASK) >> BACC_CONFIG_FAST_READ_SHIFT) 44 45 /* 46 * TIMING (RW) 47 * 48 * Time in APB clock cycles, for battery timing penerate 49 */ 50 #define BACC_CONFIG_TIMING_MASK (0xFFFFU) 51 #define BACC_CONFIG_TIMING_SHIFT (0U) 52 #define BACC_CONFIG_TIMING_SET(x) (((uint32_t)(x) << BACC_CONFIG_TIMING_SHIFT) & BACC_CONFIG_TIMING_MASK) 53 #define BACC_CONFIG_TIMING_GET(x) (((uint32_t)(x) & BACC_CONFIG_TIMING_MASK) >> BACC_CONFIG_TIMING_SHIFT) 54 55 /* Bitfield definition for register: PRE_TIME */ 56 /* 57 * PRE_RATIO (RW) 58 * 59 * Ratio of guard band before rising edge 60 * 0: 0 61 * 1: 1/32768 of low level width 62 * 2: 1/16384 of low level width 63 * 14: 1/4 of low level width 64 * 15: 1/2 of low level width 65 */ 66 #define BACC_PRE_TIME_PRE_RATIO_MASK (0xF0000UL) 67 #define BACC_PRE_TIME_PRE_RATIO_SHIFT (16U) 68 #define BACC_PRE_TIME_PRE_RATIO_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_RATIO_SHIFT) & BACC_PRE_TIME_PRE_RATIO_MASK) 69 #define BACC_PRE_TIME_PRE_RATIO_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_RATIO_MASK) >> BACC_PRE_TIME_PRE_RATIO_SHIFT) 70 71 /* 72 * PRE_OFFSET (RW) 73 * 74 * guard band before rising edge 75 * this value will be added to ratio number 76 */ 77 #define BACC_PRE_TIME_PRE_OFFSET_MASK (0xFFFFU) 78 #define BACC_PRE_TIME_PRE_OFFSET_SHIFT (0U) 79 #define BACC_PRE_TIME_PRE_OFFSET_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_OFFSET_SHIFT) & BACC_PRE_TIME_PRE_OFFSET_MASK) 80 #define BACC_PRE_TIME_PRE_OFFSET_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_OFFSET_MASK) >> BACC_PRE_TIME_PRE_OFFSET_SHIFT) 81 82 /* Bitfield definition for register: POST_TIME */ 83 /* 84 * POST_RATIO (RW) 85 * 86 * Ratio of guard band after rising edge 87 * 0: 0 88 * 1: 1/32768 of high level width 89 * 2: 1/16384 of high level width 90 * 14: 1/4 of high level width 91 * 15: 1/2 of high level width 92 */ 93 #define BACC_POST_TIME_POST_RATIO_MASK (0xF0000UL) 94 #define BACC_POST_TIME_POST_RATIO_SHIFT (16U) 95 #define BACC_POST_TIME_POST_RATIO_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_RATIO_SHIFT) & BACC_POST_TIME_POST_RATIO_MASK) 96 #define BACC_POST_TIME_POST_RATIO_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_RATIO_MASK) >> BACC_POST_TIME_POST_RATIO_SHIFT) 97 98 /* 99 * POST_OFFSET (RW) 100 * 101 * guard band after rising edge 102 * this value will be added to ratio number 103 */ 104 #define BACC_POST_TIME_POST_OFFSET_MASK (0xFFFFU) 105 #define BACC_POST_TIME_POST_OFFSET_SHIFT (0U) 106 #define BACC_POST_TIME_POST_OFFSET_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_OFFSET_SHIFT) & BACC_POST_TIME_POST_OFFSET_MASK) 107 #define BACC_POST_TIME_POST_OFFSET_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_OFFSET_MASK) >> BACC_POST_TIME_POST_OFFSET_SHIFT) 108 109 110 111 112 #endif /* HPM_BACC_H */ 113