1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PWM_H 10 #define HPM_PWM_H 11 12 typedef struct { 13 __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ 14 union { 15 __RW uint32_t STA; /* 0x4: Counter start register */ 16 }; 17 union { 18 __RW uint32_t RLD; /* 0x8: Counter reload register */ 19 }; 20 union { 21 __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ 22 }; 23 __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ 24 __RW uint32_t FRCMD; /* 0x78: Force output mode register */ 25 __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ 26 __RW uint32_t CHCFG[24]; /* 0x80 - 0xDC: Output channel configure register */ 27 __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */ 28 __RW uint32_t GCR; /* 0xF0: Global control register */ 29 __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ 30 __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ 31 __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */ 32 __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */ 33 __R uint32_t CNT; /* 0x170: Counter */ 34 __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ 35 __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */ 36 __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */ 37 __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ 38 __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ 39 __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ 40 __W uint32_t SR; /* 0x220: Status register */ 41 __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ 42 __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ 43 __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ 44 __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ 45 } PWM_Type; 46 47 48 /* Bitfield definition for register: UNLK */ 49 /* 50 * SHUNLK (RW) 51 * 52 * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, 53 * otherwise the shadow registers can not be written. 54 */ 55 #define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) 56 #define PWM_UNLK_SHUNLK_SHIFT (0U) 57 #define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) 58 #define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) 59 60 /* Bitfield definition for register: STA */ 61 /* 62 * XSTA (RW) 63 * 64 * pwm timer counter extended start point, should back to this value after reach xrld 65 */ 66 #define PWM_STA_XSTA_MASK (0xF0000000UL) 67 #define PWM_STA_XSTA_SHIFT (28U) 68 #define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) 69 #define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) 70 71 /* 72 * STA (RW) 73 * 74 * pwm timer counter start value 75 * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk 76 */ 77 #define PWM_STA_STA_MASK (0xFFFFFF0UL) 78 #define PWM_STA_STA_SHIFT (4U) 79 #define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) 80 #define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) 81 82 /* Bitfield definition for register: RLD */ 83 /* 84 * XRLD (RW) 85 * 86 * timeout counter extended reload point, counter will reload to xsta after reach this point 87 */ 88 #define PWM_RLD_XRLD_MASK (0xF0000000UL) 89 #define PWM_RLD_XRLD_SHIFT (28U) 90 #define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) 91 #define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) 92 93 /* 94 * RLD (RW) 95 * 96 * pwm timer counter reload value 97 */ 98 #define PWM_RLD_RLD_MASK (0xFFFFFF0UL) 99 #define PWM_RLD_RLD_SHIFT (4U) 100 #define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) 101 #define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) 102 103 /* Bitfield definition for register: 0 */ 104 /* 105 * XCMP (RW) 106 * 107 * extended counter compare value 108 */ 109 #define PWM_CMP_XCMP_MASK (0xF0000000UL) 110 #define PWM_CMP_XCMP_SHIFT (28U) 111 #define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) 112 #define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) 113 114 /* 115 * CMP (RW) 116 * 117 * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, 118 * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. 119 */ 120 #define PWM_CMP_CMP_MASK (0xFFFFFF0UL) 121 #define PWM_CMP_CMP_SHIFT (4U) 122 #define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) 123 #define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) 124 125 /* 126 * CMPHLF (RW) 127 * 128 * half clock counter compare value 129 */ 130 #define PWM_CMP_CMPHLF_MASK (0x8U) 131 #define PWM_CMP_CMPHLF_SHIFT (3U) 132 #define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) 133 #define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) 134 135 /* 136 * CMPJIT (RW) 137 * 138 * jitter counter compare value 139 */ 140 #define PWM_CMP_CMPJIT_MASK (0x7U) 141 #define PWM_CMP_CMPJIT_SHIFT (0U) 142 #define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) 143 #define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) 144 145 /* Bitfield definition for register: FRCMD */ 146 /* 147 * FRCMD (RW) 148 * 149 * 2bit for each PWM output channel (0-7); 150 * 00: force output 0 151 * 01: force output 1 152 * 10: output highz 153 * 11: no force 154 */ 155 #define PWM_FRCMD_FRCMD_MASK (0xFFFFU) 156 #define PWM_FRCMD_FRCMD_SHIFT (0U) 157 #define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) 158 #define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) 159 160 /* Bitfield definition for register: SHLK */ 161 /* 162 * SHLK (RW) 163 * 164 * write 1 to lock all shawdow register, write access is not permitted 165 */ 166 #define PWM_SHLK_SHLK_MASK (0x80000000UL) 167 #define PWM_SHLK_SHLK_SHIFT (31U) 168 #define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) 169 #define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) 170 171 /* Bitfield definition for register array: CHCFG */ 172 /* 173 * CMPSELEND (RW) 174 * 175 * assign the last comparator for this output channel 176 */ 177 #define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) 178 #define PWM_CHCFG_CMPSELEND_SHIFT (24U) 179 #define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) 180 #define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) 181 182 /* 183 * CMPSELBEG (RW) 184 * 185 * assign the first comparator for this output channel 186 */ 187 #define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) 188 #define PWM_CHCFG_CMPSELBEG_SHIFT (16U) 189 #define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) 190 #define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) 191 192 /* 193 * OUTPOL (RW) 194 * 195 * output polarity, set to 1 will invert the output 196 */ 197 #define PWM_CHCFG_OUTPOL_MASK (0x2U) 198 #define PWM_CHCFG_OUTPOL_SHIFT (1U) 199 #define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) 200 #define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) 201 202 /* Bitfield definition for register: GCR */ 203 /* 204 * FAULTI3EN (RW) 205 * 206 * 1- enable the internal fault input 3 207 */ 208 #define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) 209 #define PWM_GCR_FAULTI3EN_SHIFT (31U) 210 #define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) 211 #define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) 212 213 /* 214 * FAULTI2EN (RW) 215 * 216 * 1- enable the internal fault input 2 217 */ 218 #define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) 219 #define PWM_GCR_FAULTI2EN_SHIFT (30U) 220 #define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) 221 #define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) 222 223 /* 224 * FAULTI1EN (RW) 225 * 226 * 1- enable the internal fault input 1 227 */ 228 #define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) 229 #define PWM_GCR_FAULTI1EN_SHIFT (29U) 230 #define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) 231 #define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) 232 233 /* 234 * FAULTI0EN (RW) 235 * 236 * 1- enable the internal fault input 0 237 */ 238 #define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) 239 #define PWM_GCR_FAULTI0EN_SHIFT (28U) 240 #define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) 241 #define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) 242 243 /* 244 * DEBUGFAULT (RW) 245 * 246 * 1- enable debug mode output protection 247 */ 248 #define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) 249 #define PWM_GCR_DEBUGFAULT_SHIFT (27U) 250 #define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) 251 #define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) 252 253 /* 254 * FRCPOL (RW) 255 * 256 * polarity of input pwm_force, 257 * 1- active low 258 * 0- active high 259 */ 260 #define PWM_GCR_FRCPOL_MASK (0x4000000UL) 261 #define PWM_GCR_FRCPOL_SHIFT (26U) 262 #define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) 263 #define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) 264 265 /* 266 * HWSHDWEDG (RW) 267 * 268 * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. 269 * This bit assign its which edge is used as compare shadow register hardware load event. 270 * 1- Falling edge 271 * 0- Rising edge 272 */ 273 #define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) 274 #define PWM_GCR_HWSHDWEDG_SHIFT (24U) 275 #define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) 276 #define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) 277 278 /* 279 * CMPSHDWSEL (RW) 280 * 281 * This bitfield select one of the comparators as hardware event time to load comparator shadow registers 282 */ 283 #define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) 284 #define PWM_GCR_CMPSHDWSEL_SHIFT (19U) 285 #define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) 286 #define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) 287 288 /* 289 * FAULTRECEDG (RW) 290 * 291 * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. 292 * This bit assign its effective edge of fault recover trigger. 293 * 1- Falling edge 294 * 0- Rising edge 295 */ 296 #define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) 297 #define PWM_GCR_FAULTRECEDG_SHIFT (18U) 298 #define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) 299 #define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) 300 301 /* 302 * FAULTRECHWSEL (RW) 303 * 304 * Selec one of the 24 comparators as fault output recover trigger. 305 */ 306 #define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) 307 #define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) 308 #define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) 309 #define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) 310 311 /* 312 * FAULTE1EN (RW) 313 * 314 * 1- enable the external fault input 1 315 */ 316 #define PWM_GCR_FAULTE1EN_MASK (0x1000U) 317 #define PWM_GCR_FAULTE1EN_SHIFT (12U) 318 #define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) 319 #define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) 320 321 /* 322 * FAULTE0EN (RW) 323 * 324 * 1- enable the external fault input 0 325 */ 326 #define PWM_GCR_FAULTE0EN_MASK (0x800U) 327 #define PWM_GCR_FAULTE0EN_SHIFT (11U) 328 #define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) 329 #define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) 330 331 /* 332 * FAULTEXPOL (RW) 333 * 334 * external fault polarity 335 * 1-active low 336 * 0-active high 337 */ 338 #define PWM_GCR_FAULTEXPOL_MASK (0x600U) 339 #define PWM_GCR_FAULTEXPOL_SHIFT (9U) 340 #define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) 341 #define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) 342 343 /* 344 * RLDSYNCEN (RW) 345 * 346 * 1- pwm timer counter reset to reload value (rld) by synci is enabled 347 */ 348 #define PWM_GCR_RLDSYNCEN_MASK (0x100U) 349 #define PWM_GCR_RLDSYNCEN_SHIFT (8U) 350 #define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) 351 #define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) 352 353 /* 354 * CEN (RW) 355 * 356 * 1- enable the pwm timer counter 357 * 0- stop the pwm timer counter 358 */ 359 #define PWM_GCR_CEN_MASK (0x80U) 360 #define PWM_GCR_CEN_SHIFT (7U) 361 #define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) 362 #define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) 363 364 /* 365 * FAULTCLR (RW) 366 * 367 * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. 368 * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. 369 */ 370 #define PWM_GCR_FAULTCLR_MASK (0x40U) 371 #define PWM_GCR_FAULTCLR_SHIFT (6U) 372 #define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) 373 #define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) 374 375 /* 376 * XRLDSYNCEN (RW) 377 * 378 * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled 379 */ 380 #define PWM_GCR_XRLDSYNCEN_MASK (0x20U) 381 #define PWM_GCR_XRLDSYNCEN_SHIFT (5U) 382 #define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) 383 #define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) 384 385 /* 386 * TIMERRESET (RW) 387 * 388 * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear 389 */ 390 #define PWM_GCR_TIMERRESET_MASK (0x8U) 391 #define PWM_GCR_TIMERRESET_SHIFT (3U) 392 #define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) 393 #define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) 394 395 /* 396 * FRCTIME (WO) 397 * 398 * This bit field select the force effective time 399 * 00: force immediately 400 * 01: force at main counter reload time 401 * 10: force at FRCSYNCI 402 * 11: no force 403 */ 404 #define PWM_GCR_FRCTIME_MASK (0x6U) 405 #define PWM_GCR_FRCTIME_SHIFT (1U) 406 #define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) 407 #define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) 408 409 /* 410 * SWFRC (RW) 411 * 412 * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect 413 */ 414 #define PWM_GCR_SWFRC_MASK (0x1U) 415 #define PWM_GCR_SWFRC_SHIFT (0U) 416 #define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) 417 #define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) 418 419 /* Bitfield definition for register: SHCR */ 420 /* 421 * FRCSHDWSEL (RW) 422 * 423 * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers 424 */ 425 #define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) 426 #define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) 427 #define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) 428 #define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) 429 430 /* 431 * CNTSHDWSEL (RW) 432 * 433 * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) 434 */ 435 #define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) 436 #define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) 437 #define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) 438 #define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) 439 440 /* 441 * CNTSHDWUPT (RW) 442 * 443 * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 444 * 00: after software set shlk bit of shlk register 445 * 01: immediately after the register being modified 446 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 447 * The comparator can be either output compare mode or input capture mode. 448 * 11: after SHSYNCI assert 449 */ 450 #define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) 451 #define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) 452 #define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) 453 #define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) 454 455 /* 456 * SHLKEN (RW) 457 * 458 * 1- enable shadow registers lock feature, 459 * 0- disable shadow registers lock, shlk bit will always be 0 460 */ 461 #define PWM_SHCR_SHLKEN_MASK (0x1U) 462 #define PWM_SHCR_SHLKEN_SHIFT (0U) 463 #define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) 464 #define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) 465 466 /* Bitfield definition for register array: CAPPOS */ 467 /* 468 * CAPPOS (RO) 469 * 470 * counter value captured at input posedge 471 */ 472 #define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) 473 #define PWM_CAPPOS_CAPPOS_SHIFT (4U) 474 #define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) 475 476 /* Bitfield definition for register: CNT */ 477 /* 478 * XCNT (RO) 479 * 480 * current extended counter value 481 */ 482 #define PWM_CNT_XCNT_MASK (0xF0000000UL) 483 #define PWM_CNT_XCNT_SHIFT (28U) 484 #define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) 485 486 /* 487 * CNT (RO) 488 * 489 * current clock counter value 490 */ 491 #define PWM_CNT_CNT_MASK (0xFFFFFF0UL) 492 #define PWM_CNT_CNT_SHIFT (4U) 493 #define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) 494 495 /* Bitfield definition for register array: CAPNEG */ 496 /* 497 * CAPNEG (RO) 498 * 499 * counter value captured at input signal falling edge 500 */ 501 #define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) 502 #define PWM_CAPNEG_CAPNEG_SHIFT (0U) 503 #define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) 504 505 /* Bitfield definition for register: CNTCOPY */ 506 /* 507 * XCNT (RO) 508 * 509 * current extended counter value 510 */ 511 #define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) 512 #define PWM_CNTCOPY_XCNT_SHIFT (28U) 513 #define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) 514 515 /* 516 * CNT (RO) 517 * 518 * current clock counter value 519 */ 520 #define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) 521 #define PWM_CNTCOPY_CNT_SHIFT (4U) 522 #define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) 523 524 /* Bitfield definition for register array: PWMCFG */ 525 /* 526 * OEN (RW) 527 * 528 * PWM output enable 529 * 1- output is enabled 530 * 0- output is disabled 531 */ 532 #define PWM_PWMCFG_OEN_MASK (0x10000000UL) 533 #define PWM_PWMCFG_OEN_SHIFT (28U) 534 #define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) 535 #define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) 536 537 /* 538 * FRCSHDWUPT (RW) 539 * 540 * This bitfield select when the FRCMD shadow register will be loaded to its work register 541 * 00: after software set shlk bit of shlk register 542 * 01: immediately after the register being modified 543 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 544 * The comparator can be either output compare mode or input capture mode. 545 * 11: after SHSYNCI assert 546 */ 547 #define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) 548 #define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) 549 #define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) 550 #define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) 551 552 /* 553 * FAULTMODE (RW) 554 * 555 * This bitfield defines the PWM output status when fault condition happen 556 * 00: force output 0 557 * 01: force output 1 558 * 1x: output highz 559 */ 560 #define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) 561 #define PWM_PWMCFG_FAULTMODE_SHIFT (24U) 562 #define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) 563 #define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) 564 565 /* 566 * FAULTRECTIME (RW) 567 * 568 * This bitfield select when to recover PWM output after fault condition removed. 569 * 00: immediately 570 * 01: after pwm timer counter reload time 571 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 572 * The comparator can be either output compare mode or input capture mode. 573 * 11: after software write faultclr bit in GCR register 574 */ 575 #define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) 576 #define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) 577 #define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) 578 #define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) 579 580 /* 581 * FRCSRCSEL (RW) 582 * 583 * Select sources for force output 584 * 0- force output is enabled when FRCI assert 585 * 1- force output is enabled by software write swfrc to 1 586 */ 587 #define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) 588 #define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) 589 #define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) 590 #define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) 591 592 /* 593 * PAIR (RW) 594 * 595 * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 596 * 0- PWM output is in indepandent mode. 597 */ 598 #define PWM_PWMCFG_PAIR_MASK (0x100000UL) 599 #define PWM_PWMCFG_PAIR_SHIFT (20U) 600 #define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) 601 #define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) 602 603 /* 604 * DEADAREA (RW) 605 * 606 * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. 607 * Note: user should configure pair bit and this bitfield before PWM output is enabled. 608 */ 609 #define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) 610 #define PWM_PWMCFG_DEADAREA_SHIFT (0U) 611 #define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) 612 #define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) 613 614 /* Bitfield definition for register: SR */ 615 /* 616 * FAULTF (W1C) 617 * 618 * fault condition flag 619 */ 620 #define PWM_SR_FAULTF_MASK (0x8000000UL) 621 #define PWM_SR_FAULTF_SHIFT (27U) 622 #define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) 623 #define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) 624 625 /* 626 * XRLDF (W1C) 627 * 628 * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert 629 */ 630 #define PWM_SR_XRLDF_MASK (0x4000000UL) 631 #define PWM_SR_XRLDF_SHIFT (26U) 632 #define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) 633 #define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) 634 635 /* 636 * HALFRLDF (W1C) 637 * 638 * half reload flag, this flag set when cnt count to rld/2 639 */ 640 #define PWM_SR_HALFRLDF_MASK (0x2000000UL) 641 #define PWM_SR_HALFRLDF_SHIFT (25U) 642 #define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) 643 #define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) 644 645 /* 646 * RLDF (W1C) 647 * 648 * reload flag, this flag set when cnt count to rld value or when SYNCI assert 649 */ 650 #define PWM_SR_RLDF_MASK (0x1000000UL) 651 #define PWM_SR_RLDF_SHIFT (24U) 652 #define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) 653 #define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) 654 655 /* 656 * CMPFX (W1C) 657 * 658 * comparator output compare or input capture flag 659 */ 660 #define PWM_SR_CMPFX_MASK (0xFFFFFFUL) 661 #define PWM_SR_CMPFX_SHIFT (0U) 662 #define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) 663 #define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) 664 665 /* Bitfield definition for register: IRQEN */ 666 /* 667 * FAULTIRQE (RW) 668 * 669 * fault condition interrupt enable 670 */ 671 #define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) 672 #define PWM_IRQEN_FAULTIRQE_SHIFT (27U) 673 #define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) 674 #define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) 675 676 /* 677 * XRLDIRQE (RW) 678 * 679 * extended reload flag interrupt enable 680 */ 681 #define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) 682 #define PWM_IRQEN_XRLDIRQE_SHIFT (26U) 683 #define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) 684 #define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) 685 686 /* 687 * HALFRLDIRQE (RW) 688 * 689 * half reload flag interrupt enable 690 */ 691 #define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) 692 #define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) 693 #define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) 694 #define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) 695 696 /* 697 * RLDIRQE (RW) 698 * 699 * reload flag interrupt enable 700 */ 701 #define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) 702 #define PWM_IRQEN_RLDIRQE_SHIFT (24U) 703 #define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) 704 #define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) 705 706 /* 707 * CMPIRQEX (RW) 708 * 709 * comparator output compare or input capture flag interrupt enable 710 */ 711 #define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) 712 #define PWM_IRQEN_CMPIRQEX_SHIFT (0U) 713 #define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) 714 #define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) 715 716 /* Bitfield definition for register: DMAEN */ 717 /* 718 * FAULTEN (RW) 719 * 720 * fault condition DMA request enable 721 */ 722 #define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) 723 #define PWM_DMAEN_FAULTEN_SHIFT (27U) 724 #define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) 725 #define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) 726 727 /* 728 * XRLDEN (RW) 729 * 730 * extended reload flag DMA request enable 731 */ 732 #define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) 733 #define PWM_DMAEN_XRLDEN_SHIFT (26U) 734 #define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) 735 #define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) 736 737 /* 738 * HALFRLDEN (RW) 739 * 740 * half reload flag DMA request enable 741 */ 742 #define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) 743 #define PWM_DMAEN_HALFRLDEN_SHIFT (25U) 744 #define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) 745 #define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) 746 747 /* 748 * RLDEN (RW) 749 * 750 * reload flag DMA request enable 751 */ 752 #define PWM_DMAEN_RLDEN_MASK (0x1000000UL) 753 #define PWM_DMAEN_RLDEN_SHIFT (24U) 754 #define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) 755 #define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) 756 757 /* 758 * CMPENX (RW) 759 * 760 * comparator output compare or input capture flag DMA request enable 761 */ 762 #define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) 763 #define PWM_DMAEN_CMPENX_SHIFT (0U) 764 #define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) 765 #define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) 766 767 /* Bitfield definition for register array: CMPCFG */ 768 /* 769 * XCNTCMPEN (RW) 770 * 771 * This bitfield enable the comparator to compare xcmp with xcnt. 772 */ 773 #define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) 774 #define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) 775 #define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) 776 #define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) 777 778 /* 779 * CMPSHDWUPT (RW) 780 * 781 * This bitfield select when the comparator shadow register will be loaded to its work register 782 * 00: after software set shlk bit of shlk register 783 * 01: immediately after the register being modified 784 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 785 * The comparator can be either output compare mode or input capture mode. 786 * 11: after SHSYNCI assert 787 */ 788 #define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) 789 #define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) 790 #define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) 791 #define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) 792 793 /* 794 * CMPMODE (RW) 795 * 796 * comparator mode 797 * 0- output compare mode 798 * 1- input capture mode 799 */ 800 #define PWM_CMPCFG_CMPMODE_MASK (0x2U) 801 #define PWM_CMPCFG_CMPMODE_SHIFT (1U) 802 #define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) 803 #define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) 804 805 806 807 /* CMP register group index macro definition */ 808 #define PWM_CMP_0 (0UL) 809 #define PWM_CMP_1 (1UL) 810 #define PWM_CMP_2 (2UL) 811 #define PWM_CMP_3 (3UL) 812 #define PWM_CMP_4 (4UL) 813 #define PWM_CMP_5 (5UL) 814 #define PWM_CMP_6 (6UL) 815 #define PWM_CMP_7 (7UL) 816 #define PWM_CMP_8 (8UL) 817 #define PWM_CMP_9 (9UL) 818 #define PWM_CMP_10 (10UL) 819 #define PWM_CMP_11 (11UL) 820 #define PWM_CMP_12 (12UL) 821 #define PWM_CMP_13 (13UL) 822 #define PWM_CMP_14 (14UL) 823 #define PWM_CMP_15 (15UL) 824 #define PWM_CMP_16 (16UL) 825 #define PWM_CMP_17 (17UL) 826 #define PWM_CMP_18 (18UL) 827 #define PWM_CMP_19 (19UL) 828 #define PWM_CMP_20 (20UL) 829 #define PWM_CMP_21 (21UL) 830 #define PWM_CMP_22 (22UL) 831 #define PWM_CMP_23 (23UL) 832 833 /* CHCFG register group index macro definition */ 834 #define PWM_CHCFG_0 (0UL) 835 #define PWM_CHCFG_1 (1UL) 836 #define PWM_CHCFG_2 (2UL) 837 #define PWM_CHCFG_3 (3UL) 838 #define PWM_CHCFG_4 (4UL) 839 #define PWM_CHCFG_5 (5UL) 840 #define PWM_CHCFG_6 (6UL) 841 #define PWM_CHCFG_7 (7UL) 842 #define PWM_CHCFG_8 (8UL) 843 #define PWM_CHCFG_9 (9UL) 844 #define PWM_CHCFG_10 (10UL) 845 #define PWM_CHCFG_11 (11UL) 846 #define PWM_CHCFG_12 (12UL) 847 #define PWM_CHCFG_13 (13UL) 848 #define PWM_CHCFG_14 (14UL) 849 #define PWM_CHCFG_15 (15UL) 850 #define PWM_CHCFG_16 (16UL) 851 #define PWM_CHCFG_17 (17UL) 852 #define PWM_CHCFG_18 (18UL) 853 #define PWM_CHCFG_19 (19UL) 854 #define PWM_CHCFG_20 (20UL) 855 #define PWM_CHCFG_21 (21UL) 856 #define PWM_CHCFG_22 (22UL) 857 #define PWM_CHCFG_23 (23UL) 858 859 /* CAPPOS register group index macro definition */ 860 #define PWM_CAPPOS_0 (0UL) 861 #define PWM_CAPPOS_1 (1UL) 862 #define PWM_CAPPOS_2 (2UL) 863 #define PWM_CAPPOS_3 (3UL) 864 #define PWM_CAPPOS_4 (4UL) 865 #define PWM_CAPPOS_5 (5UL) 866 #define PWM_CAPPOS_6 (6UL) 867 #define PWM_CAPPOS_7 (7UL) 868 #define PWM_CAPPOS_8 (8UL) 869 #define PWM_CAPPOS_9 (9UL) 870 #define PWM_CAPPOS_10 (10UL) 871 #define PWM_CAPPOS_11 (11UL) 872 #define PWM_CAPPOS_12 (12UL) 873 #define PWM_CAPPOS_13 (13UL) 874 #define PWM_CAPPOS_14 (14UL) 875 #define PWM_CAPPOS_15 (15UL) 876 #define PWM_CAPPOS_16 (16UL) 877 #define PWM_CAPPOS_17 (17UL) 878 #define PWM_CAPPOS_18 (18UL) 879 #define PWM_CAPPOS_19 (19UL) 880 #define PWM_CAPPOS_20 (20UL) 881 #define PWM_CAPPOS_21 (21UL) 882 #define PWM_CAPPOS_22 (22UL) 883 #define PWM_CAPPOS_23 (23UL) 884 885 /* CAPNEG register group index macro definition */ 886 #define PWM_CAPNEG_0 (0UL) 887 #define PWM_CAPNEG_1 (1UL) 888 #define PWM_CAPNEG_2 (2UL) 889 #define PWM_CAPNEG_3 (3UL) 890 #define PWM_CAPNEG_4 (4UL) 891 #define PWM_CAPNEG_5 (5UL) 892 #define PWM_CAPNEG_6 (6UL) 893 #define PWM_CAPNEG_7 (7UL) 894 #define PWM_CAPNEG_8 (8UL) 895 #define PWM_CAPNEG_9 (9UL) 896 #define PWM_CAPNEG_10 (10UL) 897 #define PWM_CAPNEG_11 (11UL) 898 #define PWM_CAPNEG_12 (12UL) 899 #define PWM_CAPNEG_13 (13UL) 900 #define PWM_CAPNEG_14 (14UL) 901 #define PWM_CAPNEG_15 (15UL) 902 #define PWM_CAPNEG_16 (16UL) 903 #define PWM_CAPNEG_17 (17UL) 904 #define PWM_CAPNEG_18 (18UL) 905 #define PWM_CAPNEG_19 (19UL) 906 #define PWM_CAPNEG_20 (20UL) 907 #define PWM_CAPNEG_21 (21UL) 908 #define PWM_CAPNEG_22 (22UL) 909 #define PWM_CAPNEG_23 (23UL) 910 911 /* PWMCFG register group index macro definition */ 912 #define PWM_PWMCFG_0 (0UL) 913 #define PWM_PWMCFG_1 (1UL) 914 #define PWM_PWMCFG_2 (2UL) 915 #define PWM_PWMCFG_3 (3UL) 916 #define PWM_PWMCFG_4 (4UL) 917 #define PWM_PWMCFG_5 (5UL) 918 #define PWM_PWMCFG_6 (6UL) 919 #define PWM_PWMCFG_7 (7UL) 920 921 /* CMPCFG register group index macro definition */ 922 #define PWM_CMPCFG_CMPCFG0 (0UL) 923 #define PWM_CMPCFG_1 (1UL) 924 #define PWM_CMPCFG_2 (2UL) 925 #define PWM_CMPCFG_3 (3UL) 926 #define PWM_CMPCFG_4 (4UL) 927 #define PWM_CMPCFG_5 (5UL) 928 #define PWM_CMPCFG_6 (6UL) 929 #define PWM_CMPCFG_7 (7UL) 930 #define PWM_CMPCFG_8 (8UL) 931 #define PWM_CMPCFG_9 (9UL) 932 #define PWM_CMPCFG_10 (10UL) 933 #define PWM_CMPCFG_11 (11UL) 934 #define PWM_CMPCFG_12 (12UL) 935 #define PWM_CMPCFG_13 (13UL) 936 #define PWM_CMPCFG_14 (14UL) 937 #define PWM_CMPCFG_15 (15UL) 938 #define PWM_CMPCFG_16 (16UL) 939 #define PWM_CMPCFG_17 (17UL) 940 #define PWM_CMPCFG_18 (18UL) 941 #define PWM_CMPCFG_19 (19UL) 942 #define PWM_CMPCFG_20 (20UL) 943 #define PWM_CMPCFG_21 (21UL) 944 #define PWM_CMPCFG_22 (22UL) 945 #define PWM_CMPCFG_23 (23UL) 946 947 948 #endif /* HPM_PWM_H */ 949