1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_TRGMMUX_SRC_H 10 #define HPM_TRGMMUX_SRC_H 11 12 /* trgm0_input mux definitions */ 13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) 14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) 15 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) 16 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) 17 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) 18 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) 19 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) 20 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) 21 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) 22 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) 23 #define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) 24 #define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) 25 #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) 26 #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) 27 #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) 28 #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) 29 #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) 30 #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) 31 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) 32 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) 33 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) 34 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) 35 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) 36 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) 37 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) 38 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) 39 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) 40 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) 41 #define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) 42 #define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) 43 #define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) 44 #define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) 45 #define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) 46 #define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) 47 #define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) 48 #define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) 49 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) 50 #define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) 51 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) 52 #define HPM_TRGM0_INPUT_SRC_USB1_SOF (0x27UL) 53 #define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) 54 #define HPM_TRGM0_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) 55 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) 56 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) 57 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) 58 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) 59 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) 60 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) 61 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) 62 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) 63 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) 64 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) 65 #define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) 66 #define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) 67 #define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) 68 #define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) 69 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) 70 71 /* trgm1_input mux definitions */ 72 #define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) 73 #define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) 74 #define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) 75 #define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) 76 #define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) 77 #define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) 78 #define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) 79 #define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) 80 #define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) 81 #define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) 82 #define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) 83 #define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) 84 #define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) 85 #define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) 86 #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) 87 #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) 88 #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) 89 #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) 90 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) 91 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) 92 #define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) 93 #define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) 94 #define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) 95 #define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) 96 #define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) 97 #define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) 98 #define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) 99 #define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) 100 #define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) 101 #define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) 102 #define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) 103 #define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) 104 #define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) 105 #define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) 106 #define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) 107 #define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) 108 #define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) 109 #define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) 110 #define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) 111 #define HPM_TRGM1_INPUT_SRC_USB1_SOF (0x27UL) 112 #define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) 113 #define HPM_TRGM1_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) 114 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) 115 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) 116 #define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x2CUL) 117 #define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x2DUL) 118 #define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x2EUL) 119 #define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x2FUL) 120 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) 121 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) 122 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) 123 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) 124 #define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) 125 #define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) 126 #define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) 127 #define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) 128 #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) 129 130 /* trgm2_input mux definitions */ 131 #define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) 132 #define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) 133 #define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) 134 #define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) 135 #define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) 136 #define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) 137 #define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) 138 #define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) 139 #define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) 140 #define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) 141 #define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) 142 #define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) 143 #define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) 144 #define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) 145 #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) 146 #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) 147 #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) 148 #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) 149 #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) 150 #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) 151 #define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) 152 #define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) 153 #define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) 154 #define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) 155 #define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) 156 #define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) 157 #define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) 158 #define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) 159 #define HPM_TRGM2_INPUT_SRC_PWM2_CH16REF (0x1CUL) 160 #define HPM_TRGM2_INPUT_SRC_PWM2_CH17REF (0x1DUL) 161 #define HPM_TRGM2_INPUT_SRC_PWM2_CH18REF (0x1EUL) 162 #define HPM_TRGM2_INPUT_SRC_PWM2_CH19REF (0x1FUL) 163 #define HPM_TRGM2_INPUT_SRC_PWM2_CH20REF (0x20UL) 164 #define HPM_TRGM2_INPUT_SRC_PWM2_CH21REF (0x21UL) 165 #define HPM_TRGM2_INPUT_SRC_PWM2_CH22REF (0x22UL) 166 #define HPM_TRGM2_INPUT_SRC_PWM2_CH23REF (0x23UL) 167 #define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x24UL) 168 #define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x25UL) 169 #define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x26UL) 170 #define HPM_TRGM2_INPUT_SRC_USB1_SOF (0x27UL) 171 #define HPM_TRGM2_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) 172 #define HPM_TRGM2_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) 173 #define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x2AUL) 174 #define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x2BUL) 175 #define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x2CUL) 176 #define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x2DUL) 177 #define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x2EUL) 178 #define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x2FUL) 179 #define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT2 (0x30UL) 180 #define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT3 (0x31UL) 181 #define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2 (0x32UL) 182 #define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3 (0x33UL) 183 #define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) 184 #define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) 185 #define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) 186 #define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) 187 #define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x38UL) 188 189 /* trgm3_input mux definitions */ 190 #define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) 191 #define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) 192 #define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) 193 #define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) 194 #define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) 195 #define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) 196 #define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) 197 #define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) 198 #define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) 199 #define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) 200 #define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) 201 #define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) 202 #define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) 203 #define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) 204 #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) 205 #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) 206 #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) 207 #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) 208 #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) 209 #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) 210 #define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) 211 #define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) 212 #define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) 213 #define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) 214 #define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) 215 #define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) 216 #define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) 217 #define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) 218 #define HPM_TRGM3_INPUT_SRC_PWM3_CH16REF (0x1CUL) 219 #define HPM_TRGM3_INPUT_SRC_PWM3_CH17REF (0x1DUL) 220 #define HPM_TRGM3_INPUT_SRC_PWM3_CH18REF (0x1EUL) 221 #define HPM_TRGM3_INPUT_SRC_PWM3_CH19REF (0x1FUL) 222 #define HPM_TRGM3_INPUT_SRC_PWM3_CH20REF (0x20UL) 223 #define HPM_TRGM3_INPUT_SRC_PWM3_CH21REF (0x21UL) 224 #define HPM_TRGM3_INPUT_SRC_PWM3_CH22REF (0x22UL) 225 #define HPM_TRGM3_INPUT_SRC_PWM3_CH23REF (0x23UL) 226 #define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x24UL) 227 #define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x25UL) 228 #define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x26UL) 229 #define HPM_TRGM3_INPUT_SRC_USB1_SOF (0x27UL) 230 #define HPM_TRGM3_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) 231 #define HPM_TRGM3_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) 232 #define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x2AUL) 233 #define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x2BUL) 234 #define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x2CUL) 235 #define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x2DUL) 236 #define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x2EUL) 237 #define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x2FUL) 238 #define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT2 (0x30UL) 239 #define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT3 (0x31UL) 240 #define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT2 (0x32UL) 241 #define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT3 (0x33UL) 242 #define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) 243 #define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) 244 #define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) 245 #define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) 246 #define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x38UL) 247 248 /* trgm0_output mux definitions */ 249 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) 250 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) 251 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) 252 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) 253 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) 254 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) 255 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) 256 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) 257 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) 258 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) 259 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) 260 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) 261 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) 262 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) 263 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) 264 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) 265 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) 266 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) 267 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) 268 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) 269 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) 270 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) 271 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) 272 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) 273 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) 274 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) 275 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) 276 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) 277 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) 278 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) 279 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) 280 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) 281 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) 282 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) 283 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) 284 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) 285 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) 286 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) 287 #define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) 288 #define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) 289 #define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) 290 #define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) 291 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) 292 #define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) 293 #define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) 294 #define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) 295 #define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) 296 #define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) 297 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) 298 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) 299 #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) 300 #define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI (0x33UL) 301 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) 302 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) 303 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) 304 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) 305 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) 306 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) 307 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) 308 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) 309 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) 310 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) 311 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) 312 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) 313 314 /* trgm1_output mux definitions */ 315 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) 316 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) 317 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) 318 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) 319 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) 320 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) 321 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) 322 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) 323 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) 324 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) 325 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) 326 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) 327 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) 328 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) 329 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) 330 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) 331 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) 332 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) 333 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) 334 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) 335 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) 336 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) 337 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) 338 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) 339 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) 340 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) 341 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) 342 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) 343 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) 344 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) 345 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) 346 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) 347 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) 348 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) 349 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) 350 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) 351 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) 352 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) 353 #define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) 354 #define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) 355 #define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) 356 #define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) 357 #define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) 358 #define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) 359 #define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) 360 #define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) 361 #define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) 362 #define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) 363 #define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) 364 #define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) 365 #define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) 366 #define HPM_TRGM1_OUTPUT_SRC_ADC3_STRGI (0x33UL) 367 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) 368 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) 369 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) 370 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) 371 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) 372 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) 373 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) 374 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) 375 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) 376 #define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) 377 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) 378 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) 379 380 /* trgm2_output mux definitions */ 381 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) 382 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) 383 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) 384 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) 385 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) 386 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) 387 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) 388 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) 389 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) 390 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) 391 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) 392 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) 393 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) 394 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) 395 #define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) 396 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) 397 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) 398 #define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) 399 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) 400 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) 401 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) 402 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) 403 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) 404 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) 405 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) 406 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) 407 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) 408 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) 409 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) 410 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) 411 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN16 (0x1EUL) 412 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN17 (0x1FUL) 413 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN18 (0x20UL) 414 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN19 (0x21UL) 415 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN20 (0x22UL) 416 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN21 (0x23UL) 417 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN22 (0x24UL) 418 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN23 (0x25UL) 419 #define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) 420 #define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) 421 #define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) 422 #define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) 423 #define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) 424 #define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) 425 #define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) 426 #define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) 427 #define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) 428 #define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) 429 #define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) 430 #define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) 431 #define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) 432 #define HPM_TRGM2_OUTPUT_SRC_ADC3_STRGI (0x33UL) 433 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) 434 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) 435 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) 436 #define HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI (0x37UL) 437 #define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 (0x38UL) 438 #define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN3 (0x39UL) 439 #define HPM_TRGM2_OUTPUT_SRC_GPTMR5_SYNCI (0x3AUL) 440 #define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN2 (0x3BUL) 441 #define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN3 (0x3CUL) 442 #define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) 443 #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) 444 #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) 445 446 /* trgm3_output mux definitions */ 447 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) 448 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) 449 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) 450 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) 451 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) 452 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) 453 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) 454 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) 455 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) 456 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) 457 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) 458 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) 459 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) 460 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) 461 #define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) 462 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) 463 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) 464 #define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) 465 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) 466 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) 467 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) 468 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) 469 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) 470 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) 471 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) 472 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) 473 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) 474 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) 475 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) 476 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) 477 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN16 (0x1EUL) 478 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN17 (0x1FUL) 479 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN18 (0x20UL) 480 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN19 (0x21UL) 481 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN20 (0x22UL) 482 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN21 (0x23UL) 483 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN22 (0x24UL) 484 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN23 (0x25UL) 485 #define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) 486 #define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) 487 #define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) 488 #define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) 489 #define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) 490 #define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) 491 #define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) 492 #define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) 493 #define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) 494 #define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) 495 #define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) 496 #define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) 497 #define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) 498 #define HPM_TRGM3_OUTPUT_SRC_ADC3_STRGI (0x33UL) 499 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) 500 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) 501 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) 502 #define HPM_TRGM3_OUTPUT_SRC_GPTMR6_SYNCI (0x37UL) 503 #define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN2 (0x38UL) 504 #define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN3 (0x39UL) 505 #define HPM_TRGM3_OUTPUT_SRC_GPTMR7_SYNCI (0x3AUL) 506 #define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN2 (0x3BUL) 507 #define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN3 (0x3CUL) 508 #define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) 509 #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) 510 #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) 511 512 /* trgm0_filter mux definitions */ 513 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) 514 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) 515 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) 516 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) 517 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) 518 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) 519 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) 520 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) 521 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) 522 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) 523 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) 524 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) 525 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) 526 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) 527 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) 528 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) 529 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) 530 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) 531 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) 532 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) 533 534 /* trgm1_filter mux definitions */ 535 #define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) 536 #define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) 537 #define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) 538 #define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) 539 #define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) 540 #define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) 541 #define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) 542 #define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) 543 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) 544 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) 545 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) 546 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) 547 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) 548 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) 549 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) 550 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) 551 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) 552 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) 553 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) 554 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) 555 556 /* trgm2_filter mux definitions */ 557 #define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) 558 #define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) 559 #define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) 560 #define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) 561 #define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) 562 #define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) 563 #define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) 564 #define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) 565 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) 566 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) 567 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) 568 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) 569 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) 570 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) 571 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) 572 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) 573 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) 574 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) 575 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) 576 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) 577 578 /* trgm3_filter mux definitions */ 579 #define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) 580 #define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) 581 #define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) 582 #define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) 583 #define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) 584 #define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) 585 #define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) 586 #define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) 587 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) 588 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) 589 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) 590 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) 591 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) 592 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) 593 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) 594 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) 595 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) 596 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) 597 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) 598 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) 599 600 /* trgm0_dma mux definitions */ 601 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) 602 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) 603 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) 604 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) 605 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) 606 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) 607 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) 608 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) 609 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) 610 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) 611 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) 612 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) 613 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) 614 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) 615 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) 616 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) 617 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) 618 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) 619 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) 620 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) 621 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) 622 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) 623 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) 624 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) 625 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) 626 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) 627 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) 628 #define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) 629 #define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) 630 631 /* trgm1_dma mux definitions */ 632 #define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) 633 #define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) 634 #define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) 635 #define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) 636 #define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) 637 #define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) 638 #define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) 639 #define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) 640 #define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) 641 #define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) 642 #define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) 643 #define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) 644 #define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) 645 #define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) 646 #define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) 647 #define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) 648 #define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) 649 #define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) 650 #define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) 651 #define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) 652 #define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) 653 #define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) 654 #define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) 655 #define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) 656 #define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) 657 #define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) 658 #define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) 659 #define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) 660 #define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) 661 662 /* trgm2_dma mux definitions */ 663 #define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) 664 #define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) 665 #define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) 666 #define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) 667 #define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) 668 #define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) 669 #define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) 670 #define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) 671 #define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) 672 #define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) 673 #define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) 674 #define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) 675 #define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) 676 #define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) 677 #define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) 678 #define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) 679 #define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) 680 #define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) 681 #define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) 682 #define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) 683 #define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) 684 #define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) 685 #define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) 686 #define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) 687 #define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) 688 #define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) 689 #define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) 690 #define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) 691 #define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) 692 693 /* trgm3_dma mux definitions */ 694 #define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) 695 #define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) 696 #define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) 697 #define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) 698 #define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) 699 #define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) 700 #define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) 701 #define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) 702 #define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) 703 #define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) 704 #define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) 705 #define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) 706 #define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) 707 #define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) 708 #define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) 709 #define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) 710 #define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) 711 #define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) 712 #define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) 713 #define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) 714 #define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) 715 #define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) 716 #define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) 717 #define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) 718 #define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) 719 #define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) 720 #define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) 721 #define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) 722 #define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) 723 724 725 726 #endif /* HPM_TRGMMUX_SRC_H */ 727