1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_BPOR_H
10 #define HPM_BPOR_H
11 
12 typedef struct {
13     __RW uint32_t POR_CAUSE;                   /* 0x0: Power on cause */
14     __RW uint32_t POR_SELECT;                  /* 0x4: Power on select */
15     __RW uint32_t POR_CONFIG;                  /* 0x8: Power on reset config */
16     __RW uint32_t POR_CONTROL;                 /* 0xC: Power down control */
17 } BPOR_Type;
18 
19 
20 /* Bitfield definition for register: POR_CAUSE */
21 /*
22  * CAUSE (RW)
23  *
24  * Power on cause, each bit represnts one cause, write 1 to clear each bit
25  * bit0: wakeup button
26  * bit1: security violation
27  * bit2: RTC alarm 0
28  * bit3: RTC alarm 1
29  * bit4: GPIO
30  */
31 #define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU)
32 #define BPOR_POR_CAUSE_CAUSE_SHIFT (0U)
33 #define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK)
34 #define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT)
35 
36 /* Bitfield definition for register: POR_SELECT */
37 /*
38  * SELECT (RW)
39  *
40  * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause
41  * bit0: wakeup button
42  * bit1: security violation
43  * bit2: RTC alarm 0
44  * bit3: RTC alarm 1
45  * bit4: GPIO
46  */
47 #define BPOR_POR_SELECT_SELECT_MASK (0x1FU)
48 #define BPOR_POR_SELECT_SELECT_SHIFT (0U)
49 #define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK)
50 #define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT)
51 
52 /* Bitfield definition for register: POR_CONFIG */
53 /*
54  * RETENTION (RW)
55  *
56  * retention battery domain setting
57  * 0: battery reset on reset pin reset happen
58  * 1: battery domain retention when reset pin reset happen
59  */
60 #define BPOR_POR_CONFIG_RETENTION_MASK (0x1U)
61 #define BPOR_POR_CONFIG_RETENTION_SHIFT (0U)
62 #define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK)
63 #define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT)
64 
65 /* Bitfield definition for register: POR_CONTROL */
66 /*
67  * COUNTER (RW)
68  *
69  * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1
70  */
71 #define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU)
72 #define BPOR_POR_CONTROL_COUNTER_SHIFT (0U)
73 #define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK)
74 #define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT)
75 
76 
77 
78 
79 #endif /* HPM_BPOR_H */
80