1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_GPIOM_H
10 #define HPM_GPIOM_H
11 
12 typedef struct {
13     struct {
14         __RW uint32_t PIN[32];                 /* 0x0 - 0x7C: GPIO mananger */
15     } ASSIGN[16];
16 } GPIOM_Type;
17 
18 
19 /* Bitfield definition for register of struct array ASSIGN: PIN00 */
20 /*
21  * LOCK (RW)
22  *
23  * lock fields in this register, lock can only be cleared by soc reset
24  * 0: fields can be changed
25  * 1: fields locked to current value, not changeable
26  */
27 #define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL)
28 #define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U)
29 #define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK)
30 #define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT)
31 
32 /*
33  * HIDE (RW)
34  *
35  * pin value visibility to gpios,
36  * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0
37  * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1
38  * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio
39  * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio
40  */
41 #define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U)
42 #define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U)
43 #define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK)
44 #define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT)
45 
46 /*
47  * SELECT (RW)
48  *
49  * select which gpio controls chip pin,
50  * 0: soc gpio0;
51  * 1: soc gpio1;
52  * 2: cpu0 fastgpio
53  * 3: cpu1 fast gpio
54  */
55 #define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U)
56 #define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U)
57 #define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK)
58 #define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT)
59 
60 
61 
62 /* PIN register group index macro definition */
63 #define GPIOM_ASSIGN_PIN_PIN00 (0UL)
64 #define GPIOM_ASSIGN_PIN_PIN01 (1UL)
65 #define GPIOM_ASSIGN_PIN_PIN02 (2UL)
66 #define GPIOM_ASSIGN_PIN_PIN03 (3UL)
67 #define GPIOM_ASSIGN_PIN_PIN04 (4UL)
68 #define GPIOM_ASSIGN_PIN_PIN05 (5UL)
69 #define GPIOM_ASSIGN_PIN_PIN06 (6UL)
70 #define GPIOM_ASSIGN_PIN_PIN07 (7UL)
71 #define GPIOM_ASSIGN_PIN_PIN08 (8UL)
72 #define GPIOM_ASSIGN_PIN_PIN09 (9UL)
73 #define GPIOM_ASSIGN_PIN_PIN10 (10UL)
74 #define GPIOM_ASSIGN_PIN_PIN11 (11UL)
75 #define GPIOM_ASSIGN_PIN_PIN12 (12UL)
76 #define GPIOM_ASSIGN_PIN_PIN13 (13UL)
77 #define GPIOM_ASSIGN_PIN_PIN14 (14UL)
78 #define GPIOM_ASSIGN_PIN_PIN15 (15UL)
79 #define GPIOM_ASSIGN_PIN_PIN16 (16UL)
80 #define GPIOM_ASSIGN_PIN_PIN17 (17UL)
81 #define GPIOM_ASSIGN_PIN_PIN18 (18UL)
82 #define GPIOM_ASSIGN_PIN_PIN19 (19UL)
83 #define GPIOM_ASSIGN_PIN_PIN20 (20UL)
84 #define GPIOM_ASSIGN_PIN_PIN21 (21UL)
85 #define GPIOM_ASSIGN_PIN_PIN22 (22UL)
86 #define GPIOM_ASSIGN_PIN_PIN23 (23UL)
87 #define GPIOM_ASSIGN_PIN_PIN24 (24UL)
88 #define GPIOM_ASSIGN_PIN_PIN25 (25UL)
89 #define GPIOM_ASSIGN_PIN_PIN26 (26UL)
90 #define GPIOM_ASSIGN_PIN_PIN27 (27UL)
91 #define GPIOM_ASSIGN_PIN_PIN28 (28UL)
92 #define GPIOM_ASSIGN_PIN_PIN29 (29UL)
93 #define GPIOM_ASSIGN_PIN_PIN30 (30UL)
94 #define GPIOM_ASSIGN_PIN_PIN31 (31UL)
95 
96 /* ASSIGN register group index macro definition */
97 #define GPIOM_ASSIGN_GPIOA (0UL)
98 #define GPIOM_ASSIGN_GPIOB (1UL)
99 #define GPIOM_ASSIGN_GPIOC (2UL)
100 #define GPIOM_ASSIGN_GPIOD (3UL)
101 #define GPIOM_ASSIGN_GPIOE (4UL)
102 #define GPIOM_ASSIGN_GPIOF (5UL)
103 #define GPIOM_ASSIGN_GPIOX (13UL)
104 #define GPIOM_ASSIGN_GPIOY (14UL)
105 #define GPIOM_ASSIGN_GPIOZ (15UL)
106 
107 
108 #endif /* HPM_GPIOM_H */
109