1 /*
2  * Copyright (c) 2023-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_SOC_FEATURE_H
9 #define HPM_SOC_FEATURE_H
10 
11 #include "hpm_soc.h"
12 #include "hpm_soc_ip_feature.h"
13 
14 /*
15  * I2C Section
16  */
17 #define I2C_SOC_FIFO_SIZE (4U)
18 #define I2C_SOC_TRANSFER_COUNT_MAX (4096U)
19 
20 /*
21  * PMIC Section
22  */
23 #define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)
24 #define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)
25 #define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)
26 #define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)
27 #define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)
28 #define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)
29 
30 /*
31  * I2S Section
32  */
33 #define I2S_SOC_MAX_CHANNEL_NUM (16U)
34 #define I2S_SOC_MAX_TX_CHANNEL_NUM (8U)
35 #define I2S_SOC_MAX_TX_FIFO_DEPTH (8U)
36 #define PDM_I2S HPM_I2S0
37 #define DAO_I2S HPM_I2S1
38 #define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U)
39 #define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U)
40 #define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U)
41 #define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U)
42 #define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U)
43 
44 /*
45  * PLLCTL Section
46  */
47 #define PLLCTL_SOC_PLL_MAX_COUNT (5U)
48 /* PLL reference clock in hz */
49 #define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)
50 /* only PLL1 and PLL2 have DIV0, DIV1 */
51 #define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
52 #define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
53 
54 
55 /*
56  * PWM Section
57  */
58 #define PWM_SOC_PWM_MAX_COUNT (8U)
59 #define PWM_SOC_CMP_MAX_COUNT (24U)
60 #define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)
61 #define PWM_SOC_OUTPUT_MAX_COUNT (24U)
62 
63 /*
64  * DMA Section
65  */
66 #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD)
67 #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T)
68 #define DMA_SOC_CHANNEL_NUM (32U)
69 #define DMA_SOC_MAX_COUNT (2U)
70 #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n))
71 #define DMA_SOC_HAS_IDLE_FLAG (1U)
72 
73 /*
74  * PDMA Section
75  */
76 #define PDMA_SOC_PS_MAX_COUNT (2U)
77 #define PDMA_SOC_SUPPORT_BS16 (0U)
78 
79 /*
80  * LCDC Section
81  */
82 #define LCDC_SOC_MAX_LAYER_COUNT         (8U)
83 #define LCDC_SOC_MAX_CSC_LAYER_COUNT     (2U)
84 #define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2)
85 #define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2)
86 
87 /*
88  * USB Section
89  */
90 #define USB_SOC_MAX_COUNT                          (1U)
91 
92 #define USB_SOC_DCD_QTD_NEXT_INVALID               (1U)
93 #define USB_SOC_DCD_QHD_BUFFER_COUNT               (5U)
94 #define USB_SOC_DCD_MAX_ENDPOINT_COUNT             (16U)
95 #ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT
96 #define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT        (8U)
97 #endif
98 #define USB_SOC_DCD_MAX_QTD_COUNT                  (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)
99 #define USB_SOS_DCD_MAX_QHD_COUNT                  (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)
100 #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT     (2048U)
101 
102 #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS         (1024U)
103 
104 /*
105  * ENET Section
106  */
107 #define ENET_SOC_RGMII_EN                          (1U)
108 #define ENET_SOC_DESC_ADDR_ALIGNMENT               (32U)
109 #define ENET_SOC_BUFF_ADDR_ALIGNMENT               (4U)
110 #define ENET_SOC_ADDR_MAX_COUNT                    (5U)
111 #define ENET_SOC_ALT_EHD_DES_MIN_LEN               (4U)
112 #define ENET_SOC_ALT_EHD_DES_MAX_LEN               (8U)
113 #define ENET_SOC_ALT_EHD_DES_LEN                   (8U)
114 #define ENET_SOC_PPS_MAX_COUNT                     (4L)
115 #define ENET_SOC_PPS1_EN                           (0U)
116 
117 /*
118  * ADC Section
119  */
120 #define ADC_SOC_SEQ_MAX_LEN                        (16U)
121 #define ADC_SOC_SEQ_HCFG_EN                        (1U)
122 #define ADC_SOC_MAX_TRIG_CH_LEN                    (4U)
123 #define ADC_SOC_MAX_TRIG_CH_NUM                    (11U)
124 #define ADC_SOC_DMA_ADDR_ALIGNMENT                 (4U)
125 #define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE         (8U)
126 #define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT        (1U)
127 #define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES     (16777216U)
128 #define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES     (48U)
129 #define ADC_SOC_NO_HW_TRIG_SRC                     (1U)
130 
131 #define ADC16_SOC_PARAMS_LEN                       (34U)
132 #define ADC16_SOC_MAX_CH_NUM                       (15U)
133 #define ADC16_SOC_TEMP_CH_EN                       (0U)
134 #define ADC16_SOC_MAX_SAMPLE_VALUE                 (65535U)
135 #define ADC16_SOC_MAX_CONV_CLK_NUM                 (21U)
136 
137 /*
138  * SYSCTL Section
139  */
140 #define SYSCTL_SOC_CPU_GPR_COUNT (14U)
141 #define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)
142 
143 /*
144  * PTPC Section
145  */
146 #define PTPC_SOC_TIMER_MAX_COUNT       (2U)
147 
148 /*
149  * SDP Section
150  */
151 #define SDP_REGISTER_DESCRIPTOR_COUNT (1U)
152 #define SDP_HAS_SM3_SUPPORT (1U)
153 #define SDP_HAS_SM4_SUPPORT (1U)
154 
155 /*
156  * SOC Privilege mode
157  */
158 #define SOC_HAS_S_MODE              (1U)
159 
160 /*
161  * DAC Section
162  */
163 #define DAC_SOC_BUFF_ALIGNED_SIZE (32U)
164 #define DAC_SOC_MAX_DATA          (4095U)
165 #define DAC_SOC_MAX_BUFF_COUNT    (65536U)
166 #define DAC_SOC_MAX_OUTPUT_FREQ   (1000000UL)
167 
168 
169 /*
170  * SDXC Section
171  */
172 #define SDXC_SOC_HAS_MISC_CTRL0 (1)
173 #define SDXC_SOC_HAS_MISC_CTRL1 (1)
174 #define SDXC_SOC_MAX_COUNT      (2)
175 
176 /*
177  * UART Section
178  */
179 #define UART_SOC_FIFO_SIZE                 (16U)
180 
181 /*
182  * SPI Section
183  */
184 #define SPI_SOC_TRANSFER_COUNT_MAX  (0xFFFFFFFFU)
185 #define SPI_SOC_FIFO_DEPTH          (8U)
186 
187 /*
188  * EWDG Section
189  */
190 #define EWDG_SOC_CLK_DIV_VAL_MAX           (5U)
191 #define EWDG_SOC_OVERTIME_REG_WIDTH        (16U)
192 #define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (0U)
193 
194 
195 /*
196  * MCAN Section
197  */
198 #define MCAN_SOC_MSG_BUF_IN_IP          (0U)
199 #define MCAN_SOC_MSG_BUF_IN_AHB_RAM     (1U)
200 #define MCAN_SOC_MAX_COUNT              (8U)
201 #define CAN_SOC_MAX_COUNT               MCAN_SOC_MAX_COUNT
202 
203 /*
204  * OTP Section
205  */
206 #define OTP_SOC_MAC0_IDX   (65U)
207 #define OTP_SOC_MAC0_LEN   (6U)  /* in bytes */
208 
209 #define OTP_SOC_UUID_IDX   (88U)
210 #define OTP_SOC_UUID_LEN   (16U) /* in bytes */
211 
212 /**
213  * PWM Section
214  *
215  */
216 #define PWM_SOC_HRPWM_SUPPORT  (0U)
217 #define PWM_SOC_SHADOW_TRIG_SUPPORT (0U)
218 #define PWM_SOC_TIMER_RESET_SUPPORT (0U)
219 
220 #endif /* HPM_SOC_FEATURE_H */
221