1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LVB_H 10 #define HPM_LVB_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: control register */ 14 __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ 15 __R uint32_t PHY_STAT; /* 0x10: LVDS TX PHY Status register */ 16 __RW uint32_t PHY_POW_CTRL[2]; /* 0x14 - 0x18: LVDS0 PHY power control register */ 17 struct { 18 __RW uint32_t CTL0; /* 0x1C: TX PHY Setting */ 19 __RW uint32_t CTL1; /* 0x20: TX_PHY Setting */ 20 } TX_PHY[10]; 21 } LVB_Type; 22 23 24 /* Bitfield definition for register: CTRL */ 25 /* 26 * SPLIT_CH_REVERSE (RW) 27 * 28 * Just for split mode, reverse two channel data 29 */ 30 #define LVB_CTRL_SPLIT_CH_REVERSE_MASK (0x8000000UL) 31 #define LVB_CTRL_SPLIT_CH_REVERSE_SHIFT (27U) 32 #define LVB_CTRL_SPLIT_CH_REVERSE_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) 33 #define LVB_CTRL_SPLIT_CH_REVERSE_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) >> LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) 34 35 /* 36 * SPLIT_CH_MODE (RW) 37 * 38 * Just for split mode 39 * 1: two channel pixel data are not aligned 40 * 0: two channel pixel data are aligned 41 */ 42 #define LVB_CTRL_SPLIT_CH_MODE_MASK (0x4000000UL) 43 #define LVB_CTRL_SPLIT_CH_MODE_SHIFT (26U) 44 #define LVB_CTRL_SPLIT_CH_MODE_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_MODE_SHIFT) & LVB_CTRL_SPLIT_CH_MODE_MASK) 45 #define LVB_CTRL_SPLIT_CH_MODE_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_MODE_MASK) >> LVB_CTRL_SPLIT_CH_MODE_SHIFT) 46 47 /* 48 * SPLIT_HSWHBP_WIDTH (RW) 49 * 50 * Just for split mode, the sum of HSW and HBP width is even 51 * 1: yes 52 * 0: no 53 */ 54 #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK (0x2000000UL) 55 #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT (25U) 56 #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) 57 #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) >> LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) 58 59 /* 60 * SPLIT_MODE_EN (RW) 61 * 62 * Split mode enable: 63 * 1: enable 64 * 0: disable 65 * Note: when using split mode, ch0/1 should be enabled, and should select same DI 66 */ 67 #define LVB_CTRL_SPLIT_MODE_EN_MASK (0x1000000UL) 68 #define LVB_CTRL_SPLIT_MODE_EN_SHIFT (24U) 69 #define LVB_CTRL_SPLIT_MODE_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_MODE_EN_SHIFT) & LVB_CTRL_SPLIT_MODE_EN_MASK) 70 #define LVB_CTRL_SPLIT_MODE_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_MODE_EN_MASK) >> LVB_CTRL_SPLIT_MODE_EN_SHIFT) 71 72 /* 73 * DI1_VSYNC_POLARITY (RW) 74 * 75 * DI 1 vsync polarity: 76 * 1: active low 77 * 0: active high 78 */ 79 #define LVB_CTRL_DI1_VSYNC_POLARITY_MASK (0x20000UL) 80 #define LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT (17U) 81 #define LVB_CTRL_DI1_VSYNC_POLARITY_SET(x) (((uint32_t)(x) << LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) 82 #define LVB_CTRL_DI1_VSYNC_POLARITY_GET(x) (((uint32_t)(x) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) 83 84 /* 85 * DI0_VSYNC_POLARITY (RW) 86 * 87 * DI 0 vsync polarity: 88 * 1: active low 89 * 0: active high 90 */ 91 #define LVB_CTRL_DI0_VSYNC_POLARITY_MASK (0x10000UL) 92 #define LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT (16U) 93 #define LVB_CTRL_DI0_VSYNC_POLARITY_SET(x) (((uint32_t)(x) << LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) 94 #define LVB_CTRL_DI0_VSYNC_POLARITY_GET(x) (((uint32_t)(x) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) 95 96 /* 97 * LVDS_TXCLK_SHIFT (RW) 98 * 99 * Shift the LVDS TX PHY clock in relation to the data. 100 * 000: txck is 7'b1100011 101 * 001: txck is 7‘b1110001 102 * 010: txck is 7‘b1111000 103 * 011: txck is 7‘b1000111 104 * 100: txck is 7‘b0001111 105 * 101: txck is 7‘b0011110 106 * 110: txck is 7‘b0111100 107 * 111: txck is 7‘b1100011 108 */ 109 #define LVB_CTRL_LVDS_TXCLK_SHIFT_MASK (0x700U) 110 #define LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT (8U) 111 #define LVB_CTRL_LVDS_TXCLK_SHIFT_SET(x) (((uint32_t)(x) << LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) 112 #define LVB_CTRL_LVDS_TXCLK_SHIFT_GET(x) (((uint32_t)(x) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) >> LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) 113 114 /* 115 * CH1_BIT_MAPPING (RW) 116 * 117 * Channel 1 data protocol: 118 * 1: JEIDA standard 119 * 0: SPWG standard 120 */ 121 #define LVB_CTRL_CH1_BIT_MAPPING_MASK (0x80U) 122 #define LVB_CTRL_CH1_BIT_MAPPING_SHIFT (7U) 123 #define LVB_CTRL_CH1_BIT_MAPPING_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_BIT_MAPPING_SHIFT) & LVB_CTRL_CH1_BIT_MAPPING_MASK) 124 #define LVB_CTRL_CH1_BIT_MAPPING_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_BIT_MAPPING_MASK) >> LVB_CTRL_CH1_BIT_MAPPING_SHIFT) 125 126 /* 127 * CH0_BIT_MAPPING (RW) 128 * 129 * Channel 0 data protocol: 130 * 1: JEIDA standard 131 * 0: SPWG standard 132 */ 133 #define LVB_CTRL_CH0_BIT_MAPPING_MASK (0x20U) 134 #define LVB_CTRL_CH0_BIT_MAPPING_SHIFT (5U) 135 #define LVB_CTRL_CH0_BIT_MAPPING_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_BIT_MAPPING_SHIFT) & LVB_CTRL_CH0_BIT_MAPPING_MASK) 136 #define LVB_CTRL_CH0_BIT_MAPPING_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_BIT_MAPPING_MASK) >> LVB_CTRL_CH0_BIT_MAPPING_SHIFT) 137 138 /* 139 * CH1_SEL (RW) 140 * 141 * Channel 1 select: 142 * 1: select DI 1 143 * 0: select DI 0 144 */ 145 #define LVB_CTRL_CH1_SEL_MASK (0x8U) 146 #define LVB_CTRL_CH1_SEL_SHIFT (3U) 147 #define LVB_CTRL_CH1_SEL_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_SEL_SHIFT) & LVB_CTRL_CH1_SEL_MASK) 148 #define LVB_CTRL_CH1_SEL_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_SEL_MASK) >> LVB_CTRL_CH1_SEL_SHIFT) 149 150 /* 151 * CH1_EN (RW) 152 * 153 * Channel 1 enable: 154 * 1: enable 155 * 0: disable 156 */ 157 #define LVB_CTRL_CH1_EN_MASK (0x4U) 158 #define LVB_CTRL_CH1_EN_SHIFT (2U) 159 #define LVB_CTRL_CH1_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_EN_SHIFT) & LVB_CTRL_CH1_EN_MASK) 160 #define LVB_CTRL_CH1_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_EN_MASK) >> LVB_CTRL_CH1_EN_SHIFT) 161 162 /* 163 * CH0_SEL (RW) 164 * 165 * Channel 0 select: 166 * 1: select DI 1 167 * 0: select DI 0 168 */ 169 #define LVB_CTRL_CH0_SEL_MASK (0x2U) 170 #define LVB_CTRL_CH0_SEL_SHIFT (1U) 171 #define LVB_CTRL_CH0_SEL_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_SEL_SHIFT) & LVB_CTRL_CH0_SEL_MASK) 172 #define LVB_CTRL_CH0_SEL_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_SEL_MASK) >> LVB_CTRL_CH0_SEL_SHIFT) 173 174 /* 175 * CH0_EN (RW) 176 * 177 * Channel 0 enable: 178 * 1: enable 179 * 0: disable 180 */ 181 #define LVB_CTRL_CH0_EN_MASK (0x1U) 182 #define LVB_CTRL_CH0_EN_SHIFT (0U) 183 #define LVB_CTRL_CH0_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_EN_SHIFT) & LVB_CTRL_CH0_EN_MASK) 184 #define LVB_CTRL_CH0_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_EN_MASK) >> LVB_CTRL_CH0_EN_SHIFT) 185 186 /* Bitfield definition for register: PHY_STAT */ 187 /* 188 * LVDS1_TX_PHY_PLL_LOCK (RO) 189 * 190 * LVDS1 TX PHY PLL Lock indication Signal, 1 means pll already locked 191 */ 192 #define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK (0x2U) 193 #define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT (1U) 194 #define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(x) (((uint32_t)(x) & LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT) 195 196 /* 197 * LVDS0_TX_PHY_PLL_LOCK (RO) 198 * 199 * LVDS0 TX PHY PLL Lock indication Signal, 1 means pll already locked 200 */ 201 #define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK (0x1U) 202 #define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT (0U) 203 #define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(x) (((uint32_t)(x) & LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT) 204 205 /* Bitfield definition for register array: PHY_POW_CTRL */ 206 /* 207 * PWON_PLL (RW) 208 * 209 * pll power on 210 */ 211 #define LVB_PHY_POW_CTRL_PWON_PLL_MASK (0x20U) 212 #define LVB_PHY_POW_CTRL_PWON_PLL_SHIFT (5U) 213 #define LVB_PHY_POW_CTRL_PWON_PLL_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) 214 #define LVB_PHY_POW_CTRL_PWON_PLL_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) >> LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) 215 216 /* 217 * TXCK_PD (RW) 218 * 219 * Power down control signal of channel txck 220 * 0: Normal operation 221 * 1: Power down channel 222 */ 223 #define LVB_PHY_POW_CTRL_TXCK_PD_MASK (0x10U) 224 #define LVB_PHY_POW_CTRL_TXCK_PD_SHIFT (4U) 225 #define LVB_PHY_POW_CTRL_TXCK_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) 226 #define LVB_PHY_POW_CTRL_TXCK_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) >> LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) 227 228 /* 229 * TX3_PD (RW) 230 * 231 * Power down control signal of channel tx3 232 * 0: Normal operation 233 * 1: Power down channel 234 */ 235 #define LVB_PHY_POW_CTRL_TX3_PD_MASK (0x8U) 236 #define LVB_PHY_POW_CTRL_TX3_PD_SHIFT (3U) 237 #define LVB_PHY_POW_CTRL_TX3_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX3_PD_SHIFT) & LVB_PHY_POW_CTRL_TX3_PD_MASK) 238 #define LVB_PHY_POW_CTRL_TX3_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX3_PD_MASK) >> LVB_PHY_POW_CTRL_TX3_PD_SHIFT) 239 240 /* 241 * TX2_PD (RW) 242 * 243 * Power down control signal of channel tx2 244 * 0: Normal operation 245 * 1: Power down channel 246 */ 247 #define LVB_PHY_POW_CTRL_TX2_PD_MASK (0x4U) 248 #define LVB_PHY_POW_CTRL_TX2_PD_SHIFT (2U) 249 #define LVB_PHY_POW_CTRL_TX2_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX2_PD_SHIFT) & LVB_PHY_POW_CTRL_TX2_PD_MASK) 250 #define LVB_PHY_POW_CTRL_TX2_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX2_PD_MASK) >> LVB_PHY_POW_CTRL_TX2_PD_SHIFT) 251 252 /* 253 * TX1_PD (RW) 254 * 255 * Power down control signal of channel tx1 256 * 0: Normal operation 257 * 1: Power down channel 258 */ 259 #define LVB_PHY_POW_CTRL_TX1_PD_MASK (0x2U) 260 #define LVB_PHY_POW_CTRL_TX1_PD_SHIFT (1U) 261 #define LVB_PHY_POW_CTRL_TX1_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX1_PD_SHIFT) & LVB_PHY_POW_CTRL_TX1_PD_MASK) 262 #define LVB_PHY_POW_CTRL_TX1_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX1_PD_MASK) >> LVB_PHY_POW_CTRL_TX1_PD_SHIFT) 263 264 /* 265 * TX0_PD (RW) 266 * 267 * Power down control signal of channel tx0 268 * 0: Normal operation 269 * 1: Power down channel 270 */ 271 #define LVB_PHY_POW_CTRL_TX0_PD_MASK (0x1U) 272 #define LVB_PHY_POW_CTRL_TX0_PD_SHIFT (0U) 273 #define LVB_PHY_POW_CTRL_TX0_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX0_PD_SHIFT) & LVB_PHY_POW_CTRL_TX0_PD_MASK) 274 #define LVB_PHY_POW_CTRL_TX0_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX0_PD_MASK) >> LVB_PHY_POW_CTRL_TX0_PD_SHIFT) 275 276 /* Bitfield definition for register of struct array TX_PHY: CTL0 */ 277 /* 278 * TX_IDLE (RW) 279 * 280 * Force the high-speed differential signal to common mode. 281 * This signal can be set during IP power up stage to prevent unexpected leakage current in TXP/TXN 282 * 0: Normal operation 283 * 1: Force TXPN /TXMN to common mode 284 */ 285 #define LVB_TX_PHY_CTL0_TX_IDLE_MASK (0x100000UL) 286 #define LVB_TX_PHY_CTL0_TX_IDLE_SHIFT (20U) 287 #define LVB_TX_PHY_CTL0_TX_IDLE_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) 288 #define LVB_TX_PHY_CTL0_TX_IDLE_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) >> LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) 289 290 /* 291 * TX_RTERM_EN (RW) 292 * 293 * Inner Terminal Resistance enable 294 * 0: Disable rterm 2000ohm 295 * 1: Enable rterm 100ohm 296 */ 297 #define LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK (0x80000UL) 298 #define LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT (19U) 299 #define LVB_TX_PHY_CTL0_TX_RTERM_EN_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) 300 #define LVB_TX_PHY_CTL0_TX_RTERM_EN_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) >> LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) 301 302 /* 303 * TX_BUS_WIDTH (RW) 304 * 305 * Parallel data bus width select： 306 * 000: 4-bit mode, txN_data[3:0] are valid, txN_data[11:4] can be arbitrary state. 307 * 001: 6-bit mode, txN_data[5:0] are valid, txN_data[11:6] can be arbitrary state. 308 * 010: 7-bit mode. txN_data[6:0] are valid, txN_data[11:7] can be arbitrary state. 309 * 011: 8-bit mode. txN_data[7:0] are valid, txN_data[11:8] can be arbitrary state. 310 * 100: 9-bit mode. txN_data[8:0] are valid, txN_data[11:9] can be arbitrary state. 311 * 101: 10-bit mode. txN_data[9:0] are valid, txN_data[11:10] can be arbitrary state. 312 * 110: 11-bit mode. txN_data[10:0] are valid, txN_data[11] can be arbitrary state. 313 * 111: 12-bit mode. txN_data[11:0] are valid 314 */ 315 #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK (0x70000UL) 316 #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT (16U) 317 #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) 318 #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) >> LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) 319 320 /* 321 * TX_PHASE_SEL (RW) 322 * 323 * data/clock lane output phase adjustment: 324 * 0000: 0 325 * 0001: data lane is 1/32, clock lane is 1/16 326 * 0010: data lane is 2/32, clock lane is 2/16 327 * 0011: data lane is 3/32, clock lane is 3/16 328 * 0100: data lane is 4/32, clock lane is 4/16 329 * 0101: data lane is 5/32, clock lane is 5/16 330 * 0110: data lane is 6/32, clock lane is 6/16 331 * 0111: data lane is 7/32, clock lane is 7/16 332 * 1000: data lane is 8/32, clock lane is 8/16 333 * 1001: data lane is 9/32, clock lane is 9/16 334 * 1010: data lane is 10/32, clock lane is 10/16 335 * 1011: data lane is 11/32, clock lane is 11/16 336 * 1100: data lane is 12/32, clock lane is 12/16 337 * 1101: data lane is 13/32, clock lane is 13/16 338 * 1110: data lane is 14/32, clock lane is 14/16 339 * 1111: data lane is 15/32, clock lane is 15/16 340 */ 341 #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK (0xF000U) 342 #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT (12U) 343 #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) 344 #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) >> LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) 345 346 /* 347 * TX_VCOM (RW) 348 * 349 * output Common Mode Voltage adjustment(Unit: V). 350 * 0000: 0.7 351 * 0001: 0.8 352 * 0010: 0.9 353 * 0011: 1.0 354 * 0100: 1.1 355 * 0101: 1.2 356 * 0110: 1.3 357 * 0111: 1.4 358 * 1000~1111: 1.5 359 */ 360 #define LVB_TX_PHY_CTL0_TX_VCOM_MASK (0xF00U) 361 #define LVB_TX_PHY_CTL0_TX_VCOM_SHIFT (8U) 362 #define LVB_TX_PHY_CTL0_TX_VCOM_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) 363 #define LVB_TX_PHY_CTL0_TX_VCOM_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) >> LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) 364 365 /* 366 * TX_AMP (RW) 367 * 368 * Output voltage Adjustment(Unit: mV). 369 * 0000 : 50 370 * 0001: 100 371 * 0010: 150 372 * 0011: 200 373 * 0100: 250 374 * 0101: 300 375 * 0110: 350 376 * 0111: 400 377 * 1000: 450 378 * 1001: 500 379 * 1010: 550 380 * 1011~1111: 600 381 */ 382 #define LVB_TX_PHY_CTL0_TX_AMP_MASK (0xF0U) 383 #define LVB_TX_PHY_CTL0_TX_AMP_SHIFT (4U) 384 #define LVB_TX_PHY_CTL0_TX_AMP_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_AMP_SHIFT) & LVB_TX_PHY_CTL0_TX_AMP_MASK) 385 #define LVB_TX_PHY_CTL0_TX_AMP_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_AMP_MASK) >> LVB_TX_PHY_CTL0_TX_AMP_SHIFT) 386 387 /* 388 * TX_SR (RW) 389 * 390 * output slew-rate trimming 391 * 00: slowest slew-rate; 392 * 11: fastest slew-rate 393 */ 394 #define LVB_TX_PHY_CTL0_TX_SR_MASK (0xCU) 395 #define LVB_TX_PHY_CTL0_TX_SR_SHIFT (2U) 396 #define LVB_TX_PHY_CTL0_TX_SR_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_SR_SHIFT) & LVB_TX_PHY_CTL0_TX_SR_MASK) 397 #define LVB_TX_PHY_CTL0_TX_SR_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_SR_MASK) >> LVB_TX_PHY_CTL0_TX_SR_SHIFT) 398 399 /* 400 * TX_DEEMP (RW) 401 * 402 * output de-emphasis level trimming(Unit: dB) 403 * 00: 0 404 * 01: 2.5 405 * 10: 6.0 406 * 11: 6.0 407 */ 408 #define LVB_TX_PHY_CTL0_TX_DEEMP_MASK (0x3U) 409 #define LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT (0U) 410 #define LVB_TX_PHY_CTL0_TX_DEEMP_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) 411 #define LVB_TX_PHY_CTL0_TX_DEEMP_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) >> LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) 412 413 /* Bitfield definition for register of struct array TX_PHY: CTL1 */ 414 /* 415 * TX_CTL (RW) 416 * 417 */ 418 #define LVB_TX_PHY_CTL1_TX_CTL_MASK (0xFFFFFUL) 419 #define LVB_TX_PHY_CTL1_TX_CTL_SHIFT (0U) 420 #define LVB_TX_PHY_CTL1_TX_CTL_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL1_TX_CTL_SHIFT) & LVB_TX_PHY_CTL1_TX_CTL_MASK) 421 #define LVB_TX_PHY_CTL1_TX_CTL_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL1_TX_CTL_MASK) >> LVB_TX_PHY_CTL1_TX_CTL_SHIFT) 422 423 424 425 /* PHY_POW_CTRL register group index macro definition */ 426 #define LVB_PHY_POW_CTRL_LVDS0 (0UL) 427 #define LVB_PHY_POW_CTRL_LVDS1 (1UL) 428 429 /* TX_PHY register group index macro definition */ 430 #define LVB_TX_PHY_LVDS0_TX0 (0UL) 431 #define LVB_TX_PHY_LVDS0_TX1 (1UL) 432 #define LVB_TX_PHY_LVDS0_TX2 (1UL) 433 #define LVB_TX_PHY_LVDS0_TX3 (3UL) 434 #define LVB_TX_PHY_LVDS0_TXCK (4UL) 435 #define LVB_TX_PHY_LVDS1_TX0 (5UL) 436 #define LVB_TX_PHY_LVDS1_TX1 (6UL) 437 #define LVB_TX_PHY_LVDS1_TX2 (7UL) 438 #define LVB_TX_PHY_LVDS1_TX3 (8UL) 439 #define LVB_TX_PHY_LVDS1_TXCK (9UL) 440 441 442 #endif /* HPM_LVB_H */ 443