1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SOC_H
10 #define HPM_SOC_H
11 
12 
13 /* List of external IRQs */
14 #define IRQn_GPIO0_A                   1       /* GPIO0_A IRQ */
15 #define IRQn_GPIO0_B                   2       /* GPIO0_B IRQ */
16 #define IRQn_GPIO0_C                   3       /* GPIO0_C IRQ */
17 #define IRQn_GPIO0_D                   4       /* GPIO0_D IRQ */
18 #define IRQn_GPIO0_E                   5       /* GPIO0_E IRQ */
19 #define IRQn_GPIO0_F                   6       /* GPIO0_F IRQ */
20 #define IRQn_GPIO0_V                   7       /* GPIO0_V IRQ */
21 #define IRQn_GPIO0_W                   8       /* GPIO0_W IRQ */
22 #define IRQn_GPIO0_X                   9       /* GPIO0_X IRQ */
23 #define IRQn_GPIO0_Y                   10      /* GPIO0_Y IRQ */
24 #define IRQn_GPIO0_Z                   11      /* GPIO0_Z IRQ */
25 #define IRQn_GPIO1_A                   12      /* GPIO1_A IRQ */
26 #define IRQn_GPIO1_B                   13      /* GPIO1_B IRQ */
27 #define IRQn_GPIO1_C                   14      /* GPIO1_C IRQ */
28 #define IRQn_GPIO1_D                   15      /* GPIO1_D IRQ */
29 #define IRQn_GPIO1_E                   16      /* GPIO1_E IRQ */
30 #define IRQn_GPIO1_F                   17      /* GPIO1_F IRQ */
31 #define IRQn_GPIO1_V                   18      /* GPIO1_V IRQ */
32 #define IRQn_GPIO1_W                   19      /* GPIO1_W IRQ */
33 #define IRQn_GPIO1_X                   20      /* GPIO1_X IRQ */
34 #define IRQn_GPIO1_Y                   21      /* GPIO1_Y IRQ */
35 #define IRQn_GPIO1_Z                   22      /* GPIO1_Z IRQ */
36 #define IRQn_GPTMR0                    23      /* GPTMR0 IRQ */
37 #define IRQn_GPTMR1                    24      /* GPTMR1 IRQ */
38 #define IRQn_GPTMR2                    25      /* GPTMR2 IRQ */
39 #define IRQn_GPTMR3                    26      /* GPTMR3 IRQ */
40 #define IRQn_GPTMR4                    27      /* GPTMR4 IRQ */
41 #define IRQn_GPTMR5                    28      /* GPTMR5 IRQ */
42 #define IRQn_GPTMR6                    29      /* GPTMR6 IRQ */
43 #define IRQn_GPTMR7                    30      /* GPTMR7 IRQ */
44 #define IRQn_UART0                     31      /* UART0 IRQ */
45 #define IRQn_UART1                     32      /* UART1 IRQ */
46 #define IRQn_UART2                     33      /* UART2 IRQ */
47 #define IRQn_UART3                     34      /* UART3 IRQ */
48 #define IRQn_UART4                     35      /* UART4 IRQ */
49 #define IRQn_UART5                     36      /* UART5 IRQ */
50 #define IRQn_UART6                     37      /* UART6 IRQ */
51 #define IRQn_UART7                     38      /* UART7 IRQ */
52 #define IRQn_I2C0                      39      /* I2C0 IRQ */
53 #define IRQn_I2C1                      40      /* I2C1 IRQ */
54 #define IRQn_I2C2                      41      /* I2C2 IRQ */
55 #define IRQn_I2C3                      42      /* I2C3 IRQ */
56 #define IRQn_SPI0                      43      /* SPI0 IRQ */
57 #define IRQn_SPI1                      44      /* SPI1 IRQ */
58 #define IRQn_SPI2                      45      /* SPI2 IRQ */
59 #define IRQn_SPI3                      46      /* SPI3 IRQ */
60 #define IRQn_TSNS                      47      /* TSNS IRQ */
61 #define IRQn_MBX0A                     48      /* MBX0A IRQ */
62 #define IRQn_MBX0B                     49      /* MBX0B IRQ */
63 #define IRQn_MBX1A                     50      /* MBX1A IRQ */
64 #define IRQn_MBX1B                     51      /* MBX1B IRQ */
65 #define IRQn_EWDG0                     52      /* EWDG0 IRQ */
66 #define IRQn_EWDG1                     53      /* EWDG1 IRQ */
67 #define IRQn_EWDG2                     54      /* EWDG2 IRQ */
68 #define IRQn_EWDG3                     55      /* EWDG3 IRQ */
69 #define IRQn_HDMA                      56      /* HDMA IRQ */
70 #define IRQn_LOBS                      57      /* LOBS IRQ */
71 #define IRQn_ADC0                      58      /* ADC0 IRQ */
72 #define IRQn_ADC1                      59      /* ADC1 IRQ */
73 #define IRQn_ADC2                      60      /* ADC2 IRQ */
74 #define IRQn_ADC3                      61      /* ADC3 IRQ */
75 #define IRQn_ACMP0_0                   62      /* ACMP0[0] IRQ */
76 #define IRQn_ACMP0_1                   63      /* ACMP0[1] IRQ */
77 #define IRQn_ACMP1_0                   64      /* ACMP1[0] IRQ */
78 #define IRQn_ACMP1_1                   65      /* ACMP1[1] IRQ */
79 #define IRQn_ACMP2_0                   66      /* ACMP2[0] IRQ */
80 #define IRQn_ACMP2_1                   67      /* ACMP2[1] IRQ */
81 #define IRQn_ACMP3_0                   68      /* ACMP3[0] IRQ */
82 #define IRQn_ACMP3_1                   69      /* ACMP3[1] IRQ */
83 #define IRQn_I2S0                      70      /* I2S0 IRQ */
84 #define IRQn_I2S1                      71      /* I2S1 IRQ */
85 #define IRQn_DAO                       72      /* DAO IRQ */
86 #define IRQn_PDM                       73      /* PDM IRQ */
87 #define IRQn_UART8                     74      /* UART8 IRQ */
88 #define IRQn_UART9                     75      /* UART9 IRQ */
89 #define IRQn_UART10                    76      /* UART10 IRQ */
90 #define IRQn_UART11                    77      /* UART11 IRQ */
91 #define IRQn_UART12                    78      /* UART12 IRQ */
92 #define IRQn_UART13                    79      /* UART13 IRQ */
93 #define IRQn_UART14                    80      /* UART14 IRQ */
94 #define IRQn_UART15                    81      /* UART15 IRQ */
95 #define IRQn_I2C4                      82      /* I2C4 IRQ */
96 #define IRQn_I2C5                      83      /* I2C5 IRQ */
97 #define IRQn_I2C6                      84      /* I2C6 IRQ */
98 #define IRQn_I2C7                      85      /* I2C7 IRQ */
99 #define IRQn_SPI4                      86      /* SPI4 IRQ */
100 #define IRQn_SPI5                      87      /* SPI5 IRQ */
101 #define IRQn_SPI6                      88      /* SPI6 IRQ */
102 #define IRQn_SPI7                      89      /* SPI7 IRQ */
103 #define IRQn_MCAN0                     90      /* MCAN0 IRQ */
104 #define IRQn_MCAN1                     91      /* MCAN1 IRQ */
105 #define IRQn_MCAN2                     92      /* MCAN2 IRQ */
106 #define IRQn_MCAN3                     93      /* MCAN3 IRQ */
107 #define IRQn_MCAN4                     94      /* MCAN4 IRQ */
108 #define IRQn_MCAN5                     95      /* MCAN5 IRQ */
109 #define IRQn_MCAN6                     96      /* MCAN6 IRQ */
110 #define IRQn_MCAN7                     97      /* MCAN7 IRQ */
111 #define IRQn_PTPC                      98      /* PTPC IRQ */
112 #define IRQn_QEI0                      99      /* QEI0 IRQ */
113 #define IRQn_QEI1                      100     /* QEI1 IRQ */
114 #define IRQn_QEI2                      101     /* QEI2 IRQ */
115 #define IRQn_QEI3                      102     /* QEI3 IRQ */
116 #define IRQn_PWM0                      103     /* PWM0 IRQ */
117 #define IRQn_PWM1                      104     /* PWM1 IRQ */
118 #define IRQn_PWM2                      105     /* PWM2 IRQ */
119 #define IRQn_PWM3                      106     /* PWM3 IRQ */
120 #define IRQn_RDC0                      107     /* RDC0 IRQ */
121 #define IRQn_RDC1                      108     /* RDC1 IRQ */
122 #define IRQn_SDM0                      109     /* SDM0 IRQ */
123 #define IRQn_SDM1                      110     /* SDM1 IRQ */
124 #define IRQn_SEI_0                     111     /* SEI[0] IRQ */
125 #define IRQn_SEI_1                     112     /* SEI[1] IRQ */
126 #define IRQn_SEI_2                     113     /* SEI[2] IRQ */
127 #define IRQn_SEI_3                     114     /* SEI[3] IRQ */
128 #define IRQn_MTG0                      115     /* MTG0 IRQ */
129 #define IRQn_MTG1                      116     /* MTG1 IRQ */
130 #define IRQn_VSC0                      117     /* VSC0 IRQ */
131 #define IRQn_VSC1                      118     /* VSC1 IRQ */
132 #define IRQn_CLC0_0                    119     /* CLC0[0] IRQ */
133 #define IRQn_CLC0_1                    120     /* CLC0[1] IRQ */
134 #define IRQn_CLC1_0                    121     /* CLC1[0] IRQ */
135 #define IRQn_CLC1_1                    122     /* CLC1[1] IRQ */
136 #define IRQn_TRGMUX0                   123     /* TRGMUX0 IRQ */
137 #define IRQn_TRGMUX1                   124     /* TRGMUX1 IRQ */
138 #define IRQn_ENET0                     125     /* ENET0 IRQ */
139 #define IRQn_NTMR0                     126     /* NTMR0 IRQ */
140 #define IRQn_USB0                      127     /* USB0 IRQ */
141 #define IRQn_TSW_0                     128     /* TSW[0] IRQ */
142 #define IRQn_TSW_1                     129     /* TSW[1] IRQ */
143 #define IRQn_TSW_2                     130     /* TSW[2] IRQ */
144 #define IRQn_TSW_3                     131     /* TSW[3] IRQ */
145 #define IRQn_TSW_PTP_EVT               132     /* TSW_PTP_EVT IRQ */
146 #define IRQn_ESC                       133     /* ESC IRQ */
147 #define IRQn_ESC_SYNC0                 134     /* ESC_SYNC0 IRQ */
148 #define IRQn_ESC_SYNC1                 135     /* ESC_SYNC1 IRQ */
149 #define IRQn_ESC_RESET                 136     /* ESC_RESET IRQ */
150 #define IRQn_XPI0                      137     /* XPI0 IRQ */
151 #define IRQn_FEMC                      138     /* FEMC IRQ */
152 #define IRQn_PPI                       139     /* PPI IRQ */
153 #define IRQn_XDMA                      140     /* XDMA IRQ */
154 #define IRQn_FFA                       141     /* FFA IRQ */
155 #define IRQn_SDP                       142     /* SDP IRQ */
156 #define IRQn_RNG                       143     /* RNG IRQ */
157 #define IRQn_PKA                       144     /* PKA IRQ */
158 #define IRQn_PSEC                      145     /* PSEC IRQ */
159 #define IRQn_PGPIO                     146     /* PGPIO IRQ */
160 #define IRQn_PEWDG                     147     /* PEWDG IRQ */
161 #define IRQn_PTMR                      148     /* PTMR IRQ */
162 #define IRQn_PUART                     149     /* PUART IRQ */
163 #define IRQn_FUSE                      150     /* FUSE IRQ */
164 #define IRQn_SECMON                    151     /* SECMON IRQ */
165 #define IRQn_RTC                       152     /* RTC IRQ */
166 #define IRQn_PAD_WAKEUP                153     /* PAD_WAKEUP IRQ */
167 #define IRQn_BGPIO                     154     /* BGPIO IRQ */
168 #define IRQn_BVIO                      155     /* BVIO IRQ */
169 #define IRQn_BROWNOUT                  156     /* BROWNOUT IRQ */
170 #define IRQn_SYSCTL                    157     /* SYSCTL IRQ */
171 #define IRQn_CPU0                      158     /* CPU0 IRQ */
172 #define IRQn_CPU1                      159     /* CPU1 IRQ */
173 #define IRQn_DEBUG0                    160     /* DEBUG0 IRQ */
174 #define IRQn_DEBUG1                    161     /* DEBUG1 IRQ */
175 
176 #include "hpm_common.h"
177 
178 #include "hpm_gpio_regs.h"
179 /* Address of GPIO instances */
180 /* FGPIO base address */
181 #define HPM_FGPIO_BASE (0x300000UL)
182 /* FGPIO base pointer */
183 #define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE)
184 /* GPIO0 base address */
185 #define HPM_GPIO0_BASE (0xF00D0000UL)
186 /* GPIO0 base pointer */
187 #define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE)
188 /* GPIO1 base address */
189 #define HPM_GPIO1_BASE (0xF00D4000UL)
190 /* GPIO1 base pointer */
191 #define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE)
192 /* PGPIO base address */
193 #define HPM_PGPIO_BASE (0xF411C000UL)
194 /* PGPIO base pointer */
195 #define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE)
196 /* BGPIO base address */
197 #define HPM_BGPIO_BASE (0xF4214000UL)
198 /* BGPIO base pointer */
199 #define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE)
200 
201 /* Address of DM instances */
202 /* DM base address */
203 #define HPM_DM_BASE (0x30000000UL)
204 
205 #include "hpm_plic_regs.h"
206 /* Address of PLIC instances */
207 /* PLIC base address */
208 #define HPM_PLIC_BASE (0xE4000000UL)
209 /* PLIC base pointer */
210 #define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE)
211 
212 #include "hpm_mchtmr_regs.h"
213 /* Address of MCHTMR instances */
214 /* MCHTMR base address */
215 #define HPM_MCHTMR_BASE (0xE6000000UL)
216 /* MCHTMR base pointer */
217 #define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE)
218 
219 #include "hpm_plic_sw_regs.h"
220 /* Address of PLICSW instances */
221 /* PLICSW base address */
222 #define HPM_PLICSW_BASE (0xE6400000UL)
223 /* PLICSW base pointer */
224 #define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE)
225 
226 #include "hpm_gptmr_regs.h"
227 /* Address of GPTMR instances */
228 /* GPTMR0 base address */
229 #define HPM_GPTMR0_BASE (0xF0000000UL)
230 /* GPTMR0 base pointer */
231 #define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE)
232 /* GPTMR1 base address */
233 #define HPM_GPTMR1_BASE (0xF0004000UL)
234 /* GPTMR1 base pointer */
235 #define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE)
236 /* GPTMR2 base address */
237 #define HPM_GPTMR2_BASE (0xF0008000UL)
238 /* GPTMR2 base pointer */
239 #define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE)
240 /* GPTMR3 base address */
241 #define HPM_GPTMR3_BASE (0xF000C000UL)
242 /* GPTMR3 base pointer */
243 #define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE)
244 /* GPTMR4 base address */
245 #define HPM_GPTMR4_BASE (0xF0010000UL)
246 /* GPTMR4 base pointer */
247 #define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE)
248 /* GPTMR5 base address */
249 #define HPM_GPTMR5_BASE (0xF0014000UL)
250 /* GPTMR5 base pointer */
251 #define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE)
252 /* GPTMR6 base address */
253 #define HPM_GPTMR6_BASE (0xF0018000UL)
254 /* GPTMR6 base pointer */
255 #define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE)
256 /* GPTMR7 base address */
257 #define HPM_GPTMR7_BASE (0xF001C000UL)
258 /* GPTMR7 base pointer */
259 #define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE)
260 /* NTMR0 base address */
261 #define HPM_NTMR0_BASE (0xF1410000UL)
262 /* NTMR0 base pointer */
263 #define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE)
264 /* NTMR1 base address */
265 #define HPM_NTMR1_BASE (0xF1414000UL)
266 /* NTMR1 base pointer */
267 #define HPM_NTMR1 ((GPTMR_Type *) HPM_NTMR1_BASE)
268 /* PTMR base address */
269 #define HPM_PTMR_BASE (0xF4120000UL)
270 /* PTMR base pointer */
271 #define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE)
272 
273 #include "hpm_uart_regs.h"
274 /* Address of UART instances */
275 /* UART0 base address */
276 #define HPM_UART0_BASE (0xF0040000UL)
277 /* UART0 base pointer */
278 #define HPM_UART0 ((UART_Type *) HPM_UART0_BASE)
279 /* UART1 base address */
280 #define HPM_UART1_BASE (0xF0044000UL)
281 /* UART1 base pointer */
282 #define HPM_UART1 ((UART_Type *) HPM_UART1_BASE)
283 /* UART2 base address */
284 #define HPM_UART2_BASE (0xF0048000UL)
285 /* UART2 base pointer */
286 #define HPM_UART2 ((UART_Type *) HPM_UART2_BASE)
287 /* UART3 base address */
288 #define HPM_UART3_BASE (0xF004C000UL)
289 /* UART3 base pointer */
290 #define HPM_UART3 ((UART_Type *) HPM_UART3_BASE)
291 /* UART4 base address */
292 #define HPM_UART4_BASE (0xF0050000UL)
293 /* UART4 base pointer */
294 #define HPM_UART4 ((UART_Type *) HPM_UART4_BASE)
295 /* UART5 base address */
296 #define HPM_UART5_BASE (0xF0054000UL)
297 /* UART5 base pointer */
298 #define HPM_UART5 ((UART_Type *) HPM_UART5_BASE)
299 /* UART6 base address */
300 #define HPM_UART6_BASE (0xF0058000UL)
301 /* UART6 base pointer */
302 #define HPM_UART6 ((UART_Type *) HPM_UART6_BASE)
303 /* UART7 base address */
304 #define HPM_UART7_BASE (0xF005C000UL)
305 /* UART7 base pointer */
306 #define HPM_UART7 ((UART_Type *) HPM_UART7_BASE)
307 /* UART8 base address */
308 #define HPM_UART8_BASE (0xF0180000UL)
309 /* UART8 base pointer */
310 #define HPM_UART8 ((UART_Type *) HPM_UART8_BASE)
311 /* UART9 base address */
312 #define HPM_UART9_BASE (0xF0184000UL)
313 /* UART9 base pointer */
314 #define HPM_UART9 ((UART_Type *) HPM_UART9_BASE)
315 /* UART10 base address */
316 #define HPM_UART10_BASE (0xF0188000UL)
317 /* UART10 base pointer */
318 #define HPM_UART10 ((UART_Type *) HPM_UART10_BASE)
319 /* UART11 base address */
320 #define HPM_UART11_BASE (0xF018C000UL)
321 /* UART11 base pointer */
322 #define HPM_UART11 ((UART_Type *) HPM_UART11_BASE)
323 /* UART12 base address */
324 #define HPM_UART12_BASE (0xF0190000UL)
325 /* UART12 base pointer */
326 #define HPM_UART12 ((UART_Type *) HPM_UART12_BASE)
327 /* UART13 base address */
328 #define HPM_UART13_BASE (0xF0194000UL)
329 /* UART13 base pointer */
330 #define HPM_UART13 ((UART_Type *) HPM_UART13_BASE)
331 /* UART14 base address */
332 #define HPM_UART14_BASE (0xF0198000UL)
333 /* UART14 base pointer */
334 #define HPM_UART14 ((UART_Type *) HPM_UART14_BASE)
335 /* UART15 base address */
336 #define HPM_UART15_BASE (0xF019C000UL)
337 /* UART15 base pointer */
338 #define HPM_UART15 ((UART_Type *) HPM_UART15_BASE)
339 /* PUART base address */
340 #define HPM_PUART_BASE (0xF4124000UL)
341 /* PUART base pointer */
342 #define HPM_PUART ((UART_Type *) HPM_PUART_BASE)
343 
344 #include "hpm_i2c_regs.h"
345 /* Address of I2C instances */
346 /* I2C0 base address */
347 #define HPM_I2C0_BASE (0xF0060000UL)
348 /* I2C0 base pointer */
349 #define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE)
350 /* I2C1 base address */
351 #define HPM_I2C1_BASE (0xF0064000UL)
352 /* I2C1 base pointer */
353 #define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE)
354 /* I2C2 base address */
355 #define HPM_I2C2_BASE (0xF0068000UL)
356 /* I2C2 base pointer */
357 #define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE)
358 /* I2C3 base address */
359 #define HPM_I2C3_BASE (0xF006C000UL)
360 /* I2C3 base pointer */
361 #define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE)
362 /* I2C4 base address */
363 #define HPM_I2C4_BASE (0xF01A0000UL)
364 /* I2C4 base pointer */
365 #define HPM_I2C4 ((I2C_Type *) HPM_I2C4_BASE)
366 /* I2C5 base address */
367 #define HPM_I2C5_BASE (0xF01A4000UL)
368 /* I2C5 base pointer */
369 #define HPM_I2C5 ((I2C_Type *) HPM_I2C5_BASE)
370 /* I2C6 base address */
371 #define HPM_I2C6_BASE (0xF01A8000UL)
372 /* I2C6 base pointer */
373 #define HPM_I2C6 ((I2C_Type *) HPM_I2C6_BASE)
374 /* I2C7 base address */
375 #define HPM_I2C7_BASE (0xF01AC000UL)
376 /* I2C7 base pointer */
377 #define HPM_I2C7 ((I2C_Type *) HPM_I2C7_BASE)
378 
379 #include "hpm_spi_regs.h"
380 /* Address of SPI instances */
381 /* SPI0 base address */
382 #define HPM_SPI0_BASE (0xF0070000UL)
383 /* SPI0 base pointer */
384 #define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE)
385 /* SPI1 base address */
386 #define HPM_SPI1_BASE (0xF0074000UL)
387 /* SPI1 base pointer */
388 #define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE)
389 /* SPI2 base address */
390 #define HPM_SPI2_BASE (0xF0078000UL)
391 /* SPI2 base pointer */
392 #define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE)
393 /* SPI3 base address */
394 #define HPM_SPI3_BASE (0xF007C000UL)
395 /* SPI3 base pointer */
396 #define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE)
397 /* SPI4 base address */
398 #define HPM_SPI4_BASE (0xF01B0000UL)
399 /* SPI4 base pointer */
400 #define HPM_SPI4 ((SPI_Type *) HPM_SPI4_BASE)
401 /* SPI5 base address */
402 #define HPM_SPI5_BASE (0xF01B4000UL)
403 /* SPI5 base pointer */
404 #define HPM_SPI5 ((SPI_Type *) HPM_SPI5_BASE)
405 /* SPI6 base address */
406 #define HPM_SPI6_BASE (0xF01B8000UL)
407 /* SPI6 base pointer */
408 #define HPM_SPI6 ((SPI_Type *) HPM_SPI6_BASE)
409 /* SPI7 base address */
410 #define HPM_SPI7_BASE (0xF01BC000UL)
411 /* SPI7 base pointer */
412 #define HPM_SPI7 ((SPI_Type *) HPM_SPI7_BASE)
413 
414 #include "hpm_crc_regs.h"
415 /* Address of CRC instances */
416 /* CRC base address */
417 #define HPM_CRC_BASE (0xF0080000UL)
418 /* CRC base pointer */
419 #define HPM_CRC ((CRC_Type *) HPM_CRC_BASE)
420 
421 #include "hpm_tsns_regs.h"
422 /* Address of TSNS instances */
423 /* TSNS base address */
424 #define HPM_TSNS_BASE (0xF0090000UL)
425 /* TSNS base pointer */
426 #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE)
427 
428 #include "hpm_mbx_regs.h"
429 /* Address of MBX instances */
430 /* MBX0A base address */
431 #define HPM_MBX0A_BASE (0xF00A0000UL)
432 /* MBX0A base pointer */
433 #define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE)
434 /* MBX0B base address */
435 #define HPM_MBX0B_BASE (0xF00A4000UL)
436 /* MBX0B base pointer */
437 #define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE)
438 /* MBX1A base address */
439 #define HPM_MBX1A_BASE (0xF00A8000UL)
440 /* MBX1A base pointer */
441 #define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE)
442 /* MBX1B base address */
443 #define HPM_MBX1B_BASE (0xF00AC000UL)
444 /* MBX1B base pointer */
445 #define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE)
446 
447 #include "hpm_ewdg_regs.h"
448 /* Address of EWDG instances */
449 /* EWDG0 base address */
450 #define HPM_EWDG0_BASE (0xF00B0000UL)
451 /* EWDG0 base pointer */
452 #define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE)
453 /* EWDG1 base address */
454 #define HPM_EWDG1_BASE (0xF00B4000UL)
455 /* EWDG1 base pointer */
456 #define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE)
457 /* EWDG2 base address */
458 #define HPM_EWDG2_BASE (0xF00B8000UL)
459 /* EWDG2 base pointer */
460 #define HPM_EWDG2 ((EWDG_Type *) HPM_EWDG2_BASE)
461 /* EWDG3 base address */
462 #define HPM_EWDG3_BASE (0xF00BC000UL)
463 /* EWDG3 base pointer */
464 #define HPM_EWDG3 ((EWDG_Type *) HPM_EWDG3_BASE)
465 /* PEWDG base address */
466 #define HPM_PEWDG_BASE (0xF4128000UL)
467 /* PEWDG base pointer */
468 #define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE)
469 
470 #include "hpm_dmamux_regs.h"
471 /* Address of DMAMUX instances */
472 /* DMAMUX base address */
473 #define HPM_DMAMUX_BASE (0xF00C4000UL)
474 /* DMAMUX base pointer */
475 #define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE)
476 
477 #include "hpm_dmav2_regs.h"
478 /* Address of DMAV2 instances */
479 /* HDMA base address */
480 #define HPM_HDMA_BASE (0xF00C8000UL)
481 /* HDMA base pointer */
482 #define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE)
483 /* XDMA base address */
484 #define HPM_XDMA_BASE (0xF3100000UL)
485 /* XDMA base pointer */
486 #define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE)
487 
488 #include "hpm_ppi_regs.h"
489 /* Address of PPI instances */
490 /* PPI base address */
491 #define HPM_PPI_BASE (0xF00CC000UL)
492 /* PPI base pointer */
493 #define HPM_PPI ((PPI_Type *) HPM_PPI_BASE)
494 
495 #include "hpm_gpiom_regs.h"
496 /* Address of GPIOM instances */
497 /* GPIOM base address */
498 #define HPM_GPIOM_BASE (0xF00D8000UL)
499 /* GPIOM base pointer */
500 #define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE)
501 
502 #include "hpm_lobs_regs.h"
503 /* Address of LOBS instances */
504 /* LOBS base address */
505 #define HPM_LOBS_BASE (0xF00DC000UL)
506 /* LOBS base pointer */
507 #define HPM_LOBS ((LOBS_Type *) HPM_LOBS_BASE)
508 
509 #include "hpm_adc16_regs.h"
510 /* Address of ADC16 instances */
511 /* ADC0 base address */
512 #define HPM_ADC0_BASE (0xF0100000UL)
513 /* ADC0 base pointer */
514 #define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE)
515 /* ADC1 base address */
516 #define HPM_ADC1_BASE (0xF0104000UL)
517 /* ADC1 base pointer */
518 #define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE)
519 /* ADC2 base address */
520 #define HPM_ADC2_BASE (0xF0108000UL)
521 /* ADC2 base pointer */
522 #define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE)
523 /* ADC3 base address */
524 #define HPM_ADC3_BASE (0xF010C000UL)
525 /* ADC3 base pointer */
526 #define HPM_ADC3 ((ADC16_Type *) HPM_ADC3_BASE)
527 
528 #include "hpm_acmp_regs.h"
529 /* Address of ACMP instances */
530 /* ACMP0 base address */
531 #define HPM_ACMP0_BASE (0xF0130000UL)
532 /* ACMP0 base pointer */
533 #define HPM_ACMP0 ((ACMP_Type *) HPM_ACMP0_BASE)
534 /* ACMP1 base address */
535 #define HPM_ACMP1_BASE (0xF0134000UL)
536 /* ACMP1 base pointer */
537 #define HPM_ACMP1 ((ACMP_Type *) HPM_ACMP1_BASE)
538 /* ACMP2 base address */
539 #define HPM_ACMP2_BASE (0xF0138000UL)
540 /* ACMP2 base pointer */
541 #define HPM_ACMP2 ((ACMP_Type *) HPM_ACMP2_BASE)
542 /* ACMP3 base address */
543 #define HPM_ACMP3_BASE (0xF013C000UL)
544 /* ACMP3 base pointer */
545 #define HPM_ACMP3 ((ACMP_Type *) HPM_ACMP3_BASE)
546 
547 #include "hpm_i2s_regs.h"
548 /* Address of I2S instances */
549 /* I2S0 base address */
550 #define HPM_I2S0_BASE (0xF0140000UL)
551 /* I2S0 base pointer */
552 #define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE)
553 /* I2S1 base address */
554 #define HPM_I2S1_BASE (0xF0144000UL)
555 /* I2S1 base pointer */
556 #define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE)
557 
558 #include "hpm_dao_regs.h"
559 /* Address of DAO instances */
560 /* DAO base address */
561 #define HPM_DAO_BASE (0xF0150000UL)
562 /* DAO base pointer */
563 #define HPM_DAO ((DAO_Type *) HPM_DAO_BASE)
564 
565 #include "hpm_pdm_regs.h"
566 /* Address of PDM instances */
567 /* PDM base address */
568 #define HPM_PDM_BASE (0xF0154000UL)
569 /* PDM base pointer */
570 #define HPM_PDM ((PDM_Type *) HPM_PDM_BASE)
571 
572 #include "hpm_mcan_regs.h"
573 /* Address of MCAN instances */
574 /* MCAN0 base address */
575 #define HPM_MCAN0_BASE (0xF0300000UL)
576 /* MCAN0 base pointer */
577 #define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE)
578 /* MCAN1 base address */
579 #define HPM_MCAN1_BASE (0xF0304000UL)
580 /* MCAN1 base pointer */
581 #define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE)
582 /* MCAN2 base address */
583 #define HPM_MCAN2_BASE (0xF0308000UL)
584 /* MCAN2 base pointer */
585 #define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE)
586 /* MCAN3 base address */
587 #define HPM_MCAN3_BASE (0xF030C000UL)
588 /* MCAN3 base pointer */
589 #define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE)
590 /* MCAN4 base address */
591 #define HPM_MCAN4_BASE (0xF0310000UL)
592 /* MCAN4 base pointer */
593 #define HPM_MCAN4 ((MCAN_Type *) HPM_MCAN4_BASE)
594 /* MCAN5 base address */
595 #define HPM_MCAN5_BASE (0xF0314000UL)
596 /* MCAN5 base pointer */
597 #define HPM_MCAN5 ((MCAN_Type *) HPM_MCAN5_BASE)
598 /* MCAN6 base address */
599 #define HPM_MCAN6_BASE (0xF0318000UL)
600 /* MCAN6 base pointer */
601 #define HPM_MCAN6 ((MCAN_Type *) HPM_MCAN6_BASE)
602 /* MCAN7 base address */
603 #define HPM_MCAN7_BASE (0xF031C000UL)
604 /* MCAN7 base pointer */
605 #define HPM_MCAN7 ((MCAN_Type *) HPM_MCAN7_BASE)
606 
607 #include "hpm_ptpc_regs.h"
608 /* Address of PTPC instances */
609 /* PTPC base address */
610 #define HPM_PTPC_BASE (0xF037C000UL)
611 /* PTPC base pointer */
612 #define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE)
613 
614 #include "hpm_qeiv2_regs.h"
615 /* Address of QEIV2 instances */
616 /* QEI0 base address */
617 #define HPM_QEI0_BASE (0xF0400000UL)
618 /* QEI0 base pointer */
619 #define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE)
620 /* QEI1 base address */
621 #define HPM_QEI1_BASE (0xF0404000UL)
622 /* QEI1 base pointer */
623 #define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE)
624 /* QEI2 base address */
625 #define HPM_QEI2_BASE (0xF0408000UL)
626 /* QEI2 base pointer */
627 #define HPM_QEI2 ((QEIV2_Type *) HPM_QEI2_BASE)
628 /* QEI3 base address */
629 #define HPM_QEI3_BASE (0xF040C000UL)
630 /* QEI3 base pointer */
631 #define HPM_QEI3 ((QEIV2_Type *) HPM_QEI3_BASE)
632 
633 #include "hpm_qeov2_regs.h"
634 /* Address of QEOV2 instances */
635 /* QEO0 base address */
636 #define HPM_QEO0_BASE (0xF0410000UL)
637 /* QEO0 base pointer */
638 #define HPM_QEO0 ((QEOV2_Type *) HPM_QEO0_BASE)
639 /* QEO1 base address */
640 #define HPM_QEO1_BASE (0xF0414000UL)
641 /* QEO1 base pointer */
642 #define HPM_QEO1 ((QEOV2_Type *) HPM_QEO1_BASE)
643 /* QEO2 base address */
644 #define HPM_QEO2_BASE (0xF0418000UL)
645 /* QEO2 base pointer */
646 #define HPM_QEO2 ((QEOV2_Type *) HPM_QEO2_BASE)
647 /* QEO3 base address */
648 #define HPM_QEO3_BASE (0xF041C000UL)
649 /* QEO3 base pointer */
650 #define HPM_QEO3 ((QEOV2_Type *) HPM_QEO3_BASE)
651 
652 #include "hpm_pwmv2_regs.h"
653 /* Address of PWMV2 instances */
654 /* PWM0 base address */
655 #define HPM_PWM0_BASE (0xF0420000UL)
656 /* PWM0 base pointer */
657 #define HPM_PWM0 ((PWMV2_Type *) HPM_PWM0_BASE)
658 /* PWM1 base address */
659 #define HPM_PWM1_BASE (0xF0424000UL)
660 /* PWM1 base pointer */
661 #define HPM_PWM1 ((PWMV2_Type *) HPM_PWM1_BASE)
662 /* PWM2 base address */
663 #define HPM_PWM2_BASE (0xF0428000UL)
664 /* PWM2 base pointer */
665 #define HPM_PWM2 ((PWMV2_Type *) HPM_PWM2_BASE)
666 /* PWM3 base address */
667 #define HPM_PWM3_BASE (0xF042C000UL)
668 /* PWM3 base pointer */
669 #define HPM_PWM3 ((PWMV2_Type *) HPM_PWM3_BASE)
670 
671 #include "hpm_rdc_regs.h"
672 /* Address of RDC instances */
673 /* RDC0 base address */
674 #define HPM_RDC0_BASE (0xF0440000UL)
675 /* RDC0 base pointer */
676 #define HPM_RDC0 ((RDC_Type *) HPM_RDC0_BASE)
677 /* RDC1 base address */
678 #define HPM_RDC1_BASE (0xF0444000UL)
679 /* RDC1 base pointer */
680 #define HPM_RDC1 ((RDC_Type *) HPM_RDC1_BASE)
681 
682 #include "hpm_sdm_regs.h"
683 /* Address of SDM instances */
684 /* SDM0 base address */
685 #define HPM_SDM0_BASE (0xF0450000UL)
686 /* SDM0 base pointer */
687 #define HPM_SDM0 ((SDM_Type *) HPM_SDM0_BASE)
688 /* SDM1 base address */
689 #define HPM_SDM1_BASE (0xF0454000UL)
690 /* SDM1 base pointer */
691 #define HPM_SDM1 ((SDM_Type *) HPM_SDM1_BASE)
692 
693 #include "hpm_plb_regs.h"
694 /* Address of PLB instances */
695 /* PLB base address */
696 #define HPM_PLB_BASE (0xF0460000UL)
697 /* PLB base pointer */
698 #define HPM_PLB ((PLB_Type *) HPM_PLB_BASE)
699 
700 #include "hpm_synt_regs.h"
701 /* Address of SYNT instances */
702 /* SYNT base address */
703 #define HPM_SYNT_BASE (0xF0464000UL)
704 /* SYNT base pointer */
705 #define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE)
706 
707 #include "hpm_sei_regs.h"
708 /* Address of SEI instances */
709 /* SEI base address */
710 #define HPM_SEI_BASE (0xF0470000UL)
711 /* SEI base pointer */
712 #define HPM_SEI ((SEI_Type *) HPM_SEI_BASE)
713 
714 #include "hpm_trgm_regs.h"
715 /* Address of TRGM instances */
716 /* TRGM0 base address */
717 #define HPM_TRGM0_BASE (0xF047C000UL)
718 /* TRGM0 base pointer */
719 #define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE)
720 
721 #include "hpm_mtg_regs.h"
722 /* Address of MTG instances */
723 /* MTG0 base address */
724 #define HPM_MTG0_BASE (0xF0490000UL)
725 /* MTG0 base pointer */
726 #define HPM_MTG0 ((MTG_Type *) HPM_MTG0_BASE)
727 /* MTG1 base address */
728 #define HPM_MTG1_BASE (0xF0494000UL)
729 /* MTG1 base pointer */
730 #define HPM_MTG1 ((MTG_Type *) HPM_MTG1_BASE)
731 
732 #include "hpm_vsc_regs.h"
733 /* Address of VSC instances */
734 /* VSC0 base address */
735 #define HPM_VSC0_BASE (0xF04A0000UL)
736 /* VSC0 base pointer */
737 #define HPM_VSC0 ((VSC_Type *) HPM_VSC0_BASE)
738 /* VSC1 base address */
739 #define HPM_VSC1_BASE (0xF04A4000UL)
740 /* VSC1 base pointer */
741 #define HPM_VSC1 ((VSC_Type *) HPM_VSC1_BASE)
742 
743 #include "hpm_clc_regs.h"
744 /* Address of CLC instances */
745 /* CLC0 base address */
746 #define HPM_CLC0_BASE (0xF04B0000UL)
747 /* CLC0 base pointer */
748 #define HPM_CLC0 ((CLC_Type *) HPM_CLC0_BASE)
749 /* CLC1 base address */
750 #define HPM_CLC1_BASE (0xF04B4000UL)
751 /* CLC1 base pointer */
752 #define HPM_CLC1 ((CLC_Type *) HPM_CLC1_BASE)
753 
754 #include "hpm_enet_regs.h"
755 /* Address of ENET instances */
756 /* ENET0 base address */
757 #define HPM_ENET0_BASE (0xF1400000UL)
758 /* ENET0 base pointer */
759 #define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE)
760 /* ENET1 base address */
761 #define HPM_ENET1_BASE (0xF1404000UL)
762 /* ENET1 base pointer */
763 #define HPM_ENET1 ((ENET_Type *) HPM_ENET1_BASE)
764 
765 #include "hpm_usb_regs.h"
766 /* Address of USB instances */
767 /* USB0 base address */
768 #define HPM_USB0_BASE (0xF1420000UL)
769 /* USB0 base pointer */
770 #define HPM_USB0 ((USB_Type *) HPM_USB0_BASE)
771 
772 #include "hpm_tsw_regs.h"
773 /* Address of TSW instances */
774 /* TSW base address */
775 #define HPM_TSW_BASE (0xF1600000UL)
776 /* TSW base pointer */
777 #define HPM_TSW ((TSW_Type *) HPM_TSW_BASE)
778 
779 #include "hpm_esc_regs.h"
780 /* Address of ESC instances */
781 /* ESC base address */
782 #define HPM_ESC_BASE (0xF1700000UL)
783 /* ESC base pointer */
784 #define HPM_ESC ((ESC_Type *) HPM_ESC_BASE)
785 
786 #include "hpm_femc_regs.h"
787 /* Address of FEMC instances */
788 /* FEMC base address */
789 #define HPM_FEMC_BASE (0xF300C000UL)
790 /* FEMC base pointer */
791 #define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE)
792 
793 /* Address of ROMC instances */
794 /* ROMC base address */
795 #define HPM_ROMC_BASE (0xF3104000UL)
796 
797 #include "hpm_ffa_regs.h"
798 /* Address of FFA instances */
799 /* FFA base address */
800 #define HPM_FFA_BASE (0xF3108000UL)
801 /* FFA base pointer */
802 #define HPM_FFA ((FFA_Type *) HPM_FFA_BASE)
803 
804 #include "hpm_sdp_regs.h"
805 /* Address of SDP instances */
806 /* SDP base address */
807 #define HPM_SDP_BASE (0xF3140000UL)
808 /* SDP base pointer */
809 #define HPM_SDP ((SDP_Type *) HPM_SDP_BASE)
810 
811 #include "hpm_psec_regs.h"
812 /* Address of PSEC instances */
813 /* PSEC base address */
814 #define HPM_PSEC_BASE (0xF3144000UL)
815 /* PSEC base pointer */
816 #define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE)
817 
818 #include "hpm_pmon_regs.h"
819 /* Address of PMON instances */
820 /* PMON base address */
821 #define HPM_PMON_BASE (0xF3148000UL)
822 /* PMON base pointer */
823 #define HPM_PMON ((PMON_Type *) HPM_PMON_BASE)
824 
825 #include "hpm_rng_regs.h"
826 /* Address of RNG instances */
827 /* RNG base address */
828 #define HPM_RNG_BASE (0xF314C000UL)
829 /* RNG base pointer */
830 #define HPM_RNG ((RNG_Type *) HPM_RNG_BASE)
831 
832 #include "hpm_keym_regs.h"
833 /* Address of KEYM instances */
834 /* KEYM base address */
835 #define HPM_KEYM_BASE (0xF3154000UL)
836 /* KEYM base pointer */
837 #define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE)
838 
839 #include "hpm_otp_regs.h"
840 /* Address of OTP instances */
841 /* OTP base address */
842 #define HPM_OTP_BASE (0xF3158000UL)
843 /* OTP base pointer */
844 #define HPM_OTP ((OTP_Type *) HPM_OTP_BASE)
845 
846 #include "hpm_sysctl_regs.h"
847 /* Address of SYSCTL instances */
848 /* SYSCTL base address */
849 #define HPM_SYSCTL_BASE (0xF4000000UL)
850 /* SYSCTL base pointer */
851 #define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE)
852 
853 #include "hpm_ioc_regs.h"
854 /* Address of IOC instances */
855 /* IOC base address */
856 #define HPM_IOC_BASE (0xF4040000UL)
857 /* IOC base pointer */
858 #define HPM_IOC ((IOC_Type *) HPM_IOC_BASE)
859 /* PIOC base address */
860 #define HPM_PIOC_BASE (0xF4118000UL)
861 /* PIOC base pointer */
862 #define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE)
863 /* BIOC base address */
864 #define HPM_BIOC_BASE (0xF4210000UL)
865 /* BIOC base pointer */
866 #define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE)
867 
868 #include "hpm_pllctlv2_regs.h"
869 /* Address of PLLCTLV2 instances */
870 /* PLLCTLV2 base address */
871 #define HPM_PLLCTLV2_BASE (0xF40C0000UL)
872 /* PLLCTLV2 base pointer */
873 #define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE)
874 
875 #include "hpm_ppor_regs.h"
876 /* Address of PPOR instances */
877 /* PPOR base address */
878 #define HPM_PPOR_BASE (0xF4100000UL)
879 /* PPOR base pointer */
880 #define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE)
881 
882 #include "hpm_pcfg_regs.h"
883 /* Address of PCFG instances */
884 /* PCFG base address */
885 #define HPM_PCFG_BASE (0xF4104000UL)
886 /* PCFG base pointer */
887 #define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE)
888 
889 #include "hpm_pdgo_regs.h"
890 /* Address of PDGO instances */
891 /* PDGO base address */
892 #define HPM_PDGO_BASE (0xF4134000UL)
893 /* PDGO base pointer */
894 #define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE)
895 
896 #include "hpm_pgpr_regs.h"
897 /* Address of PGPR instances */
898 /* PGPR0 base address */
899 #define HPM_PGPR0_BASE (0xF4138000UL)
900 /* PGPR0 base pointer */
901 #define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE)
902 /* PGPR1 base address */
903 #define HPM_PGPR1_BASE (0xF413C000UL)
904 /* PGPR1 base pointer */
905 #define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE)
906 
907 #include "hpm_bacc_regs.h"
908 /* Address of BACC instances */
909 /* BACC base address */
910 #define HPM_BACC_BASE (0xF4200000UL)
911 /* BACC base pointer */
912 #define HPM_BACC ((BACC_Type *) HPM_BACC_BASE)
913 
914 #include "hpm_bpor_regs.h"
915 /* Address of BPOR instances */
916 /* BPOR base address */
917 #define HPM_BPOR_BASE (0xF4204000UL)
918 /* BPOR base pointer */
919 #define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE)
920 
921 #include "hpm_bcfg_regs.h"
922 /* Address of BCFG instances */
923 /* BCFG base address */
924 #define HPM_BCFG_BASE (0xF4208000UL)
925 /* BCFG base pointer */
926 #define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE)
927 
928 #include "hpm_bgpr_regs.h"
929 /* Address of BGPR instances */
930 /* BGPR0 base address */
931 #define HPM_BGPR0_BASE (0xF4218000UL)
932 /* BGPR0 base pointer */
933 #define HPM_BGPR0 ((BGPR_Type *) HPM_BGPR0_BASE)
934 /* BGPR1 base address */
935 #define HPM_BGPR1_BASE (0xF4220000UL)
936 /* BGPR1 base pointer */
937 #define HPM_BGPR1 ((BGPR_Type *) HPM_BGPR1_BASE)
938 
939 #include "hpm_bsec_regs.h"
940 /* Address of BSEC instances */
941 /* BSEC base address */
942 #define HPM_BSEC_BASE (0xF4240000UL)
943 /* BSEC base pointer */
944 #define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE)
945 
946 #include "hpm_rtc_regs.h"
947 /* Address of RTC instances */
948 /* RTC base address */
949 #define HPM_RTC_BASE (0xF4244000UL)
950 /* RTC base pointer */
951 #define HPM_RTC ((RTC_Type *) HPM_RTC_BASE)
952 
953 #include "hpm_bkey_regs.h"
954 /* Address of BKEY instances */
955 /* BKEY base address */
956 #define HPM_BKEY_BASE (0xF4248000UL)
957 /* BKEY base pointer */
958 #define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE)
959 
960 #include "hpm_bmon_regs.h"
961 /* Address of BMON instances */
962 /* BMON base address */
963 #define HPM_BMON_BASE (0xF424C000UL)
964 /* BMON base pointer */
965 #define HPM_BMON ((BMON_Type *) HPM_BMON_BASE)
966 
967 #include "hpm_tamp_regs.h"
968 /* Address of TAMP instances */
969 /* TAMP base address */
970 #define HPM_TAMP_BASE (0xF4250000UL)
971 /* TAMP base pointer */
972 #define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE)
973 
974 #include "hpm_mono_regs.h"
975 /* Address of MONO instances */
976 /* MONO base address */
977 #define HPM_MONO_BASE (0xF4254000UL)
978 /* MONO base pointer */
979 #define HPM_MONO ((MONO_Type *) HPM_MONO_BASE)
980 
981 
982 #include "riscv/riscv_core.h"
983 #include "hpm_csr_regs.h"
984 #include "hpm_interrupt.h"
985 #include "hpm_misc.h"
986 #include "hpm_dmamux_src.h"
987 #include "hpm_trgmmux_src.h"
988 #include "hpm_iomux.h"
989 #include "hpm_pmic_iomux.h"
990 #include "hpm_batt_iomux.h"
991 #endif /* HPM_SOC_H */
992