1 /**
2 * Copyright (c) 2024 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_SYSCTL_DRV_H
9 #define HPM_SYSCTL_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_sysctl_regs.h"
13
14 /**
15 *
16 * @brief SYSCTL driver APIs
17 * @defgroup sysctl_interface SYSCTL driver APIs
18 * @ingroup io_interfaces
19 * @{
20 */
21
22 /**
23 * @brief Retention domains
24 */typedef enum {
25 sysctl_retention_domain_sys = 0,
26 sysctl_retention_domain_cpu0 = 2,
27 sysctl_retention_domain_cpu1 = 4,
28 sysctl_retention_domain_otn = 6,
29 sysctl_retention_domain_xtal24m = 8,
30 sysctl_retention_domain_pll0 = 9,
31 sysctl_retention_domain_pll1 = 10,
32 sysctl_retention_domain_pll2 = 11,
33 } sysctl_retention_domain_t;
34
35 /**
36 * @brief Clock presets
37 */
38 typedef enum {
39 sysctl_preset_0 = 1 << 0,
40 sysctl_preset_1 = 1 << 1,
41 sysctl_preset_2 = 1 << 2,
42 sysctl_preset_3 = 1 << 3,
43 } sysctl_preset_t;
44
45 /**
46 * @brief Reset domains
47 */
48 typedef enum {
49 sysctl_reset_domain_soc = 0,
50 sysctl_reset_domain_cpu0,
51 sysctl_reset_domain_cpu1,
52 sysctl_reset_domain_otn,
53 } sysctl_reset_domain_t;
54
55 /**
56 * @brief Resource
57 */
58 typedef enum {
59 sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0,
60 sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0,
61 sysctl_resource_cpu1 = SYSCTL_RESOURCE_CPU1,
62 sysctl_resource_cpx1 = SYSCTL_RESOURCE_CPX1,
63 sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0,
64 sysctl_resource_pow_cpu1 = SYSCTL_RESOURCE_POW_CPU1,
65 sysctl_resource_pow_otn = SYSCTL_RESOURCE_POW_OTN,
66 sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC,
67 sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0,
68 sysctl_resource_rst_cpu1 = SYSCTL_RESOURCE_RST_CPU1,
69 sysctl_resource_rst_otn = SYSCTL_RESOURCE_RST_OTN,
70 sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL,
71 sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0,
72 sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0,
73 sysctl_resource_clk1_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0,
74 sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1,
75 sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1,
76 sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1,
77 sysctl_resource_clk2_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1,
78 sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2,
79 sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2,
80 sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2,
81 sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF,
82 sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF,
83 sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF,
84
85 sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0,
86 sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0,
87 sysctl_resource_clk_top_cpu1 = SYSCTL_RESOURCE_CLK_TOP_CPU1,
88 sysctl_resource_clk_top_mchtmr1 = SYSCTL_RESOURCE_CLK_TOP_MCT1,
89 sysctl_resource_clk_top_ahb0 = SYSCTL_RESOURCE_CLK_TOP_AHB0,
90 sysctl_resource_clk_top_axif = SYSCTL_RESOURCE_CLK_TOP_AXIF,
91 sysctl_resource_clk_top_axis = SYSCTL_RESOURCE_CLK_TOP_AXIS,
92 sysctl_resource_clk_top_axic = SYSCTL_RESOURCE_CLK_TOP_AXIC,
93 sysctl_resource_clk_top_axin = SYSCTL_RESOURCE_CLK_TOP_AXIN,
94 sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0,
95 sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1,
96 sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2,
97 sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3,
98 sysctl_resource_clk_top_gptmr4 = SYSCTL_RESOURCE_CLK_TOP_TMR4,
99 sysctl_resource_clk_top_gptmr5 = SYSCTL_RESOURCE_CLK_TOP_TMR5,
100 sysctl_resource_clk_top_gptmr6 = SYSCTL_RESOURCE_CLK_TOP_TMR6,
101 sysctl_resource_clk_top_gptmr7 = SYSCTL_RESOURCE_CLK_TOP_TMR7,
102 sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0,
103 sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1,
104 sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2,
105 sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3,
106 sysctl_resource_clk_top_i2c4 = SYSCTL_RESOURCE_CLK_TOP_I2C4,
107 sysctl_resource_clk_top_i2c5 = SYSCTL_RESOURCE_CLK_TOP_I2C5,
108 sysctl_resource_clk_top_i2c6 = SYSCTL_RESOURCE_CLK_TOP_I2C6,
109 sysctl_resource_clk_top_i2c7 = SYSCTL_RESOURCE_CLK_TOP_I2C7,
110 sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0,
111 sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1,
112 sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2,
113 sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3,
114 sysctl_resource_clk_top_spi4 = SYSCTL_RESOURCE_CLK_TOP_SPI4,
115 sysctl_resource_clk_top_spi5 = SYSCTL_RESOURCE_CLK_TOP_SPI5,
116 sysctl_resource_clk_top_spi6 = SYSCTL_RESOURCE_CLK_TOP_SPI6,
117 sysctl_resource_clk_top_spi7 = SYSCTL_RESOURCE_CLK_TOP_SPI7,
118 sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0,
119 sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1,
120 sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2,
121 sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3,
122 sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4,
123 sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5,
124 sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6,
125 sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7,
126 sysctl_resource_clk_top_uart8 = SYSCTL_RESOURCE_CLK_TOP_URT8,
127 sysctl_resource_clk_top_uart9 = SYSCTL_RESOURCE_CLK_TOP_URT9,
128 sysctl_resource_clk_top_uart10 = SYSCTL_RESOURCE_CLK_TOP_URT10,
129 sysctl_resource_clk_top_uart11 = SYSCTL_RESOURCE_CLK_TOP_URT11,
130 sysctl_resource_clk_top_uart12 = SYSCTL_RESOURCE_CLK_TOP_URT12,
131 sysctl_resource_clk_top_uart13 = SYSCTL_RESOURCE_CLK_TOP_URT13,
132 sysctl_resource_clk_top_uart14 = SYSCTL_RESOURCE_CLK_TOP_URT14,
133 sysctl_resource_clk_top_uart15 = SYSCTL_RESOURCE_CLK_TOP_URT15,
134 sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0,
135 sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1,
136 sysctl_resource_clk_top_ana2 = SYSCTL_RESOURCE_CLK_TOP_ANA2,
137 sysctl_resource_clk_top_ana3 = SYSCTL_RESOURCE_CLK_TOP_ANA3,
138 sysctl_resource_clk_top_aud0 = SYSCTL_RESOURCE_CLK_TOP_AUD0,
139 sysctl_resource_clk_top_aud1 = SYSCTL_RESOURCE_CLK_TOP_AUD1,
140 sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0,
141 sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1,
142 sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2,
143 sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3,
144 sysctl_resource_clk_top_can4 = SYSCTL_RESOURCE_CLK_TOP_CAN4,
145 sysctl_resource_clk_top_can5 = SYSCTL_RESOURCE_CLK_TOP_CAN5,
146 sysctl_resource_clk_top_can6 = SYSCTL_RESOURCE_CLK_TOP_CAN6,
147 sysctl_resource_clk_top_can7 = SYSCTL_RESOURCE_CLK_TOP_CAN7,
148 sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0,
149 sysctl_resource_clk_top_femc = SYSCTL_RESOURCE_CLK_TOP_FEMC,
150 sysctl_resource_clk_top_eth0 = SYSCTL_RESOURCE_CLK_TOP_ETH0,
151 sysctl_resource_clk_top_ptp0 = SYSCTL_RESOURCE_CLK_TOP_PTP0,
152 sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0,
153 sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1,
154 sysctl_resource_clk_top_ntm0 = SYSCTL_RESOURCE_CLK_TOP_NTM0,
155 sysctl_resource_clk_top_tsn1 = SYSCTL_RESOURCE_CLK_TOP_TSW1,
156 sysctl_resource_clk_top_tsn2 = SYSCTL_RESOURCE_CLK_TOP_TSW2,
157 sysctl_resource_clk_top_tsn3 = SYSCTL_RESOURCE_CLK_TOP_TSW3,
158 sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0,
159 sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1,
160 sysctl_resource_clk_top_adc2 = SYSCTL_RESOURCE_CLK_TOP_ADC2,
161 sysctl_resource_clk_top_adc3 = SYSCTL_RESOURCE_CLK_TOP_ADC3,
162 sysctl_resource_clk_top_i2s0 = SYSCTL_RESOURCE_CLK_TOP_I2S0,
163 sysctl_resource_clk_top_i2s1 = SYSCTL_RESOURCE_CLK_TOP_I2S1,
164
165 sysctl_resource_linkable_start = 256,
166 sysctl_resource_ahbp = SYSCTL_RESOURCE_AHBP,
167 sysctl_resource_axis = SYSCTL_RESOURCE_AXIS,
168 sysctl_resource_axic = SYSCTL_RESOURCE_AXIC,
169 sysctl_resource_axin = SYSCTL_RESOURCE_AXIN,
170 sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0,
171 sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0,
172 sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0,
173 sysctl_resource_lmm1 = SYSCTL_RESOURCE_LMM1,
174 sysctl_resource_mchtmr1 = SYSCTL_RESOURCE_MCT1,
175 sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0,
176 sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1,
177 sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2,
178 sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3,
179 sysctl_resource_gptmr4 = SYSCTL_RESOURCE_TMR4,
180 sysctl_resource_gptmr5 = SYSCTL_RESOURCE_TMR5,
181 sysctl_resource_gptmr6 = SYSCTL_RESOURCE_TMR6,
182 sysctl_resource_gptmr7 = SYSCTL_RESOURCE_TMR7,
183 sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0,
184 sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1,
185 sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2,
186 sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3,
187 sysctl_resource_i2c4 = SYSCTL_RESOURCE_I2C4,
188 sysctl_resource_i2c5 = SYSCTL_RESOURCE_I2C5,
189 sysctl_resource_i2c6 = SYSCTL_RESOURCE_I2C6,
190 sysctl_resource_i2c7 = SYSCTL_RESOURCE_I2C7,
191 sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0,
192 sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1,
193 sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2,
194 sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3,
195 sysctl_resource_spi4 = SYSCTL_RESOURCE_SPI4,
196 sysctl_resource_spi5 = SYSCTL_RESOURCE_SPI5,
197 sysctl_resource_spi6 = SYSCTL_RESOURCE_SPI6,
198 sysctl_resource_spi7 = SYSCTL_RESOURCE_SPI7,
199 sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0,
200 sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1,
201 sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2,
202 sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3,
203 sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4,
204 sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5,
205 sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6,
206 sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7,
207 sysctl_resource_uart8 = SYSCTL_RESOURCE_URT8,
208 sysctl_resource_uart9 = SYSCTL_RESOURCE_URT9,
209 sysctl_resource_uart10 = SYSCTL_RESOURCE_URT10,
210 sysctl_resource_uart11 = SYSCTL_RESOURCE_URT11,
211 sysctl_resource_uart12 = SYSCTL_RESOURCE_URT12,
212 sysctl_resource_uart13 = SYSCTL_RESOURCE_URT13,
213 sysctl_resource_uart14 = SYSCTL_RESOURCE_URT14,
214 sysctl_resource_uart15 = SYSCTL_RESOURCE_URT15,
215 sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0,
216 sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS,
217 sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0,
218 sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1,
219 sysctl_resource_wdg2 = SYSCTL_RESOURCE_WDG2,
220 sysctl_resource_wdg3 = SYSCTL_RESOURCE_WDG3,
221 sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0,
222 sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1,
223 sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO,
224 sysctl_resource_ppi0 = SYSCTL_RESOURCE_PPI0,
225 sysctl_resource_hdma = SYSCTL_RESOURCE_HDMA,
226 sysctl_resource_lobs = SYSCTL_RESOURCE_LOBS,
227 sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0,
228 sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1,
229 sysctl_resource_adc2 = SYSCTL_RESOURCE_ADC2,
230 sysctl_resource_adc3 = SYSCTL_RESOURCE_ADC3,
231 sysctl_resource_cmp0 = SYSCTL_RESOURCE_CMP0,
232 sysctl_resource_cmp1 = SYSCTL_RESOURCE_CMP1,
233 sysctl_resource_cmp2 = SYSCTL_RESOURCE_CMP2,
234 sysctl_resource_cmp3 = SYSCTL_RESOURCE_CMP3,
235 sysctl_resource_i2s0 = SYSCTL_RESOURCE_I2S0,
236 sysctl_resource_i2s1 = SYSCTL_RESOURCE_I2S1,
237 sysctl_resource_i2spdm0 = SYSCTL_RESOURCE_PDM0,
238 sysctl_resource_i2sdao = SYSCTL_RESOURCE_CLSD,
239 sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0,
240 sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1,
241 sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2,
242 sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3,
243 sysctl_resource_can4 = SYSCTL_RESOURCE_CAN4,
244 sysctl_resource_can5 = SYSCTL_RESOURCE_CAN5,
245 sysctl_resource_can6 = SYSCTL_RESOURCE_CAN6,
246 sysctl_resource_can7 = SYSCTL_RESOURCE_CAN7,
247 sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC,
248 sysctl_resource_qei0 = SYSCTL_RESOURCE_QEI0,
249 sysctl_resource_qei1 = SYSCTL_RESOURCE_QEI1,
250 sysctl_resource_qei2 = SYSCTL_RESOURCE_QEI2,
251 sysctl_resource_qei3 = SYSCTL_RESOURCE_QEI3,
252 sysctl_resource_qeo0 = SYSCTL_RESOURCE_QEO0,
253 sysctl_resource_qeo1 = SYSCTL_RESOURCE_QEO1,
254 sysctl_resource_qeo2 = SYSCTL_RESOURCE_QEO2,
255 sysctl_resource_qeo3 = SYSCTL_RESOURCE_QEO3,
256 sysctl_resource_pwm0 = SYSCTL_RESOURCE_PWM0,
257 sysctl_resource_pwm1 = SYSCTL_RESOURCE_PWM1,
258 sysctl_resource_pwm2 = SYSCTL_RESOURCE_PWM2,
259 sysctl_resource_pwm3 = SYSCTL_RESOURCE_PWM3,
260 sysctl_resource_rdc0 = SYSCTL_RESOURCE_RDC0,
261 sysctl_resource_rdc1 = SYSCTL_RESOURCE_RDC1,
262 sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0,
263 sysctl_resource_sdm1 = SYSCTL_RESOURCE_SDM1,
264 sysctl_resource_plb0 = SYSCTL_RESOURCE_PLB0,
265 sysctl_resource_sei0 = SYSCTL_RESOURCE_SEI0,
266 sysctl_resource_mtg0 = SYSCTL_RESOURCE_MTG0,
267 sysctl_resource_mtg1 = SYSCTL_RESOURCE_MTG1,
268 sysctl_resource_vsc0 = SYSCTL_RESOURCE_VSC0,
269 sysctl_resource_vsc1 = SYSCTL_RESOURCE_VSC1,
270 sysctl_resource_clc0 = SYSCTL_RESOURCE_CLC0,
271 sysctl_resource_clc1 = SYSCTL_RESOURCE_CLC1,
272 sysctl_resource_emds = SYSCTL_RESOURCE_EMDS,
273 sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0,
274 sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0,
275 sysctl_resource_pka0 = SYSCTL_RESOURCE_PKA0,
276 sysctl_resource_kman = SYSCTL_RESOURCE_KMAN,
277 sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0,
278 sysctl_resource_femc = SYSCTL_RESOURCE_FEMC,
279 sysctl_resource_ram0 = SYSCTL_RESOURCE_RAM0,
280 sysctl_resource_ram1 = SYSCTL_RESOURCE_RAM1,
281 sysctl_resource_xdma = SYSCTL_RESOURCE_XDMA,
282 sysctl_resource_ffa0 = SYSCTL_RESOURCE_FFA0,
283 sysctl_resource_eth0 = SYSCTL_RESOURCE_ETH0,
284 sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0,
285 sysctl_resource_ntmr0 = SYSCTL_RESOURCE_NTM0,
286 sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0,
287 sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1,
288 sysctl_resource_tsn0 = SYSCTL_RESOURCE_TSW0,
289 sysctl_resource_esc0 = SYSCTL_RESOURCE_ESC0,
290 sysctl_resource_linkable_end,
291 sysctl_resource_end = sysctl_resource_linkable_end,
292 } sysctl_resource_t;
293
294 /**
295 * @brief Resource modes
296 */
297 typedef enum {
298 sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */
299 sysctl_resource_mode_force_on, /*!< Force the resource clock on */
300 sysctl_resource_mode_force_off, /*!< Force the resource clock off */
301 } sysctl_resource_mode_t;
302
303 /**
304 * @brief Clock nodes
305 */
306 typedef enum {
307 clock_node_cpu0 = SYSCTL_CLOCK_CLK_TOP_CPU0,
308 clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0,
309 clock_node_cpu1 = SYSCTL_CLOCK_CLK_TOP_CPU1,
310 clock_node_mchtmr1 = SYSCTL_CLOCK_CLK_TOP_MCT1,
311 clock_node_ahb0 = SYSCTL_CLOCK_CLK_TOP_AHB0,
312 clock_node_axif = SYSCTL_CLOCK_CLK_TOP_AXIF,
313 clock_node_axis = SYSCTL_CLOCK_CLK_TOP_AXIS,
314 clock_node_axic = SYSCTL_CLOCK_CLK_TOP_AXIC,
315 clock_node_axin = SYSCTL_CLOCK_CLK_TOP_AXIN,
316 clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0,
317 clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1,
318 clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2,
319 clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3,
320 clock_node_gptmr4 = SYSCTL_CLOCK_CLK_TOP_TMR4,
321 clock_node_gptmr5 = SYSCTL_CLOCK_CLK_TOP_TMR5,
322 clock_node_gptmr6 = SYSCTL_CLOCK_CLK_TOP_TMR6,
323 clock_node_gptmr7 = SYSCTL_CLOCK_CLK_TOP_TMR7,
324 clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0,
325 clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1,
326 clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2,
327 clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3,
328 clock_node_i2c4 = SYSCTL_CLOCK_CLK_TOP_I2C4,
329 clock_node_i2c5 = SYSCTL_CLOCK_CLK_TOP_I2C5,
330 clock_node_i2c6 = SYSCTL_CLOCK_CLK_TOP_I2C6,
331 clock_node_i2c7 = SYSCTL_CLOCK_CLK_TOP_I2C7,
332 clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0,
333 clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1,
334 clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2,
335 clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3,
336 clock_node_spi4 = SYSCTL_CLOCK_CLK_TOP_SPI4,
337 clock_node_spi5 = SYSCTL_CLOCK_CLK_TOP_SPI5,
338 clock_node_spi6 = SYSCTL_CLOCK_CLK_TOP_SPI6,
339 clock_node_spi7 = SYSCTL_CLOCK_CLK_TOP_SPI7,
340 clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0,
341 clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1,
342 clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2,
343 clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3,
344 clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4,
345 clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5,
346 clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6,
347 clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7,
348 clock_node_uart8 = SYSCTL_CLOCK_CLK_TOP_URT8,
349 clock_node_uart9 = SYSCTL_CLOCK_CLK_TOP_URT9,
350 clock_node_uart10 = SYSCTL_CLOCK_CLK_TOP_URT10,
351 clock_node_uart11 = SYSCTL_CLOCK_CLK_TOP_URT11,
352 clock_node_uart12 = SYSCTL_CLOCK_CLK_TOP_URT12,
353 clock_node_uart13 = SYSCTL_CLOCK_CLK_TOP_URT13,
354 clock_node_uart14 = SYSCTL_CLOCK_CLK_TOP_URT14,
355 clock_node_uart15 = SYSCTL_CLOCK_CLK_TOP_URT15,
356 clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0,
357 clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1,
358 clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2,
359 clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3,
360 clock_node_aud0 = SYSCTL_CLOCK_CLK_TOP_AUD0,
361 clock_node_aud1 = SYSCTL_CLOCK_CLK_TOP_AUD1,
362 clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0,
363 clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1,
364 clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2,
365 clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3,
366 clock_node_can4 = SYSCTL_CLOCK_CLK_TOP_CAN4,
367 clock_node_can5 = SYSCTL_CLOCK_CLK_TOP_CAN5,
368 clock_node_can6 = SYSCTL_CLOCK_CLK_TOP_CAN6,
369 clock_node_can7 = SYSCTL_CLOCK_CLK_TOP_CAN7,
370 clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0,
371 clock_node_femc = SYSCTL_CLOCK_CLK_TOP_FEMC,
372 clock_node_eth0 = SYSCTL_CLOCK_CLK_TOP_ETH0,
373 clock_node_ptp0 = SYSCTL_CLOCK_CLK_TOP_PTP0,
374 clock_node_ntmr0 = SYSCTL_CLOCK_CLK_TOP_NTM0,
375 clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0,
376 clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1,
377 clock_node_tsn1 = SYSCTL_CLOCK_CLK_TOP_TSW1,
378 clock_node_tsn2 = SYSCTL_CLOCK_CLK_TOP_TSW2,
379 clock_node_tsn3 = SYSCTL_CLOCK_CLK_TOP_TSW3,
380
381 clock_node_adc_start,
382 clock_node_adc0 = clock_node_adc_start,
383 clock_node_adc1,
384 clock_node_adc2,
385 clock_node_adc3,
386
387 clock_node_i2s_start,
388 clock_node_i2s0 = clock_node_i2s_start,
389 clock_node_i2s1,
390 clock_node_end,
391 } clock_node_t;
392
393 /**
394 * @brief General clock sources
395 */
396 typedef enum {
397 clock_source_osc0_clk0 = 0,
398 clock_source_pll0_clk0 = 1,
399 clock_source_pll0_clk1 = 2,
400 clock_source_pll1_clk0 = 3,
401 clock_source_pll1_clk1 = 4,
402 clock_source_pll1_clk2 = 5,
403 clock_source_pll2_clk0 = 6,
404 clock_source_pll2_clk1 = 7,
405 clock_source_general_source_end,
406 } clock_source_t;
407
408 /**
409 * @brief ADC clock sources
410 */
411 typedef enum {
412 clock_source_adc_ana_clock = 0,
413 clock_source_adc_ahb_clock = 1,
414 clock_source_adc_clk_end,
415 } clock_source_adc_t;
416
417 /**
418 * @brief I2S clock sources
419 */
420 typedef enum {
421 clock_source_i2s_audn_clock = 0,
422 clock_source_i2s_audx_clock = 1,
423 clock_source_i2s_clk_end,
424 } clock_source_i2s_t;
425
426 /**
427 * @brief CPU low power mode
428 */
429 typedef enum {
430 cpu_lp_mode_gate_cpu_clock = 0,
431 cpu_lp_mode_trigger_system_lp = 0x1,
432 cpu_lp_mode_ungate_cpu_clock = 0x2,
433 } cpu_lp_mode_t;
434
435 /**
436 * @brief Monitor targets
437 */
438 /* Monitor Target types */
439 typedef enum {
440 monitor_target_clk_32k_batt = 0,
441 monitor_target_clk_32k_pmic = 1,
442 monitor_target_clk_irc24m = 2,
443 monitor_target_clk_xtal_24m = 3,
444 monitor_target_clk_usb0_phy = 4,
445 monitor_target_clk0_osc0 = 20,
446 monitor_target_clk0_pll0 = 21,
447 monitor_target_clk1_pll0 = 22,
448 monitor_target_clk0_pll1 = 23,
449 monitor_target_clk1_pll1 = 24,
450 monitor_target_clk2_pll1 = 25,
451 monitor_target_clk0_pll2 = 26,
452 monitor_target_clk1_pll2 = 27,
453 monitor_target_clk_top_cpu0 = 128,
454 monitor_target_clk_top_mchtmr0 = 129,
455 monitor_target_clk_top_cpu1 = 130,
456 monitor_target_clk_top_mchtmr1 = 131,
457 monitor_target_clk_top_axif = 132,
458 monitor_target_clk_top_axis = 133,
459 monitor_target_clk_top_axic = 134,
460 monitor_target_clk_top_axin = 135,
461 monitor_target_clk_top_ahb0 = 136,
462 monitor_target_clk_top_gptmr0 = 137,
463 monitor_target_clk_top_gptmr1 = 138,
464 monitor_target_clk_top_gptmr2 = 139,
465 monitor_target_clk_top_gptmr3 = 140,
466 monitor_target_clk_top_gptmr4 = 141,
467 monitor_target_clk_top_gptmr5 = 142,
468 monitor_target_clk_top_gptmr6 = 143,
469 monitor_target_clk_top_gptmr7 = 144,
470 monitor_target_clk_top_i2c0 = 145,
471 monitor_target_clk_top_i2c1 = 146,
472 monitor_target_clk_top_i2c2 = 147,
473 monitor_target_clk_top_i2c3 = 148,
474 monitor_target_clk_top_i2c4 = 149,
475 monitor_target_clk_top_i2c5 = 150,
476 monitor_target_clk_top_i2c6 = 151,
477 monitor_target_clk_top_i2c7 = 152,
478 monitor_target_clk_top_spi0 = 153,
479 monitor_target_clk_top_spi1 = 154,
480 monitor_target_clk_top_spi2 = 155,
481 monitor_target_clk_top_spi3 = 156,
482 monitor_target_clk_top_spi4 = 157,
483 monitor_target_clk_top_spi5 = 158,
484 monitor_target_clk_top_spi6 = 159,
485 monitor_target_clk_top_spi7 = 160,
486 monitor_target_clk_top_uart0 = 161,
487 monitor_target_clk_top_uart1 = 162,
488 monitor_target_clk_top_uart2 = 163,
489 monitor_target_clk_top_uart3 = 164,
490 monitor_target_clk_top_uart4 = 165,
491 monitor_target_clk_top_uart5 = 166,
492 monitor_target_clk_top_uart6 = 167,
493 monitor_target_clk_top_uart7 = 168,
494 monitor_target_clk_top_uart8 = 169,
495 monitor_target_clk_top_uart9 = 170,
496 monitor_target_clk_top_uart10 = 171,
497 monitor_target_clk_top_uart11 = 172,
498 monitor_target_clk_top_uart12 = 173,
499 monitor_target_clk_top_uart13 = 174,
500 monitor_target_clk_top_uart14 = 175,
501 monitor_target_clk_top_uart15 = 176,
502 monitor_target_clk_top_can0 = 177,
503 monitor_target_clk_top_can1 = 178,
504 monitor_target_clk_top_can2 = 179,
505 monitor_target_clk_top_can3 = 180,
506 monitor_target_clk_top_can4 = 181,
507 monitor_target_clk_top_can5 = 182,
508 monitor_target_clk_top_can6 = 183,
509 monitor_target_clk_top_can7 = 184,
510 monitor_target_clk_top_xpi0 = 185,
511 monitor_target_clk_top_femc = 186,
512 monitor_target_clk_top_ana0 = 187,
513 monitor_target_clk_top_ana1 = 188,
514 monitor_target_clk_top_ana2 = 189,
515 monitor_target_clk_top_ana3 = 190,
516 monitor_target_clk_top_aud0 = 191,
517 monitor_target_clk_top_aud1 = 192,
518 monitor_target_clk_top_eth0 = 193,
519 monitor_target_clk_top_ptp0 = 194,
520 monitor_target_clk_top_ref0 = 195,
521 monitor_target_clk_top_ref1 = 196,
522 monitor_target_clk_top_ntmr0 = 197,
523 monitor_target_clk_top_tsn1 = 198,
524 monitor_target_clk_top_tsn2 = 199,
525 monitor_target_clk_top_tsn3 = 200,
526 } monitor_target_t;
527
528 /**
529 * @brief Monitor work mode
530 */
531 typedef enum {
532 monitor_work_mode_compare = 0,
533 monitor_work_mode_record = 1,
534 } monitor_work_mode_t;
535
536 /**
537 * @brief Monitor accuracy
538 */
539 typedef enum {
540 monitor_accuracy_1khz = 0,
541 monitor_accuracy_1hz = 1,
542 } monitor_accuracy_t;
543
544 /**
545 * @brief Monitor reference clock source
546 */
547 typedef enum {
548 monitor_reference_32khz = 0,
549 monitor_reference_24mhz = 1,
550 } monitor_reference_t;
551
552 typedef enum {
553 cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK,
554 cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK,
555 cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK,
556 cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK,
557 } cpu_event_flag_mask_t;
558
559 /**
560 * @brief Monitor config
561 */
562 typedef struct monitor_config {
563 uint8_t divide_by; /**< Divider to be used for OBS output to pads */
564 monitor_work_mode_t mode; /**< Monitor work mode */
565 monitor_accuracy_t accuracy; /**< Monitor reference accuracy */
566 monitor_reference_t reference; /**< Monitor reference clock source */
567 monitor_target_t target; /**< Monitor target */
568 bool start_measure; /**< Start flag */
569 bool enable_output; /**< Enable output to pads if true */
570 uint32_t high_limit; /**< Maximum frequency at compare mode */
571 uint32_t low_limit; /**< Minimum frequency at compare mode */
572 } monitor_config_t;
573
574 #ifdef __cplusplus
575 extern "C" {
576 #endif
577
578 /**
579 * @brief Check if monitor result is valid
580 *
581 * @param[in] ptr SYSCTL_Type base address
582 * @param[in] monitor_index specific monitor instance to be used
583 *
584 * @return true if it is valid
585 */
sysctl_monitor_result_is_valid(SYSCTL_Type * ptr,uint8_t monitor_index)586 static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index)
587 {
588 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL);
589 }
590
591 /**
592 * @brief Get target monitor instance result
593 *
594 * @param[in] ptr SYSCTL_Type base address
595 * @param[in] monitor_index specific monitor instance to be used
596 * @return value of monitor result measured
597 */
sysctl_monitor_get_current_result(SYSCTL_Type * ptr,uint8_t monitor_index)598 static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index)
599 {
600 while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) {
601 }
602 return ptr->MONITOR[monitor_index].CURRENT;
603 }
604
605 /**
606 * @brief Set work mode for target monitor instance
607 *
608 * @param[in] ptr SYSCTL_Type base address
609 * @param[in] monitor_index specific monitor instance to be used
610 * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record
611 */
sysctl_monitor_set_work_mode(SYSCTL_Type * ptr,uint8_t monitor_index,monitor_work_mode_t mode)612 static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode)
613 {
614 ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) |
615 (SYSCTL_MONITOR_CONTROL_MODE_SET(mode));
616 }
617
618 /**
619 * @brief Set minimum frequency for target monitor instance
620 *
621 * @param[in] ptr SYSCTL_Type base address
622 * @param[in] monitor_index specific monitor instance to be used
623 * @param[in] limit measurement low limit
624 */
sysctl_monitor_set_limit_low(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)625 static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit)
626 {
627 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
628 return status_invalid_argument;
629 }
630 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit);
631 return status_success;
632 }
633
634 /**
635 * @brief Set maximum frequency for target monitor instance
636 *
637 * @param[in] ptr SYSCTL_Type base address
638 * @param[in] monitor_index specific monitor instance to be used
639 * @param[in] limit measurement high limit
640 */
sysctl_monitor_set_limit_high(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)641 static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit)
642 {
643 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
644 return status_invalid_argument;
645 }
646 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit);
647 return status_success;
648 }
649
650 /**
651 * @brief Set frequency limit for target monitor instance
652 *
653 * @param[in] ptr SYSCTL_Type base address
654 * @param[in] monitor_index specific monitor instance to be used
655 * @param[in] limit_high measurement high limit
656 * @param[in] limit_low measurement low limit
657 */
sysctl_monitor_set_limit(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit_high,uint32_t limit_low)658 static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr,
659 uint8_t monitor_index,
660 uint32_t limit_high,
661 uint32_t limit_low)
662 {
663 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
664 return status_invalid_argument;
665 }
666 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high);
667 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low);
668 return status_success;
669 }
670
671 /**
672 * @brief Get maximum frequency for target monitor instance
673 *
674 * @param[in] ptr SYSCTL_Type base address
675 * @param[in] monitor_index specific monitor instance to be used
676 * @return current high limit value
677 */
sysctl_monitor_get_limit_high(SYSCTL_Type * ptr,uint32_t monitor_index)678 static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index)
679 {
680 return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT);
681 }
682
683 /**
684 * @brief Get minimum frequency for target monitor instance
685 *
686 * @param[in] ptr SYSCTL_Type base address
687 * @param[in] monitor_index specific monitor instance to be used
688 * @return current low limit value
689 */
sysctl_monitor_get_limit_low(SYSCTL_Type * ptr,uint32_t monitor_index)690 static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index)
691 {
692 return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT);
693 }
694
695 /**
696 * @brief Measure specific target frequency
697 *
698 * @param[in] ptr SYSCTL_Type base address
699 * @param[in] monitor_index specific monitor instance to be used
700 * @param[in] target monitor target to be measured
701 * @param[in] enable_output enable clock obs output
702 * @return frequency of monitor target measured
703 */
704 uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr,
705 uint8_t monitor_index,
706 monitor_target_t target,
707 bool enable_output);
708
709 /**
710 * @brief Link current CPU core its own group
711 *
712 * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode
713 *
714 * @param[in] ptr SYSCTL_Type base address
715 * @param[in] cpu_index cpu index to enable its own affiliated group
716 */
sysctl_set_enable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)717 static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
718 {
719 ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index;
720 }
721
722 /**
723 * @brief Unlink current CPU core with its own group
724 *
725 * @param[in] ptr SYSCTL_Type base address
726 * @param[in] cpu_index cpu index to enable its own affiliated group
727 */
sysctl_set_disable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)728 static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
729 {
730 ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index;
731 }
732
733 /**
734 * @brief Check if any resource is busy
735 *
736 * @param[in] ptr SYSCTL_Type base address
737 * @return true if any resource is busy
738 */
sysctl_resource_any_is_busy(SYSCTL_Type * ptr)739 static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr)
740 {
741 return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK;
742 }
743
744 /**
745 * @brief Check if specific target is busy
746 *
747 * @param[in] ptr SYSCTL_Type base address
748 * @param[in] resource target resource index
749 * @return true if target resource is busy
750 */
sysctl_resource_target_is_busy(SYSCTL_Type * ptr,sysctl_resource_t resource)751 static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource)
752 {
753 return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK;
754 }
755
756 /**
757 * @brief Set target mode
758 *
759 * @param[in] ptr SYSCTL_Type base address
760 * @param[in] resource target resource index
761 * @param[in] mode target resource mode
762 */
sysctl_resource_target_set_mode(SYSCTL_Type * ptr,sysctl_resource_t resource,sysctl_resource_mode_t mode)763 static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr,
764 sysctl_resource_t resource,
765 sysctl_resource_mode_t mode)
766 {
767 ptr->RESOURCE[resource] =
768 (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) |
769 SYSCTL_RESOURCE_MODE_SET(mode);
770 }
771
772 /**
773 * @brief Get target mode
774 *
775 * @param[in] ptr SYSCTL_Type base address
776 * @param[in] resource target resource index
777 * @return target resource mode
778 */
sysctl_resource_target_get_mode(SYSCTL_Type * ptr,sysctl_resource_t resource)779 static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr,
780 sysctl_resource_t resource)
781 {
782 return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]);
783 }
784
785 /**
786 * @brief Disable resource retention when specific CPU enters stop mode
787 *
788 * @param[in] ptr SYSCTL_Type base address
789 * @param[in] cpu_index cpu index
790 * @param[in] mask bit mask to clear
791 */
sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)792 static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask)
793 {
794 ptr->RETENTION[cpu_index].CLEAR = mask;
795 }
796
797 /**
798 * @brief Disable resource retention when CPU0 enters stop mode
799 *
800 * @param[in] ptr SYSCTL_Type base address
801 * @param[in] mask bit mask to clear
802 */
sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)803 static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
804 {
805 sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask);
806 }
807
808 /**
809 * @brief Disable resource retention when CPU1 enters stop mode
810 *
811 * @param[in] ptr SYSCTL_Type base address
812 * @param[in] mask bit mask to clear
813 */
sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)814 static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
815 {
816 sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask);
817 }
818
819 /**
820 * @brief Enable resource retention when specific CPU enters stop mode
821 *
822 * @param[in] ptr SYSCTL_Type base address
823 * @param[in] cpu_index cpu index
824 * @param[in] mask bit mask to set
825 */
sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)826 static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask)
827 {
828 ptr->RETENTION[cpu_index].SET = mask;
829 }
830
831 /**
832 * @brief Enable resource retention when CPU0 enters stop mode
833 *
834 * @param[in] ptr SYSCTL_Type base address
835 * @param[in] mask bit mask to set
836 */
sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)837 static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
838 {
839 sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask);
840 }
841
842 /**
843 * @brief Enable resource retention when CPU1 enters stop mode
844 *
845 * @param[in] ptr SYSCTL_Type base address
846 * @param[in] mask bit mask to set
847 */
sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)848 static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
849 {
850 sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask);
851 }
852
853 /**
854 * @brief Enable resource retention when specific CPU enters stop mode
855 *
856 * @param[in] ptr SYSCTL_Type base address
857 * @param[in] cpu_index cpu index
858 * @param[in] value value to be set
859 */
sysctl_set_cpu_lp_retention(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t value)860 static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value)
861 {
862 ptr->RETENTION[cpu_index].VALUE = value;
863 }
864
865 /**
866 * @brief Enable resource retention when CPU0 enters stop mode
867 *
868 * @param[in] ptr SYSCTL_Type base address
869 * @param[in] value value to be set
870 */
sysctl_set_cpu0_lp_retention(SYSCTL_Type * ptr,uint32_t value)871 static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value)
872 {
873 sysctl_set_cpu_lp_retention(ptr, 0, value);
874 }
875
876 /**
877 * @brief Enable resource retention when CPU1 enters stop mode
878 *
879 * @param[in] ptr SYSCTL_Type base address
880 * @param[in] value value to be set
881 */
sysctl_set_cpu1_lp_retention(SYSCTL_Type * ptr,uint32_t value)882 static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value)
883 {
884 sysctl_set_cpu_lp_retention(ptr, 1, value);
885 }
886
887 /**
888 * @brief Retain target domain for specific CPU
889 *
890 * @param[in] ptr SYSCTL_Type base address
891 * @param[in] cpu_index CPU index
892 * @param[in] domain target domain power to be retained
893 * @param[in] retain_mem set true to retain memory/register of target domain
894 */
sysctl_set_cpu_lp_retain_domain(SYSCTL_Type * ptr,uint8_t cpu_index,sysctl_retention_domain_t domain,bool retain_mem)895 static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr,
896 uint8_t cpu_index,
897 sysctl_retention_domain_t domain,
898 bool retain_mem)
899 {
900 uint8_t set_mask = 0x1;
901 if (domain < sysctl_retention_domain_xtal24m) {
902 set_mask = retain_mem ? 0x3 : 0x1;
903 }
904 ptr->RETENTION[cpu_index].SET = (set_mask << domain);
905 }
906
907 /**
908 * @brief Retain target domain for specific CPU0
909 *
910 * @param[in] ptr SYSCTL_Type base address
911 * @param[in] domain target domain power to be retained
912 * @param[in] retain_mem set true to retain memory/register of target domain
913 */
sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type * ptr,sysctl_retention_domain_t domain,bool retain_mem)914 static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr,
915 sysctl_retention_domain_t domain,
916 bool retain_mem)
917 {
918 sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem);
919 }
920
921 /**
922 * @brief Retain target domain for specific CPU
923 *
924 * @param[in] ptr SYSCTL_Type base address
925 * @param[in] domain target domain power to be retained
926 * @param[in] retain_mem set true to retain memory/register of target domain
927 */
sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type * ptr,sysctl_retention_domain_t domain,bool retain_mem)928 static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr,
929 sysctl_retention_domain_t domain,
930 bool retain_mem)
931 {
932 sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem);
933 }
934
935 /**
936 * @brief Check if any clock is busy
937 *
938 * @param[in] ptr SYSCTL_Type base address
939 * @return true if any clock is busy
940 */
sysctl_clock_any_is_busy(SYSCTL_Type * ptr)941 static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr)
942 {
943 return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK;
944 }
945
946 /**
947 * @brief Check if target clock is busy
948 *
949 * @param[in] ptr SYSCTL_Type base address
950 * @param[in] clock target clock
951 * @return true if target clock is busy
952 */
sysctl_clock_target_is_busy(SYSCTL_Type * ptr,uint32_t clock)953 static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock)
954 {
955 return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK;
956 }
957
958 /**
959 * @brief Preserve clock setting for certain node
960 *
961 * @param[in] ptr SYSCTL_Type base address
962 * @param[in] clock target clock
963 */
sysctl_clock_preserve_settings(SYSCTL_Type * ptr,clock_node_t clock)964 static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock)
965 {
966 ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK;
967 }
968
969 /**
970 * @brief Unpreserve clock setting for certain node
971 *
972 * @param[in] ptr SYSCTL_Type base address
973 * @param[in] clock target clock
974 */
sysctl_clock_unpreserve_settings(SYSCTL_Type * ptr,clock_node_t clock)975 static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock)
976 {
977 ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK;
978 }
979
980 /**
981 * @brief Set clock preset
982 *
983 * @param[in] ptr SYSCTL_Type base address
984 * @param[in] preset preset
985 */
sysctl_clock_set_preset(SYSCTL_Type * ptr,sysctl_preset_t preset)986 static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset)
987 {
988 ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset);
989 }
990
991 /**
992 * @brief Check if target reset domain wakeup status
993 *
994 * @param[in] ptr SYSCTL_Type base address
995 * @param[in] domain target domain to be checked
996 * @return true if target domain was taken wakeup reset
997 */
sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)998 static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
999 {
1000 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
1001 }
1002
1003 /**
1004 * @brief Clear target reset domain wakeup status
1005 *
1006 * @param[in] ptr SYSCTL_Type base address
1007 * @param[in] domain target domain to be checked
1008 */
sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)1009 static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
1010 {
1011 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
1012 }
1013
1014 /**
1015 * @brief Clear target reset domain reset status
1016 *
1017 * @param[in] ptr SYSCTL_Type base address
1018 * @param[in] domain target domain to be checked
1019 * @return true if target domain was taken reset
1020 */
sysctl_reset_check_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)1021 static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
1022 {
1023 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK;
1024 }
1025
1026 /**
1027 * @brief Clear target reset domain reset status
1028 *
1029 * @param[in] ptr SYSCTL_Type base address
1030 * @param[in] domain target domain to be checked
1031 */
sysctl_reset_clear_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)1032 static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
1033 {
1034 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK;
1035 }
1036
1037 /**
1038 * @brief Clear target reset domain for all reset status
1039 *
1040 * @param[in] ptr SYSCTL_Type base address
1041 * @param[in] domain target domain to be checked
1042 */
sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)1043 static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
1044 {
1045 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
1046 }
1047
1048 /**
1049 * @brief Get target CPU wakeup source status
1050 *
1051 * @param[in] ptr SYSCTL_Type base address
1052 * @param[in] cpu_index CPU index
1053 * @param[in] status_index wakeup status index 0 - 7
1054 * @return wakeup source status mask
1055 */
sysctl_get_wakeup_source_status(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index)1056 static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index)
1057 {
1058 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index];
1059 }
1060
1061 /**
1062 * @brief Get target CPU0 wakeup source status
1063 *
1064 * @param[in] ptr SYSCTL_Type base address
1065 * @param[in] status_index wakeup status index 0 - 7
1066 * @return wakeup source status mask
1067 */
sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type * ptr,uint8_t status_index)1068 static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index)
1069 {
1070 return sysctl_get_wakeup_source_status(ptr, 0, status_index);
1071 }
1072
1073 /**
1074 * @brief Get target CPU1 wakeup source status
1075 *
1076 * @param[in] ptr SYSCTL_Type base address
1077 * @param[in] status_index wakeup status index 0 - 7
1078 * @return wakeup source status mask
1079 */
sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type * ptr,uint8_t status_index)1080 static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index)
1081 {
1082 return sysctl_get_wakeup_source_status(ptr, 1, status_index);
1083 }
1084
1085 /**
1086 * @brief Check wakeup source status with mask
1087 *
1088 * @param[in] ptr SYSCTL_Type base address
1089 * @param[in] cpu_index CPU index
1090 * @param[in] status_index wakeup status index 0 - 7
1091 * @param[in] mask expected status mask
1092 * @return wakeup status according to given bit mask
1093 */
sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index,uint32_t mask)1094 static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
1095 uint8_t cpu_index,
1096 uint8_t status_index,
1097 uint32_t mask)
1098 {
1099 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask;
1100 }
1101
1102 /**
1103 * @brief Check CPU0 wakeup source status with mask
1104 *
1105 * @param[in] ptr SYSCTL_Type base address
1106 * @param[in] status_index wakeup status index 0 - 7
1107 * @param[in] mask expected status mask
1108 * @return wakeup status according to given bit mask
1109 */
sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t status_index,uint32_t mask)1110 static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
1111 uint8_t status_index,
1112 uint32_t mask)
1113 {
1114 return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask);
1115 }
1116
1117 /**
1118 * @brief Check CPU1 wakeup source status with mask
1119 *
1120 * @param[in] ptr SYSCTL_Type base address
1121 * @param[in] status_index wakeup status index 0 - 7
1122 * @param[in] mask expected status mask
1123 * @return wakeup status according to given bit mask
1124 */
sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t status_index,uint32_t mask)1125 static inline uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
1126 uint8_t status_index,
1127 uint32_t mask)
1128 {
1129 return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask);
1130 }
1131
1132 /**
1133 * @brief Enable wakeup source status with mask
1134 *
1135 * @param[in] ptr SYSCTL_Type base address
1136 * @param[in] cpu_index CPU index
1137 * @param[in] enable_index wakeup enable index 0 - 7
1138 * @param[in] mask expected status mask
1139 */
sysctl_enable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)1140 static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr,
1141 uint8_t cpu_index,
1142 uint8_t enable_index,
1143 uint32_t mask)
1144 {
1145 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask;
1146 }
1147
1148 /**
1149 * @brief Enable CPU0 wakeup source status with mask
1150 *
1151 * @param[in] ptr SYSCTL_Type base address
1152 * @param[in] enable_index wakeup enable index 0 - 7
1153 * @param[in] mask expected status mask
1154 */
sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1155 static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr,
1156 uint8_t enable_index,
1157 uint32_t mask)
1158 {
1159 ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask;
1160 }
1161
1162 /**
1163 * @brief Enable CPU1 wakeup source status with mask
1164 *
1165 * @param[in] ptr SYSCTL_Type base address
1166 * @param[in] enable_index wakeup enable index 0 - 7
1167 * @param[in] mask expected status mask
1168 */
sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1169 static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr,
1170 uint8_t enable_index,
1171 uint32_t mask)
1172 {
1173 ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask;
1174 }
1175
1176 /**
1177 * @brief Disable wakeup source status with mask
1178 *
1179 * @param[in] ptr SYSCTL_Type base address
1180 * @param[in] cpu_index CPU index
1181 * @param[in] enable_index wakeup enable index 0 - 7
1182 * @param[in] mask expected status mask
1183 */
sysctl_disable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)1184 static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr,
1185 uint8_t cpu_index,
1186 uint8_t enable_index,
1187 uint32_t mask)
1188 {
1189 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask;
1190 }
1191
1192 /**
1193 * @brief Disable CPU0 wakeup source status with mask
1194 *
1195 * @param[in] ptr SYSCTL_Type base address
1196 * @param[in] enable_index wakeup enable index 0 - 7
1197 * @param[in] mask expected status mask
1198 */
sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1199 static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr,
1200 uint8_t enable_index,
1201 uint32_t mask)
1202 {
1203 sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask);
1204 }
1205
1206
1207 /**
1208 * @brief Disable CPU1 wakeup source status with mask
1209 *
1210 * @param[in] ptr SYSCTL_Type base address
1211 * @param[in] enable_index wakeup enable index 0 - 7
1212 * @param[in] mask expected status mask
1213 */
sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1214 static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr,
1215 uint8_t enable_index,
1216 uint32_t mask)
1217 {
1218 sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask);
1219 }
1220
1221 /**
1222 * @brief Disable wakeup source status with irq
1223 *
1224 * @param[in] ptr SYSCTL_Type base address
1225 * @param[in] cpu_index CPU index
1226 * @param[in] irq_num irq number to be disabled as wakeup source
1227 */
sysctl_disable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1228 static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr,
1229 uint8_t cpu_index,
1230 uint16_t irq_num)
1231 {
1232 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32));
1233 }
1234
1235 /**
1236 * @brief Disable CPU0 wakeup source status with irq
1237 *
1238 * @param[in] ptr SYSCTL_Type base address
1239 * @param[in] irq_num irq number to be disabled as wakeup source
1240 */
sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1241 static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1242 {
1243 sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num);
1244 }
1245
1246
1247 /**
1248 * @brief Disable CPU1 wakeup source status with irq
1249 *
1250 * @param[in] ptr SYSCTL_Type base address
1251 * @param[in] irq_num irq number to be disabled as wakeup source
1252 */
sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1253 static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1254 {
1255 sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num);
1256 }
1257
1258 /**
1259 * @brief Enable wakeup source status with irq
1260 *
1261 * @param[in] ptr SYSCTL_Type base address
1262 * @param[in] cpu_index CPU index
1263 * @param[in] irq_num irq number to be set as wakeup source
1264 */
sysctl_enable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1265 static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num)
1266 {
1267 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F);
1268 }
1269
1270 /**
1271 * @brief Enable CPU0 wakeup source status with irq
1272 *
1273 * @param[in] ptr SYSCTL_Type base address
1274 * @param[in] irq_num irq number to be set as wakeup source
1275 */
sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1276 static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1277 {
1278 sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num);
1279 }
1280
1281 /**
1282 * @brief Enable CPU1 wakeup source status with irq
1283 *
1284 * @param[in] ptr SYSCTL_Type base address
1285 * @param[in] irq_num irq number to be set as wakeup source
1286 */
sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1287 static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1288 {
1289 sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num);
1290 }
1291
1292 /**
1293 * @brief Lock CPU gpr with mask
1294 *
1295 * @param[in] ptr SYSCTL_Type base address
1296 * @param[in] cpu_index CPU index
1297 * @param[in] gpr_mask bit mask of gpr registers to be locked
1298 */
sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t gpr_mask)1299 static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask)
1300 {
1301 ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask);
1302 }
1303
1304
1305 /**
1306 * @brief Lock CPU0 gpr with mask
1307 *
1308 * @param[in] ptr SYSCTL_Type base address
1309 * @param[in] gpr_mask bit mask of gpr registers to be locked
1310 */
sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1311 static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask)
1312 {
1313 sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask);
1314 }
1315
1316 /**
1317 * @brief Lock CPU1 gpr with mask
1318 *
1319 * @param[in] ptr SYSCTL_Type base address
1320 * @param[in] gpr_mask bit mask of gpr registers to be locked
1321 */
sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1322 static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask)
1323 {
1324 sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask);
1325 }
1326
1327 /**
1328 * @brief Lock CPU lock
1329 *
1330 * @param[in] ptr SYSCTL_Type base address
1331 * @param[in] cpu_index CPU index
1332 */
sysctl_cpu_lock(SYSCTL_Type * ptr,uint8_t cpu_index)1333 static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index)
1334 {
1335 ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK;
1336 }
1337
1338 /**
1339 * @brief Lock CPU0 lock
1340 *
1341 * @param[in] ptr SYSCTL_Type base address
1342 */
sysctl_cpu0_lock(SYSCTL_Type * ptr)1343 static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr)
1344 {
1345 sysctl_cpu_lock(ptr, 0);
1346 }
1347
1348 /**
1349 * @brief Lock CPU1 lock
1350 *
1351 * @param[in] ptr SYSCTL_Type base address
1352 */
sysctl_cpu1_lock(SYSCTL_Type * ptr)1353 static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr)
1354 {
1355 sysctl_cpu_lock(ptr, 1);
1356 }
1357
1358 /**
1359 * @brief Set CPU low power mode
1360 *
1361 * @param[in] ptr SYSCTL_Type base address
1362 * @param[in] cpu_index CPU index
1363 * @param[in] mode target mode to set
1364 */
sysctl_set_cpu_lp_mode(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_lp_mode_t mode)1365 static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode)
1366 {
1367 ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode);
1368 }
1369
1370 /**
1371 * @brief Set CPU0 low power mode
1372 *
1373 * @param[in] ptr SYSCTL_Type base address
1374 * @param[in] mode target mode to set
1375 */
sysctl_set_cpu0_lp_mode(SYSCTL_Type * ptr,cpu_lp_mode_t mode)1376 static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode)
1377 {
1378 sysctl_set_cpu_lp_mode(ptr, 0, mode);
1379 }
1380
1381 /**
1382 * @brief Set CPU1 low power mode
1383 *
1384 * @param[in] ptr SYSCTL_Type base address
1385 * @param[in] mode target mode to set
1386 */
sysctl_set_cpu1_lp_mode(SYSCTL_Type * ptr,cpu_lp_mode_t mode)1387 static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode)
1388 {
1389 sysctl_set_cpu_lp_mode(ptr, 1, mode);
1390 }
1391
1392 /**
1393 * @brief Clear CPU event flags
1394 *
1395 * @param[in] ptr SYSCTL_Type base address
1396 * @param[in] cpu_index CPU index
1397 * @param[in] flags flag mask to be cleared
1398 */
sysctl_clear_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_event_flag_mask_t flags)1399 static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags)
1400 {
1401 ptr->CPU[cpu_index].LP |=
1402 ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags);
1403 }
1404
1405 /**
1406 * @brief Clear CPU0 event flags
1407 *
1408 * @param[in] ptr SYSCTL_Type base address
1409 * @param[in] flags flag mask to be cleared
1410 */
sysctl_clear_cpu0_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)1411 static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
1412 {
1413 sysctl_clear_cpu_flags(ptr, 0, flags);
1414 }
1415
1416 /**
1417 * @brief Clear CPU1 event flags
1418 *
1419 * @param[in] ptr SYSCTL_Type base address
1420 * @param[in] flags flag mask to be cleared
1421 */
sysctl_clear_cpu1_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)1422 static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
1423 {
1424 sysctl_clear_cpu_flags(ptr, 1, flags);
1425 }
1426
1427 /**
1428 * @brief Get CPU event flags
1429 *
1430 * @param[in] ptr SYSCTL_Type base address
1431 * @param[in] cpu_index CPU index
1432 * @retval event flag mask
1433 */
sysctl_get_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index)1434 static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index)
1435 {
1436 return ptr->CPU[cpu_index].LP &
1437 (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK);
1438 }
1439
1440 /**
1441 * @brief Get CPU0 event flags
1442 *
1443 * @param[in] ptr SYSCTL_Type base address
1444 * @retval event flag mask
1445 */
sysctl_get_cpu0_flags(SYSCTL_Type * ptr)1446 static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr)
1447 {
1448 return sysctl_get_cpu_flags(ptr, 0);
1449 }
1450
1451 /**
1452 * @brief Get CPU1 event flags
1453 *
1454 * @param[in] ptr SYSCTL_Type base address
1455 * @retval event flag mask
1456 */
sysctl_get_cpu1_flags(SYSCTL_Type * ptr)1457 static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr)
1458 {
1459 return sysctl_get_cpu_flags(ptr, 1);
1460 }
1461
1462 /**
1463 * @brief Release cpu
1464 *
1465 * @param[in] ptr SYSCTL_Type base address
1466 * @param[in] cpu_index CPU index
1467 */
sysctl_release_cpu(SYSCTL_Type * ptr,uint8_t cpu_index)1468 static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index)
1469 {
1470 ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK;
1471 }
1472
1473 /**
1474 * @brief Release cpu1
1475 *
1476 * @param[in] ptr SYSCTL_Type base address
1477 */
sysctl_release_cpu1(SYSCTL_Type * ptr)1478 static inline void sysctl_release_cpu1(SYSCTL_Type *ptr)
1479 {
1480 sysctl_release_cpu(ptr, 1);
1481 }
1482
1483 /**
1484 * @brief Check whether CPU is released or not
1485 *
1486 * @param [in] ptr SYSCTL_Type base address
1487 * @param[in] cpu_index CPU index
1488 * @retval true CPU is released
1489 * @retval false CPU is on-hold
1490 */
sysctl_is_cpu_released(SYSCTL_Type * ptr,uint8_t cpu_index)1491 static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index)
1492 {
1493 return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U);
1494 }
1495
1496 /**
1497 * @brief Check whether CPU1 is released or not
1498 *
1499 * @param [in] ptr SYSCTL_Type base address
1500 * @retval true CPU1 is released
1501 * @retval false CPU1 is on-hold
1502 */
sysctl_is_cpu1_released(SYSCTL_Type * ptr)1503 static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr)
1504 {
1505 return sysctl_is_cpu_released(ptr, 1);
1506 }
1507
1508 /**
1509 * @brief Config lock
1510 *
1511 * @param[in] ptr SYSCTL_Type base address
1512 * @param[in] node clock node to be configured
1513 * @param[in] source clock source to be used
1514 * @param[in] divide_by clock frequency divider
1515 * @return status_success if everything is okay
1516 */
1517 hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by);
1518
1519 /**
1520 * @brief Set ADC clock mux
1521 *
1522 * @param[in] ptr SYSCTL_Type base address
1523 * @param[in] node clock node to be configured
1524 * @param[in] source clock source to be used
1525 * @return status_success if everything is okay
1526 */
1527 hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source);
1528
1529 /**
1530 * @brief Set I2S clock mux
1531 *
1532 * @param[in] ptr SYSCTL_Type base address
1533 * @param[in] node clock node to be configured
1534 * @param[in] source clock source to be used
1535 * @return status_success if everything is okay
1536 */
1537 hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source);
1538
1539 /**
1540 * @brief Enable group resource
1541 *
1542 * @param[in] ptr SYSCTL_Type base address
1543 * @param[in] group target group to be modified
1544 * @param[in] resource target resource to be added/removed from group
1545 * @param[in] enable set true to add resource, remove otherwise
1546 * @return status_success if everything is okay
1547 */
1548 hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr,
1549 uint8_t group,
1550 sysctl_resource_t resource,
1551 bool enable);
1552
1553 /**
1554 * @brief Check group resource enable status
1555 *
1556 * @param[in] ptr SYSCTL_Type base address
1557 * @param[in] group target group to be checked
1558 * @param[in] resource target resource to be checked from group
1559 * @return enable true if resource enable, false if resource disable
1560 */
1561 bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource);
1562
1563 /**
1564 * @brief Get group resource value
1565 *
1566 * @param[in] ptr SYSCTL_Type base address
1567 * @param[in] group target group to be getted
1568 * @param[in] index target group index
1569 * @return group index value
1570 */
1571 uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index);
1572
1573 /**
1574 * @brief Add resource to CPU0
1575 *
1576 * @param[in] ptr SYSCTL_Type base address
1577 * @param[in] resource resource to be added to CPU0
1578 * @return status_success if everything is okay
1579 */
1580 hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1581
1582 /**
1583 * @brief Remove resource from CPU0
1584 *
1585 * @param[in] ptr SYSCTL_Type base address
1586 * @param[in] resource Resource to be removed to CPU0
1587 * @return status_success if everything is okay
1588 */
1589 hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1590
1591 /**
1592 * @brief Add resource to CPU1
1593 *
1594 * @param[in] ptr SYSCTL_Type base address
1595 * @param[in] resource Resource to be added to CPU1
1596 * @return status_success if everything is okay
1597 */
1598 hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource);
1599
1600 /**
1601 * @brief Remove resource from CPU1
1602 *
1603 * @param[in] ptr SYSCTL_Type base address
1604 * @param[in] resource Resource to be removed to CPU1
1605 * @return status_success if everything is okay
1606 */
1607 hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource);
1608
1609 /**
1610 * @brief Get default monitor config
1611 *
1612 * @param[in] ptr SYSCTL_Type base address
1613 * @param[in] config Monitor config structure pointer
1614 */
1615 void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config);
1616
1617 /**
1618 * @brief Initialize Monitor
1619 *
1620 * @param[in] ptr SYSCTL_Type base address
1621 * @param[in] monitor_index Monitor instance to be initialized
1622 * @param[in] config Monitor config structure pointer
1623 */
1624 void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config);
1625
1626 /**
1627 * @brief Save data to CPU0 GPR starting from given index
1628 *
1629 * @param[in] ptr SYSCTL_Type base address
1630 * @param[in] start Starting GPR index
1631 * @param[in] count Number of GPR registers to set
1632 * @param[in] data Pointer to data buffer
1633 * @param[in] lock Set true to lock written GPR registers after setting
1634 * @return status_success if everything is okay
1635 */
1636 hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock);
1637
1638 /**
1639 * @brief Get data saved from CPU0 GPR starting from given index
1640 *
1641 * @param[in] ptr SYSCTL_Type base address
1642 * @param[in] start Starting GPR index
1643 * @param[in] count Number of GPR registers to set
1644 * @param[out] data Pointer of buffer to save data
1645 * @return status_success if everything is okay
1646 */
1647 hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data);
1648
1649 /**
1650 * @brief Set data to CPU1 GPR starting from given index
1651 *
1652 * @param[in] ptr SYSCTL_Type base address
1653 * @param[in] start Starting GPR index
1654 * @param[in] count Number of GPR registers to set
1655 * @param[in] data Pointer to data buffer
1656 * @param[in] lock Set true to lock written GPR registers after setting
1657 * @return status_success if everything is okay
1658 */
1659 hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock);
1660
1661 /**
1662 * @brief Get data saved in CPU1 GPR starting from given index
1663 *
1664 * @param[in] ptr SYSCTL_Type base address
1665 * @param[in] start Starting GPR index
1666 * @param[in] count Number of GPR registers to set
1667 * @param[out] data Pointer of buffer to save data
1668 * @return status_success if everything is okay
1669 */
1670 hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data);
1671
1672 /**
1673 * @brief Set entry point on CPU boot or wakeup
1674 *
1675 * @param[in] ptr SYSCTL_Type base address
1676 * @param[in] cpu CPU index
1677 * @param[in] entry Entry address for CPU
1678 * @return status_success if everything is okay
1679 */
1680 hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry);
1681
1682 /**
1683 * @brief Set entry point on CPU0 wakeup
1684 *
1685 * @param[in] ptr SYSCTL_Type base address
1686 * @param[in] entry Entry address for CPU0 on its wakeup
1687 * @return status_success if everything is okay
1688 */
1689 hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry);
1690
1691 /**
1692 * @brief Set entry point on either CPU1 boot or wakeup
1693 *
1694 * @param[in] ptr SYSCTL_Type base address
1695 * @param[in] entry Entry address for CPU1
1696 * @return status_success if everything is okay
1697 */
1698 hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry);
1699
1700 #ifdef __cplusplus
1701 }
1702 #endif
1703 /**
1704 * @}
1705 */
1706 #endif /* HPM_SYSCTL_DRV_H */
1707