1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_TSNS_H 10 #define HPM_TSNS_H 11 12 typedef struct { 13 __R uint32_t T; /* 0x0: Temperature */ 14 __R uint32_t TMAX; /* 0x4: Maximum Temperature */ 15 __R uint32_t TMIN; /* 0x8: Minimum Temperature */ 16 __R uint32_t AGE; /* 0xC: Sample age */ 17 __RW uint32_t STATUS; /* 0x10: Status */ 18 __RW uint32_t CONFIG; /* 0x14: Configuration */ 19 __RW uint32_t VALIDITY; /* 0x18: Sample validity */ 20 __RW uint32_t FLAG; /* 0x1C: Temperature flag */ 21 __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ 22 __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ 23 __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ 24 __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ 25 __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ 26 __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ 27 __RW uint32_t ADVAN; /* 0x38: Advance configuration */ 28 } TSNS_Type; 29 30 31 /* Bitfield definition for register: T */ 32 /* 33 * T (RO) 34 * 35 * Signed number of temperature in 256 x celsius degree 36 */ 37 #define TSNS_T_T_MASK (0xFFFFFFFFUL) 38 #define TSNS_T_T_SHIFT (0U) 39 #define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) 40 41 /* Bitfield definition for register: TMAX */ 42 /* 43 * T (RO) 44 * 45 * maximum temperature ever found 46 */ 47 #define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) 48 #define TSNS_TMAX_T_SHIFT (0U) 49 #define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) 50 51 /* Bitfield definition for register: TMIN */ 52 /* 53 * T (RO) 54 * 55 * minimum temperature ever found 56 */ 57 #define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) 58 #define TSNS_TMIN_T_SHIFT (0U) 59 #define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) 60 61 /* Bitfield definition for register: AGE */ 62 /* 63 * AGE (RO) 64 * 65 * age of T register in 24MHz clock cycles 66 */ 67 #define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) 68 #define TSNS_AGE_AGE_SHIFT (0U) 69 #define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) 70 71 /* Bitfield definition for register: STATUS */ 72 /* 73 * VALID (RO) 74 * 75 * indicate value in T is valid or not 76 * 0: not valid 77 * 1:valid 78 */ 79 #define TSNS_STATUS_VALID_MASK (0x80000000UL) 80 #define TSNS_STATUS_VALID_SHIFT (31U) 81 #define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) 82 83 /* 84 * TRIGGER (W1C) 85 * 86 * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode 87 */ 88 #define TSNS_STATUS_TRIGGER_MASK (0x1U) 89 #define TSNS_STATUS_TRIGGER_SHIFT (0U) 90 #define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) 91 #define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) 92 93 /* Bitfield definition for register: CONFIG */ 94 /* 95 * IRQ_EN (RW) 96 * 97 * Enable interrupt 98 */ 99 #define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) 100 #define TSNS_CONFIG_IRQ_EN_SHIFT (31U) 101 #define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) 102 #define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) 103 104 /* 105 * RST_EN (RW) 106 * 107 * Enable reset 108 */ 109 #define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) 110 #define TSNS_CONFIG_RST_EN_SHIFT (30U) 111 #define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) 112 #define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) 113 114 /* 115 * COMPARE_MIN_EN (RW) 116 * 117 * Enable compare for minimum temperature 118 */ 119 #define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) 120 #define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) 121 #define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) 122 #define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) 123 124 /* 125 * COMPARE_MAX_EN (RW) 126 * 127 * Enable compare for maximum temperature 128 */ 129 #define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) 130 #define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) 131 #define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) 132 #define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) 133 134 /* 135 * SPEED (RW) 136 * 137 * cycles of a progressive step in 24M clock, valid from 24-255, default 96 138 * 24: 24 cycle for a step 139 * 25: 25 cycle for a step 140 * 26: 26 cycle for a step 141 * ... 142 * 255: 255 cycle for a step 143 */ 144 #define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) 145 #define TSNS_CONFIG_SPEED_SHIFT (16U) 146 #define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) 147 #define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) 148 149 /* 150 * AVERAGE (RW) 151 * 152 * Average time, default in 3 153 * 0: measure and return 154 * 1: twice and average 155 * 2: 4 times and average 156 * . . . 157 * 7: 128 times and average 158 */ 159 #define TSNS_CONFIG_AVERAGE_MASK (0x700U) 160 #define TSNS_CONFIG_AVERAGE_SHIFT (8U) 161 #define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) 162 #define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) 163 164 /* 165 * CONTINUOUS (RW) 166 * 167 * continuous mode that keep sampling temperature peridically 168 * 0: trigger mode 169 * 1: continuous mode 170 */ 171 #define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) 172 #define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) 173 #define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) 174 #define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) 175 176 /* 177 * ASYNC (RW) 178 * 179 * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 180 * 0: active mode 181 * 1: Async mode 182 */ 183 #define TSNS_CONFIG_ASYNC_MASK (0x2U) 184 #define TSNS_CONFIG_ASYNC_SHIFT (1U) 185 #define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) 186 #define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) 187 188 /* 189 * ENABLE (RW) 190 * 191 * Enable temperature 192 * 0: disable, temperature sensor is shut down 193 * 1: enable. Temperature sensor enabled 194 */ 195 #define TSNS_CONFIG_ENABLE_MASK (0x1U) 196 #define TSNS_CONFIG_ENABLE_SHIFT (0U) 197 #define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) 198 #define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) 199 200 /* Bitfield definition for register: VALIDITY */ 201 /* 202 * VALIDITY (RW) 203 * 204 * time for temperature values to expire in 24M clock cycles 205 */ 206 #define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) 207 #define TSNS_VALIDITY_VALIDITY_SHIFT (0U) 208 #define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) 209 #define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) 210 211 /* Bitfield definition for register: FLAG */ 212 /* 213 * RECORD_MIN_CLR (RW) 214 * 215 * Clear minimum recorder of temerature, write 1 to clear 216 */ 217 #define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) 218 #define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) 219 #define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) 220 #define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) 221 222 /* 223 * RECORD_MAX_CLR (RW) 224 * 225 * Clear maximum recorder of temerature, write 1 to clear 226 */ 227 #define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) 228 #define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) 229 #define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) 230 #define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) 231 232 /* 233 * UNDER_TEMP (RW) 234 * 235 * Clear under temperature status, write 1 to clear 236 */ 237 #define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) 238 #define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) 239 #define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) 240 #define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) 241 242 /* 243 * OVER_TEMP (RW) 244 * 245 * Clear over temperature status, write 1 to clear 246 */ 247 #define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) 248 #define TSNS_FLAG_OVER_TEMP_SHIFT (16U) 249 #define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) 250 #define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) 251 252 /* 253 * IRQ (RW) 254 * 255 * IRQ flag, write 1 to clear 256 */ 257 #define TSNS_FLAG_IRQ_MASK (0x1U) 258 #define TSNS_FLAG_IRQ_SHIFT (0U) 259 #define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) 260 #define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) 261 262 /* Bitfield definition for register: UPPER_LIM_IRQ */ 263 /* 264 * T (RW) 265 * 266 * Maximum temperature for compare 267 */ 268 #define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) 269 #define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) 270 #define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) 271 #define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) 272 273 /* Bitfield definition for register: LOWER_LIM_IRQ */ 274 /* 275 * T (RW) 276 * 277 * Minimum temperature for compare 278 */ 279 #define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) 280 #define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) 281 #define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) 282 #define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) 283 284 /* Bitfield definition for register: UPPER_LIM_RST */ 285 /* 286 * T (RW) 287 * 288 * Maximum temperature for compare 289 */ 290 #define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) 291 #define TSNS_UPPER_LIM_RST_T_SHIFT (0U) 292 #define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) 293 #define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) 294 295 /* Bitfield definition for register: LOWER_LIM_RST */ 296 /* 297 * T (RW) 298 * 299 * Minimum temperature for compare 300 */ 301 #define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) 302 #define TSNS_LOWER_LIM_RST_T_SHIFT (0U) 303 #define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) 304 #define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) 305 306 /* Bitfield definition for register: ASYNC */ 307 /* 308 * ASYNC_TYPE (RW) 309 * 310 * Compare hotter than or colder than in asynchoronous mode 311 * 0: hotter than 312 * 1: colder than 313 */ 314 #define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) 315 #define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) 316 #define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) 317 #define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) 318 319 /* 320 * POLARITY (RW) 321 * 322 * Polarity of internal comparator 323 */ 324 #define TSNS_ASYNC_POLARITY_MASK (0x10000UL) 325 #define TSNS_ASYNC_POLARITY_SHIFT (16U) 326 #define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) 327 #define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) 328 329 /* 330 * VALUE (RW) 331 * 332 * Value of async mode to compare 333 */ 334 #define TSNS_ASYNC_VALUE_MASK (0x7FFU) 335 #define TSNS_ASYNC_VALUE_SHIFT (0U) 336 #define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) 337 #define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) 338 339 /* Bitfield definition for register: ADVAN */ 340 /* 341 * ASYNC_IRQ (RO) 342 * 343 * interrupt status of asynchronous mode 344 */ 345 #define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) 346 #define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) 347 #define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) 348 349 /* 350 * ACTIVE_IRQ (RO) 351 * 352 * interrupt status of active mode 353 */ 354 #define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) 355 #define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) 356 #define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) 357 358 /* 359 * SAMPLING (RO) 360 * 361 * temperature sampling is working 362 */ 363 #define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) 364 #define TSNS_ADVAN_SAMPLING_SHIFT (16U) 365 #define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) 366 367 /* 368 * NEG_ONLY (RW) 369 * 370 * use negative compare polarity only 371 */ 372 #define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) 373 #define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) 374 #define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) 375 #define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) 376 377 /* 378 * POS_ONLY (RW) 379 * 380 * use positive compare polarity only 381 */ 382 #define TSNS_ADVAN_POS_ONLY_MASK (0x1U) 383 #define TSNS_ADVAN_POS_ONLY_SHIFT (0U) 384 #define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) 385 #define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) 386 387 388 389 390 #endif /* HPM_TSNS_H */ 391