1/*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date           Author       Notes
8 * 2018/10/01     Bernard      The first version
9 * 2018/12/27     Jesven       Add SMP support
10 */
11
12#define __ASSEMBLY__
13#define MSTATUS_FS      0x00006000U /* initial state of FPU     */
14#include <cpuport.h>
15
16  .global   _start
17  .section ".start", "ax"
18_start:
19  j 1f
20  .word 0xdeadbeef
21  .align 3
22  .global g_wake_up
23  g_wake_up:
24      .dword 1
25      .dword 0
261:
27  csrw mideleg, 0
28  csrw medeleg, 0
29  csrw mie, 0
30  csrw mip, 0
31  la t0, trap_entry
32  csrw mtvec, t0
33
34  li x1, 0
35  li x2, 0
36  li x3, 0
37  li x4, 0
38  li x5, 0
39  li x6, 0
40  li x7, 0
41  li x8, 0
42  li x9, 0
43  li x10,0
44  li x11,0
45  li x12,0
46  li x13,0
47  li x14,0
48  li x15,0
49  li x16,0
50  li x17,0
51  li x18,0
52  li x19,0
53  li x20,0
54  li x21,0
55  li x22,0
56  li x23,0
57  li x24,0
58  li x25,0
59  li x26,0
60  li x27,0
61  li x28,0
62  li x29,0
63  li x30,0
64  li x31,0
65
66  /* set to initial state of FPU and disable interrupt */
67  li t0, MSTATUS_FS
68  csrs mstatus, t0
69
70  fssr    x0
71  fmv.w.x f0, x0
72  fmv.w.x f1, x0
73  fmv.w.x f2, x0
74  fmv.w.x f3, x0
75  fmv.w.x f4, x0
76  fmv.w.x f5, x0
77  fmv.w.x f6, x0
78  fmv.w.x f7, x0
79  fmv.w.x f8, x0
80  fmv.w.x f9, x0
81  fmv.w.x f10,x0
82  fmv.w.x f11,x0
83  fmv.w.x f12,x0
84  fmv.w.x f13,x0
85  fmv.w.x f14,x0
86  fmv.w.x f15,x0
87  fmv.w.x f16,x0
88  fmv.w.x f17,x0
89  fmv.w.x f18,x0
90  fmv.w.x f19,x0
91  fmv.w.x f20,x0
92  fmv.w.x f21,x0
93  fmv.w.x f22,x0
94  fmv.w.x f23,x0
95  fmv.w.x f24,x0
96  fmv.w.x f25,x0
97  fmv.w.x f26,x0
98  fmv.w.x f27,x0
99  fmv.w.x f28,x0
100  fmv.w.x f29,x0
101  fmv.w.x f30,x0
102  fmv.w.x f31,x0
103
104.option push
105.option norelax
106  la gp, __global_pointer$
107.option pop
108
109  /* get cpu id */
110  csrr a0, mhartid
111
112  la   sp, __stack_start__
113  addi t1, a0, 1
114  li   t2, __STACKSIZE__
115  mul  t1, t1, t2
116  add  sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
117
118  /* other cpu core, jump to cpu entry directly */
119  bnez a0, secondary_cpu_entry
120  tail primary_cpu_entry
121
122secondary_cpu_entry:
123#ifdef RT_USING_SMP
124  la a0, secondary_boot_flag
125  ld a0, 0(a0)
126  li a1, 0xa55a
127  beq a0, a1, 1f
128#endif
129  j secondary_cpu_entry
130
131#ifdef RT_USING_SMP
1321:
133  tail secondary_cpu_c_start
134
135.data
136.global secondary_boot_flag
137.align 3
138secondary_boot_flag:
139    .dword 0
140#endif
141