1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
2  *
3  * Redistribution and use in source and binary forms, with or without
4  * modification, are permitted provided that the following conditions are met:
5  * 1. Redistributions of source code must retain the above copyright
6  * notice, this list of conditions and the following disclaimer.
7  * 2. Redistributions in binary form must reproduce the above copyright
8  * notice, this list of conditions and the following disclaimer in the
9  * documentation and/or other materials provided with the distribution.
10  *
11  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
12  * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
15  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
16  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
17  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 /*
26  * Copyright (c) 2006-2025 RT-Thread Development Team
27  *
28  * SPDX-License-Identifier: Apache-2.0
29  */
30 #include <rtthread.h>
31 #include <rtdevice.h>
32 #include "riscv_io.h"
33 #include "board.h"
34 #include "ioremap.h"
35 #include <rtdbg.h>
36 #include <stdbool.h>
37 #include "sysctl_clk.h"
38 #include "drv_pwm.h"
39 #include <sys/ioctl.h>
40 
41 /**
42  *
43  * pwm0
44  *  ├── channel 0
45  *  ├── channel 1
46  *  └── channel 2
47  * pwm1
48  *  ├── channel 0
49  *  ├── channel 1
50  *  └── channel 2
51  *
52  * Note:
53  * The K230 PWM controller has 4 hardware channels:
54  * - Channel 0 (pwmcmp0) is used to set the period and does not generate output.
55  * - Channels 1 to 3 (pwmcmp1~3) are used to control the duty cycle and produce output signals.
56  * Therefore, the driver maps these output channels (1~3) as logical channels 0~2.
57  */
58 
59 #define PWM_REG_OFFSET       0x40
60 #define PWM_CFG_BIT_INVERT   (1 << 12)
61 #define PWM_CFG_DEGLITCH     (1 << 9)
62 #define PWM_MAX_SCALE        0xF
63 #define PWM_CMP_WIDTH        16
64 #define PWM_PERIOD_BITS      16
65 #define PWM_SCALE_MAX_BITS   15
66 #define PWM_DEV_NUM          2
67 #define PWM_MAX_CHANNELS     3
68 
69 #define PWM0_BASE_ADDR       PWM_BASE_ADDR
70 #define PWM1_BASE_ADDR       PWM_BASE_ADDR + PWM_REG_OFFSET
71 
72 struct k230_pwm_dev
73 {
74     struct rt_device_pwm device;
75     const char *name;
76     rt_ubase_t base;
77 };
78 
79 static struct k230_pwm_dev pwm_devs[] = {
80 #ifdef BSP_USING_PWM0
81     {
82         .name = "pwm0",
83         .base = PWM0_BASE_ADDR,
84     },
85 #endif
86 
87 #ifdef BSP_USING_PWM1
88     {
89         .name = "pwm1",
90         .base = PWM1_BASE_ADDR,
91     },
92 #endif
93 
94 #if !defined(BSP_USING_PWM0) && !defined(BSP_USING_PWM1)
95 #error "No pwm device defined!"
96 #endif
97 };
98 
check_channel(int channel)99 static int check_channel(int channel)
100 {
101     if (channel < 0 || channel >= PWM_MAX_CHANNELS)
102     {
103         LOG_E("channel %d is not valid\n", channel);
104         return -RT_ERROR;
105     }
106     return channel;
107 }
108 
pwm_start(kd_pwm_t * reg,int channel)109 static rt_err_t pwm_start(kd_pwm_t *reg, int channel)
110 {
111     rt_err_t ret;
112     ret = (rt_err_t)check_channel(channel);
113     if (ret < 0)
114         return ret;
115     reg->pwmcfg |= PWM_CFG_BIT_INVERT;  /* default always mode */
116     return RT_EOK;
117 }
118 
pwm_stop(kd_pwm_t * reg,int channel)119 static rt_err_t pwm_stop(kd_pwm_t *reg, int channel)
120 {
121     rt_err_t ret;
122     ret = (rt_err_t)check_channel(channel);
123     if (ret < 0)
124         return ret;
125     reg->pwmcfg &= ~PWM_CFG_BIT_INVERT;
126 
127     return RT_EOK;
128 }
129 
kd_pwm_get(kd_pwm_t * reg,int channel,struct rt_pwm_configuration * configuration)130 static rt_err_t kd_pwm_get(kd_pwm_t *reg, int channel, struct rt_pwm_configuration *configuration)
131 {
132     int ret;
133     uint64_t pulse, period;
134     uint32_t pwm_pclock, pwmscale;
135 
136     ret = check_channel(channel);
137     if (ret < 0)
138         return ret;
139 
140     pwm_pclock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_PWM_APB_GATE);
141 
142     pwmscale = reg->pwmcfg & 0xf;
143     pwm_pclock >>= pwmscale;
144     period = reg->pwmcmp0;
145     period = period * NSEC_PER_SEC / pwm_pclock;
146     pulse = *((&reg->pwmcmp1) + channel);
147     pulse = pulse * NSEC_PER_SEC / pwm_pclock;
148 
149     configuration->period = period;
150     configuration->pulse = pulse;
151 
152     return RT_EOK;
153 }
154 
kd_pwm_set(kd_pwm_t * reg,int channel,struct rt_pwm_configuration * configuration)155 static rt_err_t kd_pwm_set(kd_pwm_t *reg, int channel, struct rt_pwm_configuration *configuration)
156 {
157     int ret;
158     uint64_t pulse, period, pwmcmpx_max;
159     uint32_t pwm_pclock, pwmscale = 0;
160 
161     ret = check_channel(channel);
162     if (ret < 0)
163         return ret;
164 
165     pwm_pclock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_PWM_APB_GATE);
166     pulse = (uint64_t)configuration->pulse * pwm_pclock / NSEC_PER_SEC;
167     period = (uint64_t)configuration->period * pwm_pclock / NSEC_PER_SEC;
168     if (pulse > period)
169         return -RT_EINVAL;
170 
171 
172     /* Calculate duty cycle */
173     pwmcmpx_max = (1 << PWM_CMP_WIDTH) - 1;
174     if (period > ((1 << (PWM_SCALE_MAX_BITS + PWM_PERIOD_BITS)) - 1LL))
175         return -RT_EINVAL;
176 
177     while ((period >> pwmscale) > pwmcmpx_max)
178         pwmscale++;
179     if (pwmscale > PWM_MAX_SCALE)
180         return -RT_EINVAL;
181 
182     reg->pwmcfg |= PWM_CFG_DEGLITCH;  /* default always mode */
183     reg->pwmcfg &= (~PWM_MAX_SCALE);
184     reg->pwmcfg |= pwmscale;  /* scale */
185     reg->pwmcmp0 = (period >> pwmscale);
186     *((&reg->pwmcmp1) + channel) = reg->pwmcmp0 - (pulse >> pwmscale);
187 
188     return RT_EOK;
189 }
190 
kd_pwm_control(struct rt_device_pwm * device,int cmd,void * arg)191 static rt_err_t kd_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
192 {
193     struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
194     int channel = 0;
195     int ret;
196 
197     struct k230_pwm_dev *pwm_dev = rt_container_of(device, struct k230_pwm_dev, device);
198     kd_pwm_t *reg = (kd_pwm_t *)pwm_dev->base;
199     channel = configuration->channel;
200 
201     switch (cmd)
202     {
203     case PWM_CMD_ENABLE:
204         ret = pwm_start(reg, channel);
205         break;
206     case PWM_CMD_DISABLE:
207         ret = pwm_stop(reg, channel);
208         break;
209     case PWM_CMD_SET:
210         ret = kd_pwm_set(reg, channel, configuration);
211         break;
212     case PWM_CMD_GET:
213         ret = kd_pwm_get(reg, channel, configuration);
214         break;
215     default:
216         ret = -RT_EINVAL;
217     }
218 
219     return ret;
220 }
221 
222 static struct rt_pwm_ops drv_ops =
223 {
224     .control = kd_pwm_control
225 };
226 
rt_hw_pwm_init(void)227 int rt_hw_pwm_init(void)
228 {
229     rt_err_t ret;
230     for (int i = 0; i < sizeof(pwm_devs)/sizeof(struct k230_pwm_dev); i++)
231     {
232         struct k230_pwm_dev *dev = &pwm_devs[i];
233         dev->base = (rt_ubase_t)rt_ioremap((void *)(dev->base), sizeof(kd_pwm_t));
234         ret = rt_device_pwm_register(&dev->device, dev->name, &drv_ops, RT_NULL);
235         if (ret != RT_EOK)
236         {
237             LOG_E("Failed to register PWM device %s, error code: %d\n", dev->name, ret);
238             return ret;
239         }
240     }
241     return RT_EOK;
242 }
243 INIT_DEVICE_EXPORT(rt_hw_pwm_init);