1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
2  *
3  * Redistribution and use in source and binary forms, with or without
4  * modification, are permitted provided that the following conditions are met:
5  * 1. Redistributions of source code must retain the above copyright
6  * notice, this list of conditions and the following disclaimer.
7  * 2. Redistributions in binary form must reproduce the above copyright
8  * notice, this list of conditions and the following disclaimer in the
9  * documentation and/or other materials provided with the distribution.
10  *
11  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
12  * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
15  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
16  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
17  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 
26 /*
27  * Copyright (c) 2006-2025 RT-Thread Development Team
28  *
29  * SPDX-License-Identifier: Apache-2.0
30  */
31 #ifndef DRV_PWM_H__
32 #define DRV_PWM_H__
33 #include <stdint.h>
34 
35 #define NSEC_PER_SEC    1000000000L
36 typedef struct
37 {
38     volatile uint32_t pwmcfg;            /* 0x00 */
39     volatile uint32_t reserved0;
40     volatile uint32_t pwmcount;          /* 0x08 */
41     volatile uint32_t reserved1;
42     volatile uint32_t pwms;              /* 0x10 */
43     volatile uint32_t reserved2;
44     volatile uint32_t reserved3;
45     volatile uint32_t reserved4;
46     volatile uint32_t pwmcmp0;           /* 0x20 */
47     volatile uint32_t pwmcmp1;           /* 0x24 */
48     volatile uint32_t pwmcmp2;           /* 0x28 */
49     volatile uint32_t pwmcmp3;           /* 0x2c */
50 } kd_pwm_t;
51 
52 typedef struct
53 {
54     uint32_t scale : 4;
55     uint32_t reserve: 4;
56     uint32_t sticky : 1;
57     uint32_t zerocmp : 1;
58     uint32_t deglitch : 1;
59     uint32_t reserve1 : 1;
60     uint32_t enalways : 1;
61     uint32_t enoneshot : 1;
62     uint32_t reserve2 : 2;
63     uint32_t cmp0center : 1;
64     uint32_t cmp1center : 1;
65     uint32_t cmp2center : 1;
66     uint32_t cmp3center : 1;
67     uint32_t reserve3 : 4;
68     uint32_t cmp0gang : 1;
69     uint32_t cmp1gang : 1;
70     uint32_t cmp2gang : 1;
71     uint32_t cmp3gang : 1;
72     uint32_t cmp0ip : 1;
73     uint32_t cmp1ip : 1;
74     uint32_t cmp2ip : 1;
75     uint32_t cmp3ip : 1;
76 } pwm_cfg_t;
77 
78 typedef struct
79 {
80     pwm_cfg_t cfg;
81     uint32_t  freq;
82     uint32_t cmp0_val;
83     double   cmp1_duty;
84     double   cmp2_duty;
85     double   cmp3_duty;
86 } pwm_param_t;
87 
88 #endif