1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * 1. Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * 2. Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 12 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 15 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 16 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #ifndef __SYSCTL_PWR_H__ 27 #define __SYSCTL_PWR_H__ 28 29 /* created by yangfan */ 30 31 #include <stdint.h> 32 #include <stdbool.h> 33 34 /* See TRM 2.3.4 Table 2-3-3 */ 35 typedef struct 36 { 37 volatile uint32_t cpu0_pwr_tim; /* 0x00 */ 38 volatile uint32_t cpu0_lpi_tim; /* 0x04 */ 39 volatile uint32_t cpu0_pwr_lpi_ctl; /* 0x08 */ 40 volatile uint32_t cpu0_pwr_lpi_state; /* 0x0c */ 41 42 volatile uint32_t cpu1_pwr_tim; /* 0x10 */ 43 volatile uint32_t cpu1_lpi_tim; /* 0x14 */ 44 volatile uint32_t cpu1_pwr_lpi_ctl; /* 0x18 */ 45 volatile uint32_t cpu1_pwr_lpi_state; /* 0x1c */ 46 47 volatile uint32_t ai_pwr_tim; /* 0x20 */ 48 volatile uint32_t ai_lpi_tim; /* 0x24 */ 49 volatile uint32_t ai_pwr_lpi_ctl; /* 0x28 */ 50 volatile uint32_t ai_pwr_lpi_state; /* 0x2c */ 51 52 volatile uint32_t disp_pwr_tim; /* 0x30 */ 53 volatile uint32_t disp_lpi_tim; /* 0x34 */ 54 volatile uint32_t disp_gpu_tim; /* 0x38 */ 55 volatile uint32_t disp_lpi_ctl; /* 0x3c */ 56 volatile uint32_t disp_lpi_state; /* 0x40 */ 57 volatile uint32_t disp_reserved[7]; /* 0x44-0x4c, 0x50-0x5c */ 58 59 volatile uint32_t shrm_pwr_tim; /* 0x60 */ 60 volatile uint32_t shrm_lpi_tim; /* 0x64 */ 61 volatile uint32_t shrm_pwr_lpi_ctl; /* 0x68 */ 62 volatile uint32_t shrm_pwr_lpi_state; /* 0x6c */ 63 64 volatile uint32_t vpu_pwr_tim; /* 0x70 */ 65 volatile uint32_t vpu_lpi_tim; /* 0x74 */ 66 volatile uint32_t vpu_qch_tim; /* 0x78 */ 67 volatile uint32_t vpu_pwr_lpi_ctl; /* 0x7c */ 68 volatile uint32_t vpu_lpi_state; /* 0x80 */ 69 volatile uint32_t vpu_reserved[3]; /* 0x84-0x8c */ 70 71 volatile uint32_t mctl_pwr_tim0; /* 0x90 */ 72 volatile uint32_t mctl_noc_lpi_tim; /* 0x94 */ 73 volatile uint32_t mctl_axi_lpi_tim; /* 0x98 */ 74 volatile uint32_t mctl_pwr_lpi_ctl; /* 0x9c */ 75 volatile uint32_t mctl_clock_switch; /* 0xa0 */ 76 volatile uint32_t mctl_lpi_state; /* 0xa4 */ 77 volatile uint32_t mctl_reserved[22]; /* 0xa8-0xac, 0xb0-0xbc, 0xc0-0xcc, 0xd0-0xdc, 0xe0-0xec, 0xf0-0xfc */ 78 79 volatile uint32_t dpu_pwr_tim; /* 0x100 */ 80 volatile uint32_t dpu_lpi_tim; /* 0x104 */ 81 volatile uint32_t dpu_pwr_lpi_ctl; /* 0x108 */ 82 volatile uint32_t dpu_pwr_lpi_state; /* 0x10c */ 83 84 volatile uint32_t hi_pwr_tim; /* 0x110 */ 85 volatile uint32_t hi_lpi_tim; /* 0x114 */ 86 volatile uint32_t hi_pwr_lpi_ctl; /* 0x118 */ 87 volatile uint32_t hi_lpi_state; /* 0x11c */ 88 89 volatile uint32_t ls_pwr_tim; /* 0x120 */ 90 volatile uint32_t ls_lpi_tim; /* 0x124 */ 91 volatile uint32_t ls_pwr_lpi_ctl; /* 0x128 */ 92 volatile uint32_t ls_lpi_state; /* 0x12c */ 93 94 volatile uint32_t sec_pwr_tim; /* 0x130 */ 95 volatile uint32_t sec_lpi_tim; /* 0x134 */ 96 volatile uint32_t sec_pwr_lpi_ctl; /* 0x138 */ 97 volatile uint32_t sec_pwr_lpi_state; /* 0x13c */ 98 99 volatile uint32_t isp_pwr_tim; /* 0x140 */ 100 volatile uint32_t isp_lpi_tim; /* 0x144 */ 101 volatile uint32_t isp_pwr_lpi_ctl; /* 0x148 */ 102 volatile uint32_t isp_pwr_lpi_state; /* 0x14c */ 103 104 volatile uint32_t pmu_pwr_tim; /* 0x150 */ 105 volatile uint32_t pmu_lpi_tim; /* 0x154 */ 106 volatile uint32_t pmu_pwr_lpi_ctl; /* 0x158 */ 107 volatile uint32_t pmu_pwr_lpi_state; /* 0x15c */ 108 109 volatile uint32_t repair_status; /* 0x160 */ 110 volatile uint32_t sram0_repair_tim; /* 0x164 */ 111 volatile uint32_t ssys_ctl_gpio_ctl; /* 0x168 */ 112 volatile uint32_t ssys_reserved; /* 0x16c */ 113 volatile uint32_t ssys_ctl_gpio_en0; /* 0x170 */ 114 volatile uint32_t ssys_ctl_gpio_en1; /* 0x174 */ 115 116 volatile uint32_t cpu_repair_tim; /* 0x178 */ 117 } sysctl_pwr_s; 118 119 /* See TRM 2.3.1 Table 2-3-1 */ 120 typedef enum 121 { 122 SYSCTL_PD_CPU1, 123 SYSCTL_PD_AI, 124 SYSCTL_PD_DISP, 125 SYSCTL_PD_VPU, 126 SYSCTL_PD_DPU, 127 SYSCTL_PD_MAX, 128 } sysctl_pwr_domain_e; 129 130 131 typedef enum 132 { 133 SYSCTL_PWR_ACK_TO_TIM, /* idleReq to idleAck max time */ 134 SYSCTL_PWR_IDLE_TO_TIM, /* idleAck to idle max time */ 135 SYSCTL_PWR_IDLE_HD_TIM, /* idle hold tim, from idle to cancel idleReq min time */ 136 SYSCTL_PWR_ISO_SU_TIM, /* isolation setup tim */ 137 SYSCTL_PWR_PD_HD_TIM, /* power done hardware tim */ 138 SYSCTL_PWR_SU_TIM, /* Power bringup tim */ 139 SYSCTL_PWR_WFI_TIM, /* wait for interrupt tim*/ 140 SYSCTL_PWR_MAX_TIM, 141 } sysctl_pwr_tim_e; 142 143 144 bool sysctl_pwr_set_iso_su_tim(volatile uint32_t *reg, uint32_t iso_su_tim); 145 bool sysctl_pwr_set_pd_hd_tim(volatile uint32_t *reg, uint32_t pd_hd_tim); 146 bool sysctl_pwr_set_pwr_su_tim(volatile uint32_t *reg, uint32_t pwr_su_tim); 147 bool sysctl_pwr_set_ack_to_tim(volatile uint32_t *reg, uint32_t ack_to_tim); 148 bool sysctl_pwr_set_idle_to_tim(volatile uint32_t *reg, uint32_t idle_to_tim); 149 bool sysctl_pwr_set_idle_hd_tim(volatile uint32_t *reg, uint32_t idle_hd_tim); 150 bool sysctl_pwr_set_wfi_tim(volatile uint32_t *reg, uint32_t wfi_tim); 151 bool sysctl_pwr_set_tim(sysctl_pwr_domain_e powerdomain, sysctl_pwr_tim_e timtype, uint32_t tim_value); 152 bool sysctl_pwr_get_iso_su_tim(volatile uint32_t *reg, uint32_t *iso_su_tim); 153 bool sysctl_pwr_get_pd_hd_tim(volatile uint32_t *reg, uint32_t *pd_hd_tim); 154 bool sysctl_pwr_get_pwr_su_tim(volatile uint32_t *reg, uint32_t *pwr_su_tim); 155 bool sysctl_pwr_get_ack_to_tim(volatile uint32_t *reg, uint32_t *ack_to_tim); 156 bool sysctl_pwr_get_idle_to_tim(volatile uint32_t *reg, uint32_t *idle_to_tim); 157 bool sysctl_pwr_get_idle_hd_tim(volatile uint32_t *reg, uint32_t *idle_hd_tim); 158 bool sysctl_pwr_get_wfi_tim(volatile uint32_t *reg, uint32_t *wfi_tim); 159 bool sysctl_pwr_get_tim(sysctl_pwr_domain_e powerdomain, sysctl_pwr_tim_e timtype, uint32_t *tim_value); 160 bool sysctl_pwr_set_poweroff_keep_reset(sysctl_pwr_domain_e powerdomain, bool enable); 161 bool sysctl_pwr_get_poweroff_keep_reset(sysctl_pwr_domain_e powerdomain, bool *enable); 162 bool sysctl_pwr_set_auto_pwr(sysctl_pwr_domain_e powerdomain, bool enable); 163 bool sysctl_pwr_get_auto_pwr(sysctl_pwr_domain_e powerdomain, bool *enable); 164 bool sysctl_pwr_set_repair_enable(sysctl_pwr_domain_e powerdomain); 165 bool sysctl_pwr_check_repair_done(sysctl_pwr_domain_e powerdomain); 166 bool sysctl_pwr_set_lpi(sysctl_pwr_domain_e powerdomain, bool enable); 167 bool sysctl_pwr_set_pwr_reg(volatile uint32_t *regctl, volatile uint32_t *regsta, bool enable); 168 bool sysctl_pwr_set_power(sysctl_pwr_domain_e powerdomain, bool enable); 169 170 /* Following two APIs are used to control the power on and off of the SOC power domain */ 171 bool sysctl_pwr_up(sysctl_pwr_domain_e powerdomain); 172 bool sysctl_pwr_off(sysctl_pwr_domain_e powerdomain); 173 174 #endif