1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
2  *
3  * Redistribution and use in source and binary forms, with or without
4  * modification, are permitted provided that the following conditions are met:
5  * 1. Redistributions of source code must retain the above copyright
6  * notice, this list of conditions and the following disclaimer.
7  * 2. Redistributions in binary form must reproduce the above copyright
8  * notice, this list of conditions and the following disclaimer in the
9  * documentation and/or other materials provided with the distribution.
10  *
11  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
12  * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
15  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
16  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
17  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 
26 #include <rtthread.h>
27 #include <stdbool.h>
28 #include "sysctl_rst.h"
29 #include "ioremap.h"
30 #include "board.h"
31 
32 volatile sysctl_rst_t* sysctl_rst = (volatile sysctl_rst_t*)RMU_BASE_ADDR;
33 
sysctl_reset_cpu(volatile uint32_t * reset_reg,uint8_t reset_bit,uint8_t done_bit)34 static bool sysctl_reset_cpu(volatile uint32_t *reset_reg, uint8_t reset_bit, uint8_t done_bit)
35 {
36     /* clear done bit */
37     *reset_reg |= (1 << done_bit);
38     *reset_reg |= (1 << (done_bit + 0x10));  /* write enable */
39     /* usleep(100); */
40     rt_thread_delay(1);
41 
42     /* set reset bit */
43     *reset_reg |= (1 << reset_bit);
44     *reset_reg |= (1 << (reset_bit + 0x10));  /* write enable */
45     /* usleep(100); */
46     rt_thread_delay(1);
47 
48     /* clear reset bit */
49     if(0x9110100c == (uint64_t)reset_reg)
50     {
51         *reset_reg &= ~(1 << reset_bit);
52         *reset_reg |= (1 << (reset_bit + 0x10));   /* write enable */
53     }
54     /* usleep(100); */
55     rt_thread_delay(1);
56 
57     /* check done bit */
58     if(*reset_reg & (1 << done_bit))
59         return true;
60     else
61         return false;
62 }
63 
sysctl_reset_hw_done(volatile uint32_t * reset_reg,uint8_t reset_bit,uint8_t done_bit)64 static bool sysctl_reset_hw_done(volatile uint32_t *reset_reg, uint8_t reset_bit, uint8_t done_bit)
65 {
66     *reset_reg |= (1 << done_bit);      /* clear done bit */
67     /* usleep(100); */
68     rt_thread_delay(1);
69 
70     *reset_reg |= (1 << reset_bit);     /* set reset bit */
71     /* usleep(100); */
72     rt_thread_delay(1);
73     /* check done bit */
74     if(*reset_reg & (1 << done_bit))
75         return true;
76     else
77         return false;
78 }
79 
sysctl_reset_sw_done(volatile uint32_t * reset_reg,uint8_t reset_bit,uint32_t reset_en)80 static bool sysctl_reset_sw_done(volatile uint32_t *reset_reg, uint8_t reset_bit, uint32_t reset_en)
81 {
82     if(0 == reset_en)
83     {
84         if((0x91101020 == (uint64_t)reset_reg) || (0x91101024 == (uint64_t)reset_reg) || (0x91101080 == (uint64_t)reset_reg) || (0x91101064 == (uint64_t)reset_reg))
85         {
86             *reset_reg &= ~(1 << reset_bit);     /* set reset bit, 0 is assert */
87         }
88         else
89         {
90             *reset_reg |= (1 << reset_bit);     /* set reset bit, 1 is assert */
91         }
92     }
93     else
94     {
95         *reset_reg |= (1 << reset_bit) | (1 << reset_en);     /* set reset bit */
96     }
97     /* usleep(100); */
98     rt_thread_delay(1);
99 
100     if((0x91101004 != (uint64_t)reset_reg) && (0x9110100c != (uint64_t)reset_reg))
101     {
102         if(0x911010a8 == (uint64_t)reset_reg)
103         {
104             *reset_reg &= ~(1 << reset_bit);    /* clear reset bit, 0 is clear */
105         }
106         else
107         {
108             *reset_reg |= (1 << reset_bit);    /* clear reset bit, 1 is clear */
109         }
110     }
111     /* usleep(100); */
112     rt_thread_delay(1);
113 
114     return true;
115 }
116 
sysctl_reset(sysctl_reset_e reset)117 bool sysctl_reset(sysctl_reset_e reset)
118 {
119     switch(reset)
120     {
121         case SYSCTL_RESET_CPU0_CORE:
122             return sysctl_reset_cpu((volatile uint32_t *)&sysctl_rst->cpu0_rst_ctl, 0, 12);
123         case SYSCTL_RESET_CPU1_CORE:
124             return sysctl_reset_cpu((volatile uint32_t *)&sysctl_rst->cpu1_rst_ctl, 0, 12);
125 
126         case SYSCTL_RESET_AI:
127             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->ai_rst_ctl, 0, 31);
128         case SYSCTL_RESET_VPU:
129             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->vpu_rst_ctl, 0, 31);
130         case SYSCTL_RESET_HS:
131             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->hisys_rst_ctl, 0, 4);
132         case SYSCTL_RESET_HS_AHB:
133             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->hisys_rst_ctl, 1, 5);
134         case SYSCTL_RESET_SDIO0:
135             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sdc_rst_ctl, 0, 28);
136         case SYSCTL_RESET_SDIO1:
137             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sdc_rst_ctl, 1, 29);
138         case SYSCTL_RESET_SDIO_AXI:
139             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sdc_rst_ctl, 2, 30);
140         case SYSCTL_RESET_USB0:
141             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->usb_rst_ctl, 0, 28);
142         case SYSCTL_RESET_USB1:
143             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->usb_rst_ctl, 1, 29);
144         case SYSCTL_RESET_USB0_AHB:
145             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->usb_rst_ctl, 0, 30);
146         case SYSCTL_RESET_USB1_AHB:
147             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->usb_rst_ctl, 1, 31);
148         case SYSCTL_RESET_SPI0:
149             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->spi_rst_ctl, 0, 28);
150         case SYSCTL_RESET_SPI1:
151             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->spi_rst_ctl, 1, 29);
152         case SYSCTL_RESET_SPI2:
153             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->spi_rst_ctl, 2, 30);
154         case SYSCTL_RESET_SEC:
155             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sec_rst_ctl, 0, 31);
156         case SYSCTL_RESET_PDMA:
157             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->dma_rst_ctl, 0, 28);
158         case SYSCTL_RESET_SDMA:
159             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->dma_rst_ctl, 1, 29);
160         case SYSCTL_RESET_DECOMPRESS:
161             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->decompress_rst_ctl, 0, 31);
162         case SYSCTL_RESET_SRAM:
163             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sram_rst_ctl, 0, 28);
164         case SYSCTL_RESET_SHRM_AXIM:
165             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sram_rst_ctl, 2, 30);
166         case SYSCTL_RESET_SHRM_AXIS:
167             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->sram_rst_ctl, 3, 31);
168         case SYSCTL_RESET_NONAI2D:
169             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->nonai2d_rst_ctl, 0, 31);
170         case SYSCTL_RESET_MCTL:
171             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->mctl_rst_ctl, 0, 31);
172         case SYSCTL_RESET_ISP:
173             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 6, 29);
174         case SYSCTL_RESET_ISP_DW:
175             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 5, 28);
176         case SYSCTL_RESET_DPU:
177             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->dpu_rst_ctl, 0, 31);
178         case SYSCTL_RESET_DISP:
179             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->disp_rst_ctl, 0, 31);
180         case SYSCTL_RESET_GPU:
181             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->v2p5d_rst_ctl, 0, 31);
182         case SYSCTL_RESET_AUDIO:
183             return sysctl_reset_hw_done((volatile uint32_t *)&sysctl_rst->audio_rst_ctl, 0, 31);
184 
185         case SYSCTL_RESET_TIMER0:
186             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 0, 0);
187         case SYSCTL_RESET_TIMER1:
188             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 1, 0);
189         case SYSCTL_RESET_TIMER2:
190             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 2, 0);
191         case SYSCTL_RESET_TIMER3:
192             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 3, 0);
193         case SYSCTL_RESET_TIMER4:
194             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 4, 0);
195         case SYSCTL_RESET_TIMER5:
196             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 5, 0);
197         case SYSCTL_RESET_TIMER_APB:
198             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 6, 0);
199         case SYSCTL_RESET_HDI:
200             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 7, 0);
201         case SYSCTL_RESET_WDT0:
202             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 12, 0);
203         case SYSCTL_RESET_WDT1:
204             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 13, 0);
205         case SYSCTL_RESET_WDT0_APB:
206             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 14, 0);
207         case SYSCTL_RESET_WDT1_APB:
208             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 15, 0);
209         case SYSCTL_RESET_TS_APB:
210             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 16, 0);
211         case SYSCTL_RESET_MAILBOX:
212             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 17, 0);
213         case SYSCTL_RESET_STC:
214             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 18, 0);
215         case SYSCTL_RESET_PMU:
216             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->soc_ctl_rst_ctl, 19, 0);
217         case SYSCTL_RESET_LS_APB:
218             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 0, 0);
219         case SYSCTL_RESET_UART0:
220             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 1, 0);
221         case SYSCTL_RESET_UART1:
222             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 2, 0);
223         case SYSCTL_RESET_UART2:
224             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 3, 0);
225         case SYSCTL_RESET_UART3:
226             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 4, 0);
227         case SYSCTL_RESET_UART4:
228             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 5, 0);
229         case SYSCTL_RESET_I2C0:
230             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 6, 0);
231         case SYSCTL_RESET_I2C1:
232             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 7, 0);
233         case SYSCTL_RESET_I2C2:
234             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 8, 0);
235         case SYSCTL_RESET_I2C3:
236             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 9, 0);
237         case SYSCTL_RESET_I2C4:
238             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 10, 0);
239         case SYSCTL_RESET_JAMLINK0_APB:
240             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 11, 0);
241         case SYSCTL_RESET_JAMLINK1_APB:
242             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 12, 0);
243         case SYSCTL_RESET_JAMLINK2_APB:
244             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 13, 0);
245         case SYSCTL_RESET_JAMLINK3_APB:
246             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 14, 0);
247         case SYSCTL_RESET_CODEC_APB:
248             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 17, 0);
249         case SYSCTL_RESET_GPIO_DB:
250             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 18, 0);
251         case SYSCTL_RESET_GPIO_APB:
252             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 19, 0);
253         case SYSCTL_RESET_ADC:
254             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 20, 0);
255         case SYSCTL_RESET_ADC_APB:
256             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 21, 0);
257         case SYSCTL_RESET_PWM_APB:
258             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->losys_rst_ctl, 22, 0);
259 
260         case SYSCTL_RESET_CPU0_FLUSH:
261             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->cpu0_rst_ctl, 4, 20);
262         case SYSCTL_RESET_CPU1_FLUSH:
263             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->cpu1_rst_ctl, 4, 20);
264         case SYSCTL_RESET_SHRM_APB:
265             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->sram_rst_ctl, 1, 0);
266         case SYSCTL_RESET_CSI0_APB:
267             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 0, 0);
268         case SYSCTL_RESET_CSI1_APB:
269             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 1, 0);
270         case SYSCTL_RESET_CSI2_APB:
271             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 2, 0);
272         case SYSCTL_RESET_CSI_DPHY_APB:
273             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 3, 0);
274         case SYSCTL_RESET_ISP_AHB:
275             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 4, 0);
276         case SYSCTL_RESET_M0:
277             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 7, 0);
278         case SYSCTL_RESET_M1:
279             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 8, 0);
280         case SYSCTL_RESET_M2:
281             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->isp_rst_ctl, 9, 0);
282         case SYSCTL_RESET_SPI2AXI:
283             return sysctl_reset_sw_done((volatile uint32_t *)&sysctl_rst->spi2axi_rst_ctl, 0, 0);
284 
285         default:
286             return false;
287     }
288 }
289 
sysctl_set_reset_time(sysctl_reset_time_e reset,uint32_t tim0,uint32_t tim1,uint32_t tim2)290 bool sysctl_set_reset_time(sysctl_reset_time_e reset, uint32_t tim0, uint32_t tim1, uint32_t tim2)
291 {
292     volatile uint32_t ret;
293 
294     switch(reset)
295     {
296         case SYSCTL_RESET_TIME_CPU0:
297         {
298             if((tim1 > 0xF) || (tim2 > 0xF))
299             {
300                 return false;
301             }
302             else
303             {
304                 ret = sysctl_rst->cpu0_rst_tim;
305                 ret &= 0xf0000fff;
306                 sysctl_rst->cpu0_rst_tim = ret | ((tim1 << 12) | (tim2 << 20));
307                 return true;
308             }
309         }
310         case SYSCTL_RESET_TIME_CPU0_APB:
311         {
312             if((tim1 > 0xF) || (tim2 > 0xF))
313             {
314                 return false;
315             }
316             else
317             {
318                 ret = sysctl_rst->cpu0_rst_tim;
319                 ret &= 0xfffff00f;
320                 sysctl_rst->cpu0_rst_tim = ret | ((tim1 << 4) | (tim2 << 8));
321                 return true;
322             }
323         }
324         case SYSCTL_RESET_TIME_CPU1:
325         {
326             if((tim1 > 0xF) || (tim2 > 0xF))
327             {
328                 return false;
329             }
330             else
331             {
332                 ret = sysctl_rst->cpu1_rst_tim;
333                 ret &= 0xfff00fff;
334                 sysctl_rst->cpu1_rst_tim = ret | ((tim1 << 12) | (tim2 << 16));
335                 return true;
336             }
337         }
338         case SYSCTL_RESET_TIME_CPU1_APB:
339         {
340             if((tim1 > 0xF) || (tim2 > 0xF))
341             {
342                 return false;
343             }
344             else
345             {
346                 ret = sysctl_rst->cpu1_rst_tim;
347                 ret &= 0xfffff00f;
348                 sysctl_rst->cpu1_rst_tim = ret | ((tim1 << 4) | (tim2 << 8));
349                 return true;
350             }
351         }
352         case SYSCTL_RESET_TIME_AI:
353         {
354             if((tim1 > 0xF) || (tim2 > 0xF))
355             {
356                 return false;
357             }
358             else
359             {
360                 ret = sysctl_rst->ai_rst_tim;
361                 ret &= 0xfffff00f;
362                 sysctl_rst->ai_rst_tim = ret | ((tim1 << 4) | (tim2 << 8));
363                 return true;
364             }
365         }
366         case SYSCTL_RESET_TIME_VPU:
367         {
368             if((tim1 > 0xF) || (tim2 > 0xF))
369             {
370                 return false;
371             }
372             else
373             {
374                 ret = sysctl_rst->vpu_rst_tim;
375                 ret &= 0xfffff00f;
376                 sysctl_rst->vpu_rst_tim = ret | ((tim1 << 4) | (tim2 << 8));
377                 return true;
378             }
379         }
380         case SYSCTL_RESET_TIME_HS_HCLK:
381         {
382             if((tim1 > 0x1F) || (tim2 > 0xF))
383             {
384                 return false;
385             }
386             else
387             {
388                 ret = sysctl_rst->hisys_hclk_tim;
389                 ret &= 0xfff0f0ff;
390                 sysctl_rst->hisys_hclk_tim = ret | ((tim1 << 8) | (tim2 << 16));
391                 return true;
392             }
393         }
394         case SYSCTL_RESET_TIME_SDCTL:
395         {
396             if((tim1 > 0x1F) || (tim2 > 0xF))
397             {
398                 return false;
399             }
400             else
401             {
402                 ret = sysctl_rst->sdctl_rst_tim;
403                 ret &= 0xfff0f0ff;
404                 sysctl_rst->sdctl_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
405                 return true;
406             }
407         }
408         case SYSCTL_RESET_TIME_USB:
409         {
410             if((tim1 > 0xF) || (tim2 > 0xF))
411             {
412                 return false;
413             }
414             else
415             {
416                 ret = sysctl_rst->usb_rst_tim;
417                 ret &= 0xffffff00;
418                 sysctl_rst->usb_rst_tim = ret | ((tim1 << 0) | (tim2 << 4));
419                 return true;
420             }
421         }
422         case SYSCTL_RESET_TIME_USB_AHB:
423         {
424             if((tim1 > 0xF) || (tim2 > 0xF))
425             {
426                 return false;
427             }
428             else
429             {
430                 ret = sysctl_rst->usb_rst_tim;
431                 ret &= 0xff0000ff;
432                 sysctl_rst->usb_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
433                 return true;
434             }
435         }
436         case SYSCTL_RESET_TIME_SPI:
437         {
438             if((tim1 > 0x3F) || (tim2 > 0xF))
439             {
440                 return false;
441             }
442             else
443             {
444                 ret = sysctl_rst->spi_rst_tim;
445                 ret &= 0xfff0f0ff;
446                 sysctl_rst->spi_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
447                 return true;
448             }
449         }
450         case SYSCTL_RESET_TIME_SEC_SYS:
451         {
452             if((tim1 > 0xFF) || (tim2 > 0xF))
453             {
454                 return false;
455             }
456             else
457             {
458                 ret = sysctl_rst->sec_sys_rst_tim;
459                 ret &= 0xfff0f0ff;
460                 sysctl_rst->sec_sys_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
461                 return true;
462             }
463         }
464         case SYSCTL_RESET_TIME_DMAC:
465         {
466             if((tim1 > 0x7) || (tim2 > 0x7))
467             {
468                 return false;
469             }
470             else
471             {
472                 ret = sysctl_rst->dmac_rst_tim;
473                 ret &= 0xfff0f0ff;
474                 sysctl_rst->dmac_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
475                 return true;
476             }
477         }
478         case SYSCTL_RESET_TIME_DECOMPRESS:
479         {
480             if((tim1 > 0x7) || (tim2 > 0x7))
481             {
482                 return false;
483             }
484             else
485             {
486                 ret = sysctl_rst->decompress_rst_tim;
487                 ret &= 0xfff0f0ff;
488                 sysctl_rst->decompress_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
489                 return true;
490             }
491         }
492         case SYSCTL_RESET_TIME_SRAM:
493         {
494             if((tim1 > 0xF) || (tim2 > 0xF))
495             {
496                 return false;
497             }
498             else
499             {
500                 ret = sysctl_rst->sram_rst_tim;
501                 ret &= 0xfff0f0ff;
502                 sysctl_rst->sram_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
503                 return true;
504             }
505         }
506         case SYSCTL_RESET_TIME_NONAI2D:
507         {
508             if((tim1 > 0xF) || (tim2 > 0xF))
509             {
510                 return false;
511             }
512             else
513             {
514                 ret = sysctl_rst->nonai2d_rst_tim;
515                 ret &= 0xfff0f0ff;
516                 sysctl_rst->nonai2d_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
517                 return true;
518             }
519         }
520         case SYSCTL_RESET_TIME_MCTL:
521         {
522             if(tim0 > 0xF)
523             {
524                 return false;
525             }
526             else
527             {
528                 ret = sysctl_rst->mctl_rst_tim;
529                 ret &= 0xffffffc0;
530                 sysctl_rst->mctl_rst_tim = ret | (tim0 << 0);
531                 return true;
532             }
533         }
534         case SYSCTL_RESET_TIME_ISP:
535         {
536             if((tim0 > 0xFF) || (tim1 > 0xF) || (tim2 > 0xF))
537             {
538                 return false;
539             }
540             else
541             {
542                 ret = sysctl_rst->isp_rst_tim;
543                 ret &= 0xfff0f0f0;
544                 sysctl_rst->isp_rst_tim = ret | ((tim0 << 0) | (tim1 << 8) | (tim2 << 16));
545                 return true;
546             }
547         }
548         case SYSCTL_RESET_TIME_ISP_DW:
549         {
550             if((tim0 > 0xFF) || (tim1 > 0xF) || (tim2 > 0xF))
551             {
552                 return false;
553             }
554             else
555             {
556                 ret = sysctl_rst->isp_dw_rst_tim;
557                 ret &= 0xfff0f0f0;
558                 sysctl_rst->isp_dw_rst_tim = ret | ((tim0 << 0) | (tim1 << 8) | (tim2 << 16));
559                 return true;
560             }
561         }
562         case SYSCTL_RESET_TIME_DPU:
563         {
564             if((tim1 > 0xF) || (tim2 > 0xF))
565             {
566                 return false;
567             }
568             else
569             {
570                 ret = sysctl_rst->dpu_rst_tim;
571                 ret &= 0xfff0f0ff;
572                 sysctl_rst->dpu_rst_tim = ret | ((tim1 << 8) | (tim2 << 16));
573                 return true;
574             }
575         }
576         case SYSCTL_RESET_TIME_DISP_SYS:
577         {
578             if((tim0 > 0xFF) || (tim1 > 0xFF) || (tim2 > 0xF))
579             {
580                 return false;
581             }
582             else
583             {
584                 ret = sysctl_rst->disp_sys_rst_tim;
585                 ret &= 0xfff0f0f0;
586                 sysctl_rst->disp_sys_rst_tim = ret | ((tim0 << 0) | (tim1 << 8) | (tim2 << 16));
587                 return true;
588             }
589         }
590         case SYSCTL_RESET_TIME_V2P5D_SYS:
591         {
592             if((tim0 > 0xFF) || (tim1 > 0xFF) || (tim2 > 0xF))
593             {
594                 return false;
595             }
596             else
597             {
598                 ret = sysctl_rst->v2p5d_sys_rst_tim;
599                 ret &= 0xfff0f0f0;
600                 sysctl_rst->v2p5d_sys_rst_tim = ret | ((tim0 << 0) | (tim1 << 8) | (tim2 << 16));
601                 return true;
602             }
603         }
604         case SYSCTL_RESET_TIME_AUDIO:
605         {
606             if((tim1 > 0xF) || (tim2 > 0xF))
607             {
608                 return false;
609             }
610             else
611             {
612                 ret = sysctl_rst->audio_rst_tim;
613                 ret &= 0xfffff00f;
614                 sysctl_rst->audio_rst_tim = ret | ((tim1 << 4) | (tim2 << 8));
615                 return true;
616             }
617         }
618 
619         default:
620             return false;
621     }
622 }
623 
rt_hw_sysctl_rst_init(void)624 int rt_hw_sysctl_rst_init(void)
625 {
626     sysctl_rst = rt_ioremap((void*)RMU_BASE_ADDR, RMU_IO_SIZE);
627     if(!sysctl_rst)
628     {
629         rt_kprintf("sysctl_rst ioremap error\n");
630         return -1;
631     }
632 
633     return 0;
634 }
635 INIT_BOARD_EXPORT(rt_hw_sysctl_rst_init);