1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * 1. Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * 2. Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 12 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 15 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 16 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #ifndef __SYSCTL_RST_H__ 27 #define __SYSCTL_RST_H__ 28 29 /* created by yangfan */ 30 31 #include <stdint.h> 32 #include "stdbool.h" 33 34 typedef enum 35 { 36 SYSCTL_RESET_CPU0_CORE, 37 /* SYSCTL_RESET_CPU0_APB, */ 38 /* SYSCTL_RESET_CPU0_TDI, */ 39 SYSCTL_RESET_CPU0_FLUSH, 40 SYSCTL_RESET_CPU1_CORE, 41 /* SYSCTL_RESET_CPU1_APB, */ 42 SYSCTL_RESET_CPU1_FLUSH, 43 SYSCTL_RESET_AI, 44 SYSCTL_RESET_VPU, 45 SYSCTL_RESET_HS, 46 SYSCTL_RESET_HS_AHB, 47 SYSCTL_RESET_SDIO0, 48 SYSCTL_RESET_SDIO1, 49 SYSCTL_RESET_SDIO_AXI, 50 SYSCTL_RESET_USB0, 51 SYSCTL_RESET_USB1, 52 SYSCTL_RESET_USB0_AHB, 53 SYSCTL_RESET_USB1_AHB, 54 SYSCTL_RESET_SPI0, 55 SYSCTL_RESET_SPI1, 56 SYSCTL_RESET_SPI2, 57 SYSCTL_RESET_SEC, 58 SYSCTL_RESET_PDMA, 59 SYSCTL_RESET_SDMA, 60 SYSCTL_RESET_DECOMPRESS, 61 SYSCTL_RESET_SRAM, 62 SYSCTL_RESET_SHRM_AXIM, 63 SYSCTL_RESET_SHRM_AXIS, 64 SYSCTL_RESET_SHRM_APB, 65 SYSCTL_RESET_NONAI2D, 66 SYSCTL_RESET_MCTL, 67 SYSCTL_RESET_ISP, 68 SYSCTL_RESET_ISP_DW, 69 SYSCTL_RESET_CSI0_APB, 70 SYSCTL_RESET_CSI1_APB, 71 SYSCTL_RESET_CSI2_APB, 72 SYSCTL_RESET_CSI_DPHY_APB, 73 SYSCTL_RESET_ISP_AHB, 74 SYSCTL_RESET_M0, 75 SYSCTL_RESET_M1, 76 SYSCTL_RESET_M2, 77 SYSCTL_RESET_DPU, 78 SYSCTL_RESET_DISP, 79 SYSCTL_RESET_GPU, 80 SYSCTL_RESET_AUDIO, 81 SYSCTL_RESET_TIMER0, 82 SYSCTL_RESET_TIMER1, 83 SYSCTL_RESET_TIMER2, 84 SYSCTL_RESET_TIMER3, 85 SYSCTL_RESET_TIMER4, 86 SYSCTL_RESET_TIMER5, 87 SYSCTL_RESET_TIMER_APB, 88 SYSCTL_RESET_HDI, 89 SYSCTL_RESET_WDT0, 90 SYSCTL_RESET_WDT1, 91 SYSCTL_RESET_WDT0_APB, 92 SYSCTL_RESET_WDT1_APB, 93 SYSCTL_RESET_TS_APB, 94 SYSCTL_RESET_MAILBOX, 95 SYSCTL_RESET_STC, 96 SYSCTL_RESET_PMU, 97 SYSCTL_RESET_LS_APB, 98 SYSCTL_RESET_UART0, 99 SYSCTL_RESET_UART1, 100 SYSCTL_RESET_UART2, 101 SYSCTL_RESET_UART3, 102 SYSCTL_RESET_UART4, 103 SYSCTL_RESET_I2C0, 104 SYSCTL_RESET_I2C1, 105 SYSCTL_RESET_I2C2, 106 SYSCTL_RESET_I2C3, 107 SYSCTL_RESET_I2C4, 108 SYSCTL_RESET_JAMLINK0_APB, 109 SYSCTL_RESET_JAMLINK1_APB, 110 SYSCTL_RESET_JAMLINK2_APB, 111 SYSCTL_RESET_JAMLINK3_APB, 112 SYSCTL_RESET_CODEC_APB, 113 SYSCTL_RESET_GPIO_DB, 114 SYSCTL_RESET_GPIO_APB, 115 SYSCTL_RESET_ADC, 116 SYSCTL_RESET_ADC_APB, 117 SYSCTL_RESET_PWM_APB, 118 SYSCTL_RESET_SPI2AXI, 119 } sysctl_reset_e; 120 121 typedef enum 122 { 123 SYSCTL_RESET_TIME_CPU0, 124 SYSCTL_RESET_TIME_CPU0_APB, 125 SYSCTL_RESET_TIME_CPU1, 126 SYSCTL_RESET_TIME_CPU1_APB, 127 SYSCTL_RESET_TIME_AI, 128 SYSCTL_RESET_TIME_VPU, 129 SYSCTL_RESET_TIME_HS_HCLK, 130 SYSCTL_RESET_TIME_SDCTL, 131 SYSCTL_RESET_TIME_USB, 132 SYSCTL_RESET_TIME_USB_AHB, 133 SYSCTL_RESET_TIME_SPI, 134 SYSCTL_RESET_TIME_SEC_SYS, 135 SYSCTL_RESET_TIME_DMAC, 136 SYSCTL_RESET_TIME_DECOMPRESS, 137 SYSCTL_RESET_TIME_SRAM, 138 SYSCTL_RESET_TIME_NONAI2D, 139 SYSCTL_RESET_TIME_MCTL, 140 SYSCTL_RESET_TIME_ISP, 141 SYSCTL_RESET_TIME_ISP_DW, 142 SYSCTL_RESET_TIME_DPU, 143 SYSCTL_RESET_TIME_DISP_SYS, 144 SYSCTL_RESET_TIME_V2P5D_SYS, 145 SYSCTL_RESET_TIME_AUDIO, 146 } sysctl_reset_time_e; 147 148 /* See TRM 2.1.4, Table 2-1-2 */ 149 typedef struct { 150 volatile uint32_t cpu0_rst_tim; /* 0x00 */ 151 volatile uint32_t cpu0_rst_ctl; /* 0x04 */ 152 volatile uint32_t cpu1_rst_tim; /* 0x08 */ 153 volatile uint32_t cpu1_rst_ctl; /* 0x0c */ 154 volatile uint32_t ai_rst_tim; /* 0x10 */ 155 volatile uint32_t ai_rst_ctl; /* 0x14 */ 156 volatile uint32_t vpu_rst_tim; /* 0x18 */ 157 volatile uint32_t vpu_rst_ctl; /* 0x1c */ 158 volatile uint32_t soc_ctl_rst_ctl; /* 0x20 */ 159 volatile uint32_t losys_rst_ctl; /* 0x24 */ 160 volatile uint32_t hisys_hclk_tim; /* 0x28 */ 161 volatile uint32_t hisys_rst_ctl; /* 0x2c */ 162 volatile uint32_t sdctl_rst_tim; /* 0x30 */ 163 volatile uint32_t sdc_rst_ctl; /* 0x34 */ 164 volatile uint32_t usb_rst_tim; /* 0x38 */ 165 volatile uint32_t usb_rst_ctl; /* 0x3c */ 166 volatile uint32_t spi_rst_tim; /* 0x40 */ 167 volatile uint32_t spi_rst_ctl; /* 0x44 */ 168 volatile uint32_t sec_sys_rst_tim; /* 0x48 */ 169 volatile uint32_t sec_rst_ctl; /* 0x4c */ 170 volatile uint32_t dmac_rst_tim; /* 0x50 */ 171 volatile uint32_t dma_rst_ctl; /* 0x54 */ 172 volatile uint32_t decompress_rst_tim; /* 0x58 */ 173 volatile uint32_t decompress_rst_ctl; /* 0x5c */ 174 volatile uint32_t sram_rst_tim; /* 0x60 */ 175 volatile uint32_t sram_rst_ctl; /* 0x64 */ 176 volatile uint32_t nonai2d_rst_tim; /* 0x68 */ 177 volatile uint32_t nonai2d_rst_ctl; /* 0x6c */ 178 volatile uint32_t mctl_rst_tim; /* 0x70 */ 179 volatile uint32_t mctl_rst_ctl; /* 0x74 */ 180 volatile uint32_t isp_rst_tim; /* 0x78 */ 181 volatile uint32_t isp_dw_rst_tim; /* 0x7c */ 182 volatile uint32_t isp_rst_ctl; /* 0x80 */ 183 volatile uint32_t dpu_rst_tim; /* 0x84 */ 184 volatile uint32_t dpu_rst_ctl; /* 0x88 */ 185 volatile uint32_t disp_sys_rst_tim; /* 0x8c */ 186 volatile uint32_t disp_rst_ctl; /* 0x90 */ 187 volatile uint32_t v2p5d_sys_rst_tim; /* 0x94 */ 188 volatile uint32_t v2p5d_rst_ctl; /* 0x98 */ 189 volatile uint32_t reserved; /* 0x9c */ 190 volatile uint32_t audio_rst_tim; /* 0xa0 */ 191 volatile uint32_t audio_rst_ctl; /* 0xa4 */ 192 volatile uint32_t spi2axi_rst_ctl; /* 0xa8 */ 193 } sysctl_rst_t; 194 195 /* Just call this API to reset */ 196 bool sysctl_reset(sysctl_reset_e reset); 197 bool sysctl_set_reset_time(sysctl_reset_time_e reset, uint32_t tim0, uint32_t tim1, uint32_t tim2); 198 199 #endif