1 //***************************************************************************** 2 // 3 // hw_hibernate.h - Defines and Macros for the Hibernation module. 4 // 5 // Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_HIBERNATE_H__ 26 #define __HW_HIBERNATE_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the Hibernation module register addresses. 31 // 32 //***************************************************************************** 33 #define HIB_RTCC 0x400FC000 // Hibernation RTC Counter 34 #define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 35 #define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1 36 #define HIB_RTCLD 0x400FC00C // Hibernation RTC Load 37 #define HIB_CTL 0x400FC010 // Hibernation Control 38 #define HIB_IM 0x400FC014 // Hibernation Interrupt Mask 39 #define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status 40 #define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt 41 // Status 42 #define HIB_IC 0x400FC020 // Hibernation Interrupt Clear 43 #define HIB_RTCT 0x400FC024 // Hibernation RTC Trim 44 #define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds 45 #define HIB_DATA 0x400FC030 // Hibernation Data 46 47 //***************************************************************************** 48 // 49 // The following are defines for the bit fields in the HIB_RTCC register. 50 // 51 //***************************************************************************** 52 #define HIB_RTCC_M 0xFFFFFFFF // RTC Counter 53 #define HIB_RTCC_S 0 54 55 //***************************************************************************** 56 // 57 // The following are defines for the bit fields in the HIB_RTCM0 register. 58 // 59 //***************************************************************************** 60 #define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 61 #define HIB_RTCM0_S 0 62 63 //***************************************************************************** 64 // 65 // The following are defines for the bit fields in the HIB_RTCM1 register. 66 // 67 //***************************************************************************** 68 #define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1 69 #define HIB_RTCM1_S 0 70 71 //***************************************************************************** 72 // 73 // The following are defines for the bit fields in the HIB_RTCLD register. 74 // 75 //***************************************************************************** 76 #define HIB_RTCLD_M 0xFFFFFFFF // RTC Load 77 #define HIB_RTCLD_S 0 78 79 //***************************************************************************** 80 // 81 // The following are defines for the bit fields in the HIB_CTL register. 82 // 83 //***************************************************************************** 84 #define HIB_CTL_WRC 0x80000000 // Write Complete/Capable 85 #define HIB_CTL_OSCHYS 0x00040000 // 32 86 #define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability 87 #define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass 88 #define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery 89 // Comparator 90 #define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts 91 #define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) 92 #define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts 93 #define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts 94 #define HIB_CTL_BATCHK 0x00000400 // Check Battery Status 95 #define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery 96 #define HIB_CTL_VDD3ON 0x00000100 // VDD Powered 97 #define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable 98 #define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable 99 #define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable 100 #define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable 101 #define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable 102 #define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select 103 #define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request 104 #define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable 105 106 //***************************************************************************** 107 // 108 // The following are defines for the bit fields in the HIB_IM register. 109 // 110 //***************************************************************************** 111 #define HIB_IM_WC 0x00000010 // External Write Complete/Capable 112 // Interrupt Mask 113 #define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask 114 #define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt 115 // Mask 116 #define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask 117 #define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask 118 119 //***************************************************************************** 120 // 121 // The following are defines for the bit fields in the HIB_RIS register. 122 // 123 //***************************************************************************** 124 #define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw 125 // Interrupt Status 126 #define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt 127 // Status 128 #define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw 129 // Interrupt Status 130 #define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status 131 #define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status 132 133 //***************************************************************************** 134 // 135 // The following are defines for the bit fields in the HIB_MIS register. 136 // 137 //***************************************************************************** 138 #define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked 139 // Interrupt Status 140 #define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked 141 // Interrupt Status 142 #define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked 143 // Interrupt Status 144 #define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt 145 // Status 146 #define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt 147 // Status 148 149 //***************************************************************************** 150 // 151 // The following are defines for the bit fields in the HIB_IC register. 152 // 153 //***************************************************************************** 154 #define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked 155 // Interrupt Clear 156 #define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked 157 // Interrupt Clear 158 #define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked 159 // Interrupt Clear 160 #define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt 161 // Clear 162 #define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt 163 // Clear 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the HIB_RTCT register. 168 // 169 //***************************************************************************** 170 #define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value 171 #define HIB_RTCT_TRIM_S 0 172 173 //***************************************************************************** 174 // 175 // The following are defines for the bit fields in the HIB_RTCSS register. 176 // 177 //***************************************************************************** 178 #define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match 179 #define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count 180 #define HIB_RTCSS_RTCSSM_S 16 181 #define HIB_RTCSS_RTCSSC_S 0 182 183 //***************************************************************************** 184 // 185 // The following are defines for the bit fields in the HIB_DATA register. 186 // 187 //***************************************************************************** 188 #define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data 189 #define HIB_DATA_RTD_S 0 190 191 //***************************************************************************** 192 // 193 // The following definitions are deprecated. 194 // 195 //***************************************************************************** 196 #ifndef DEPRECATED 197 198 //***************************************************************************** 199 // 200 // The following are deprecated defines for the Hibernation module register 201 // addresses. 202 // 203 //***************************************************************************** 204 #define HIB_DATA_END 0x400FC130 // end of data area, exclusive 205 206 //***************************************************************************** 207 // 208 // The following are deprecated defines for the bit fields in the HIB_RTCC 209 // register. 210 // 211 //***************************************************************************** 212 #define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask 213 214 //***************************************************************************** 215 // 216 // The following are deprecated defines for the bit fields in the HIB_RTCM0 217 // register. 218 // 219 //***************************************************************************** 220 #define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask 221 222 //***************************************************************************** 223 // 224 // The following are deprecated defines for the bit fields in the HIB_RTCM1 225 // register. 226 // 227 //***************************************************************************** 228 #define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask 229 230 //***************************************************************************** 231 // 232 // The following are deprecated defines for the bit fields in the HIB_RTCLD 233 // register. 234 // 235 //***************************************************************************** 236 #define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask 237 238 //***************************************************************************** 239 // 240 // The following are deprecated defines for the bit fields in the HIB_RIS 241 // register. 242 // 243 //***************************************************************************** 244 #define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt 245 246 //***************************************************************************** 247 // 248 // The following are deprecated defines for the bit fields in the HIB_MIS 249 // register. 250 // 251 //***************************************************************************** 252 #define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt 253 254 //***************************************************************************** 255 // 256 // The following are deprecated defines for the bit fields in the HIB_RTCT 257 // register. 258 // 259 //***************************************************************************** 260 #define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask 261 262 //***************************************************************************** 263 // 264 // The following are deprecated defines for the bit fields in the HIB_DATA 265 // register. 266 // 267 //***************************************************************************** 268 #define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask 269 270 #endif 271 272 #endif // __HW_HIBERNATE_H__ 273