1 //***************************************************************************** 2 // 3 // hw_lpc.h - Macros used when accessing the LPC hardware. 4 // 5 // Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_LPC_H__ 26 #define __HW_LPC_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the LPC register addresses. 31 // 32 //***************************************************************************** 33 #define LPC_O_CTL 0x00000000 // LPC Control 34 #define LPC_O_STS 0x00000004 // LPC Status 35 #define LPC_O_IRQCTL 0x00000008 // LPC IRQ Control 36 #define LPC_O_IRQST 0x0000000C // LPC IRQ Status 37 #define LPC_O_CH0CTL 0x00000010 // LPC Channel 0 Control 38 #define LPC_O_CH0ST 0x00000014 // LPC Channel 0 Status 39 #define LPC_O_CH0ADR 0x00000018 // LPC Channel 0 Address 40 #define LPC_O_CH1CTL 0x00000020 // LPC Channel 1 Control 41 #define LPC_O_CH1ST 0x00000024 // LPC Channel 1 Status 42 #define LPC_O_CH1ADR 0x00000028 // LPC Channel 1 Address 43 #define LPC_O_CH2CTL 0x00000030 // LPC Channel 2 Control 44 #define LPC_O_CH2ST 0x00000034 // LPC Channel 2 Status 45 #define LPC_O_CH2ADR 0x00000038 // LPC Channel 2 Address 46 #define LPC_O_CH3CTL 0x00000040 // LPC Channel 3 Control 47 #define LPC_O_CH3ST 0x00000044 // LPC Channel 3 Status 48 #define LPC_O_CH3ADR 0x00000048 // LPC Channel 3 Address 49 #define LPC_O_CH4CTL 0x00000050 // LPC Channel 4 Control 50 #define LPC_O_CH4ST 0x00000054 // LPC Channel 4 Status 51 #define LPC_O_CH4ADR 0x00000058 // LPC Channel 4 Address 52 #define LPC_O_CH5CTL 0x00000060 // LPC Channel 5 Control 53 #define LPC_O_CH5ST 0x00000064 // LPC Channel 5 Status 54 #define LPC_O_CH5ADR 0x00000068 // LPC Channel 5 Address 55 #define LPC_O_CH6CTL 0x00000070 // LPC Channel 6 Control 56 #define LPC_O_CH6ST 0x00000074 // LPC Channel 6 Status 57 #define LPC_O_CH6ADR 0x00000078 // LPC Channel 6 Address 58 #define LPC_O_CH7CTL 0x00000080 // LPC Channel 7 / COMx Control 59 #define LPC_O_CH7ST 0x00000084 // LPC Channel 7 / COMx Status 60 #define LPC_O_CH7ADR 0x00000088 // LPC Channel 7 / COMx Address 61 #define LPC_O_STSADDR 0x000000A0 // LPC Status Block Address 62 #define LPC_O_IM 0x00000100 // LPC Interrupt Mask 63 #define LPC_O_RIS 0x00000104 // LPC Raw Interrupt Status 64 #define LPC_O_MIS 0x00000108 // LPC Masked Interrupt Status 65 #define LPC_O_IC 0x0000010C // LPC Interrupt Clear 66 #define LPC_O_DMACX 0x00000120 // LPC DMA and COMx Control 67 #define LPC_O_POOL 0x00000400 // LPC Register Pool 68 #define LPC_O_PP 0x00000FC0 // LPC Peripheral Properties 69 70 //***************************************************************************** 71 // 72 // The following are defines for the bit fields in the LPC_O_CTL register. 73 // 74 //***************************************************************************** 75 #define LPC_CTL_SCICNT_M 0x00000C00 // LPC0SCI Pulse Length 76 #define LPC_CTL_SCICNT_0 0x00000000 // No pulse occurs on the LPC0SCI 77 // pin 78 #define LPC_CTL_SCICNT_2 0x00000400 // The pulse on the LPC0SCI pin is 79 // 2 LPC0CLK periods 80 #define LPC_CTL_SCICNT_4 0x00000800 // The pulse on the LPC0SCI pin is 81 // 4 LPC0CLK periods 82 #define LPC_CTL_SCICNT_8 0x00000C00 // The pulse on the LPC0SCI pin is 83 // 8 LPC0CLK periods 84 #define LPC_CTL_SCI 0x00000200 // Start SCI Pulse 85 #define LPC_CTL_WAKE 0x00000100 // Restart the LPC Bus 86 #define LPC_CTL_CE7 0x00000080 // Enable Channel 7 87 #define LPC_CTL_CE6 0x00000040 // Enable Channel 6 88 #define LPC_CTL_CE5 0x00000020 // Enable Channel 5 89 #define LPC_CTL_CE4 0x00000010 // Enable Channel 4 90 #define LPC_CTL_CE3 0x00000008 // Enable Channel 3 91 #define LPC_CTL_CE2 0x00000004 // Enable Channel 2 92 #define LPC_CTL_CE1 0x00000002 // Enable Channel 1 93 #define LPC_CTL_CE0 0x00000001 // Enable Channel 0 94 95 //***************************************************************************** 96 // 97 // The following are defines for the bit fields in the LPC_O_STS register. 98 // 99 //***************************************************************************** 100 #define LPC_STS_CHCNT_M 0x00700000 // Number of Channels 101 #define LPC_STS_POOLSZ_M 0x00070000 // Register Pool Size 102 #define LPC_STS_POOLSZ_256 0x00010000 // 256 bytes 103 #define LPC_STS_POOLSZ_512 0x00020000 // 512 bytes 104 #define LPC_STS_POOLSZ_768 0x00030000 // 768 bytes 105 #define LPC_STS_POOLSZ_1024 0x00040000 // 1024 bytes 106 #define LPC_STS_RST 0x00000400 // LPC is in Reset 107 #define LPC_STS_BUSY 0x00000200 // LPC is Busy 108 #define LPC_STS_SLEEP 0x00000100 // LPC is in Sleep Mode 109 #define LPC_STS_CA7 0x00000080 // Channel 7 Active 110 #define LPC_STS_CA6 0x00000040 // Channel 6 Active 111 #define LPC_STS_CA5 0x00000020 // Channel 5 Active 112 #define LPC_STS_CA4 0x00000010 // Channel 4 Active 113 #define LPC_STS_CA3 0x00000008 // Channel 3 Active 114 #define LPC_STS_CA2 0x00000004 // Channel 2 Active 115 #define LPC_STS_CA1 0x00000002 // Channel 1 Active 116 #define LPC_STS_CA0 0x00000001 // Channel 0 Active 117 #define LPC_STS_CHCNT_S 20 118 119 //***************************************************************************** 120 // 121 // The following are defines for the bit fields in the LPC_O_IRQCTL register. 122 // 123 //***************************************************************************** 124 #define LPC_IRQCTL_I15 0x80000000 // Manual IRQ15 State 125 #define LPC_IRQCTL_I14 0x40000000 // Manual IRQ14 State 126 #define LPC_IRQCTL_I13 0x20000000 // Manual IRQ13 State 127 #define LPC_IRQCTL_I12 0x10000000 // Manual IRQ12 State 128 #define LPC_IRQCTL_I11 0x08000000 // Manual IRQ11 State 129 #define LPC_IRQCTL_I10 0x04000000 // Manual IRQ10 State 130 #define LPC_IRQCTL_I9 0x02000000 // Manual IRQ9 State 131 #define LPC_IRQCTL_I8 0x01000000 // Manual IRQ8 State 132 #define LPC_IRQCTL_I7 0x00800000 // Manual IRQ7 State 133 #define LPC_IRQCTL_I6 0x00400000 // Manual IRQ6 State 134 #define LPC_IRQCTL_I5 0x00200000 // Manual IRQ5 State 135 #define LPC_IRQCTL_I4 0x00100000 // Manual IRQ4 State 136 #define LPC_IRQCTL_I3 0x00080000 // Manual IRQ3 State 137 #define LPC_IRQCTL_I2 0x00040000 // Manual IRQ2 State 138 #define LPC_IRQCTL_I1 0x00020000 // Manual IRQ1 State 139 #define LPC_IRQCTL_AH 0x00010000 // Active High Control 140 #define LPC_IRQCTL_PULSE 0x00000004 // Pulse IRQ States 141 #define LPC_IRQCTL_ONCHG 0x00000002 // Initiate on Change 142 #define LPC_IRQCTL_SND 0x00000001 // Initiate Immediately 143 144 //***************************************************************************** 145 // 146 // The following are defines for the bit fields in the LPC_O_IRQST register. 147 // 148 //***************************************************************************** 149 #define LPC_IRQST_I15 0x80000000 // Host IRQ15 State 150 #define LPC_IRQST_I14 0x40000000 // IRQ14 State 151 #define LPC_IRQST_I13 0x20000000 // IRQ13 State 152 #define LPC_IRQST_I12 0x10000000 // IRQ12 State 153 #define LPC_IRQST_I11 0x08000000 // IRQ11 State 154 #define LPC_IRQST_I10 0x04000000 // IRQ10 State 155 #define LPC_IRQST_I9 0x02000000 // IRQ9 State 156 #define LPC_IRQST_I8 0x01000000 // IRQ8 State 157 #define LPC_IRQST_I7 0x00800000 // IRQ7 State 158 #define LPC_IRQST_I6 0x00400000 // IRQ6 State 159 #define LPC_IRQST_I5 0x00200000 // IRQ5 State 160 #define LPC_IRQST_I4 0x00100000 // IRQ4 State 161 #define LPC_IRQST_I3 0x00080000 // IRQ3 State 162 #define LPC_IRQST_I2 0x00040000 // IRQ2 State 163 #define LPC_IRQST_I1 0x00020000 // IRQ1 State 164 #define LPC_IRQST_I0 0x00010000 // IRQ0 State 165 #define LPC_IRQST_SIRQ 0x00000004 // Pulse IRQ States 166 #define LPC_IRQST_CONT 0x00000001 // Initiate Immediately 167 168 //***************************************************************************** 169 // 170 // The following are defines for the bit fields in the LPC_O_CH0CTL register. 171 // 172 //***************************************************************************** 173 #define LPC_CH0CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 174 #define LPC_CH0CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 175 #define LPC_CH0CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 176 #define LPC_CH0CTL_IRQEN2 0x00080000 // IRQ Enable 2 177 #define LPC_CH0CTL_CX 0x00080000 // IRQ Enable 2 178 #define LPC_CH0CTL_IRQEN1 0x00040000 // IRQ Enable 1 179 #define LPC_CH0CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 180 #define LPC_CH0CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 181 #define LPC_CH0CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 182 #define LPC_CH0CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 183 #define LPC_CH0CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 184 #define LPC_CH0CTL_ARBDIS 0x00008000 // Arbitration Disabled 185 #define LPC_CH0CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 186 #define LPC_CH0CTL_AMASK_M 0x0000001C // Address Mask for Ranges 187 #define LPC_CH0CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 188 // size of 4 bytes for an endpoint 189 // range or used for single 190 // endpoints 191 #define LPC_CH0CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 192 // size of 8 bytes 193 #define LPC_CH0CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 194 // size of 16 bytes 195 #define LPC_CH0CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 196 // size of 32 bytes 197 #define LPC_CH0CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 198 // size of 64 bytes 199 #define LPC_CH0CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 200 // size of 128 bytes 201 #define LPC_CH0CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 202 // size of 256 bytes 203 #define LPC_CH0CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 204 // size of 512 bytes 205 #define LPC_CH0CTL_TYPE 0x00000001 // Channel Type 206 #define LPC_CH0CTL_IRQSEL2_S 28 207 #define LPC_CH0CTL_IRQSEL1_S 24 208 #define LPC_CH0CTL_IRQSEL0_S 20 209 #define LPC_CH0CTL_OFFSET_S 5 210 211 //***************************************************************************** 212 // 213 // The following are defines for the bit fields in the LPC_O_CH0ST register. 214 // 215 //***************************************************************************** 216 #define LPC_CH0ST_USER_M 0x00001F00 // User Data 217 #define LPC_CH0ST_LASTHW 0x00000080 // Last Host Write 218 #define LPC_CH0ST_HW1ST 0x00000040 // First Host Write 219 #define LPC_CH0ST_LASTSW 0x00000020 // Last Slave Write 220 #define LPC_CH0ST_SW1ST 0x00000010 // First Slave Write 221 #define LPC_CH0ST_CMD 0x00000008 // Command or Data 222 #define LPC_CH0ST_FRMH 0x00000002 // From-Host Transaction 223 #define LPC_CH0ST_TOH 0x00000001 // To-Host Transaction 224 #define LPC_CH0ST_USER_S 8 225 226 //***************************************************************************** 227 // 228 // The following are defines for the bit fields in the LPC_O_CH0ADR register. 229 // 230 //***************************************************************************** 231 #define LPC_CH0ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 232 #define LPC_CH0ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 233 #define LPC_CH0ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 234 #define LPC_CH0ADR_ADDRH_S 16 235 #define LPC_CH0ADR_ADDRL_S 3 236 237 //***************************************************************************** 238 // 239 // The following are defines for the bit fields in the LPC_O_CH1CTL register. 240 // 241 //***************************************************************************** 242 #define LPC_CH1CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 243 #define LPC_CH1CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 244 #define LPC_CH1CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 245 #define LPC_CH1CTL_IRQEN2 0x00080000 // IRQ Enable 2 246 #define LPC_CH1CTL_CX 0x00080000 // IRQ Enable 2 247 #define LPC_CH1CTL_IRQEN1 0x00040000 // IRQ Enable 1 248 #define LPC_CH1CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 249 #define LPC_CH1CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 250 #define LPC_CH1CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 251 #define LPC_CH1CTL_IRQEN0_TRGI2 0x00020000 // Trigger 2 252 #define LPC_CH1CTL_IRQEN0_TRGI3 0x00030000 // Trigger 3 253 #define LPC_CH1CTL_ARBDIS 0x00008000 // Arbitration Disabled 254 #define LPC_CH1CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 255 #define LPC_CH1CTL_AMASK_M 0x0000001C // Address Mask for Ranges 256 #define LPC_CH1CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 257 // size of 4 bytes for an endpoint 258 // range or used for single 259 // endpoints 260 #define LPC_CH1CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 261 // size of 8 bytes 262 #define LPC_CH1CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 263 // size of 16 bytes 264 #define LPC_CH1CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 265 // size of 32 bytes 266 #define LPC_CH1CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 267 // size of 64 bytes 268 #define LPC_CH1CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 269 // size of 128 bytes 270 #define LPC_CH1CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 271 // size of 256 bytes 272 #define LPC_CH1CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 273 // size of 512 bytes 274 #define LPC_CH1CTL_TYPE 0x00000001 // Channel Type 275 #define LPC_CH1CTL_IRQSEL2_S 28 276 #define LPC_CH1CTL_IRQSEL1_S 24 277 #define LPC_CH1CTL_IRQSEL0_S 20 278 #define LPC_CH1CTL_OFFSET_S 5 279 280 //***************************************************************************** 281 // 282 // The following are defines for the bit fields in the LPC_O_CH1ST register. 283 // 284 //***************************************************************************** 285 #define LPC_CH1ST_USER_M 0x00001F00 // User Data 286 #define LPC_CH1ST_LASTHW 0x00000080 // Last Host Write 287 #define LPC_CH1ST_HW1ST 0x00000040 // First Host Write 288 #define LPC_CH1ST_LASTSW 0x00000020 // Last Slave Write 289 #define LPC_CH1ST_SW1ST 0x00000010 // First Slave Write 290 #define LPC_CH1ST_CMD 0x00000008 // Command or Data 291 #define LPC_CH1ST_FRMH 0x00000002 // From-Host Transaction 292 #define LPC_CH1ST_TOH 0x00000001 // To-Host Transaction 293 #define LPC_CH1ST_USER_S 8 294 295 //***************************************************************************** 296 // 297 // The following are defines for the bit fields in the LPC_O_CH1ADR register. 298 // 299 //***************************************************************************** 300 #define LPC_CH1ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 301 #define LPC_CH1ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 302 #define LPC_CH1ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 303 #define LPC_CH1ADR_ADDRH_S 16 304 #define LPC_CH1ADR_ADDRL_S 3 305 306 //***************************************************************************** 307 // 308 // The following are defines for the bit fields in the LPC_O_CH2CTL register. 309 // 310 //***************************************************************************** 311 #define LPC_CH2CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 312 #define LPC_CH2CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 313 #define LPC_CH2CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 314 #define LPC_CH2CTL_CX 0x00080000 // IRQ Enable 2 315 #define LPC_CH2CTL_IRQEN2 0x00080000 // IRQ Enable 2 316 #define LPC_CH2CTL_IRQEN1 0x00040000 // IRQ Enable 1 317 #define LPC_CH2CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 318 #define LPC_CH2CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 319 #define LPC_CH2CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 320 #define LPC_CH2CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 321 #define LPC_CH2CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 322 #define LPC_CH2CTL_ARBDIS 0x00008000 // Arbitration Disabled 323 #define LPC_CH2CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 324 #define LPC_CH2CTL_AMASK_M 0x0000001C // Address Mask for Ranges 325 #define LPC_CH2CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 326 // size of 4 bytes for an endpoint 327 // range or used for single 328 // endpoints 329 #define LPC_CH2CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 330 // size of 8 bytes 331 #define LPC_CH2CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 332 // size of 16 bytes 333 #define LPC_CH2CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 334 // size of 32 bytes 335 #define LPC_CH2CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 336 // size of 64 bytes 337 #define LPC_CH2CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 338 // size of 128 bytes 339 #define LPC_CH2CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 340 // size of 256 bytes 341 #define LPC_CH2CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 342 // size of 512 bytes 343 #define LPC_CH2CTL_TYPE 0x00000001 // Channel Type 344 #define LPC_CH2CTL_IRQSEL2_S 28 345 #define LPC_CH2CTL_IRQSEL1_S 24 346 #define LPC_CH2CTL_IRQSEL0_S 20 347 #define LPC_CH2CTL_OFFSET_S 5 348 349 //***************************************************************************** 350 // 351 // The following are defines for the bit fields in the LPC_O_CH2ST register. 352 // 353 //***************************************************************************** 354 #define LPC_CH2ST_USER_M 0x00001F00 // User Data 355 #define LPC_CH2ST_LASTHW 0x00000080 // Last Host Write 356 #define LPC_CH2ST_HW1ST 0x00000040 // First Host Write 357 #define LPC_CH2ST_LASTSW 0x00000020 // Last Slave Write 358 #define LPC_CH2ST_SW1ST 0x00000010 // First Slave Write 359 #define LPC_CH2ST_CMD 0x00000008 // Command or Data 360 #define LPC_CH2ST_FRMH 0x00000002 // From-Host Transaction 361 #define LPC_CH2ST_TOH 0x00000001 // To-Host Transaction 362 #define LPC_CH2ST_USER_S 8 363 364 //***************************************************************************** 365 // 366 // The following are defines for the bit fields in the LPC_O_CH2ADR register. 367 // 368 //***************************************************************************** 369 #define LPC_CH2ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 370 #define LPC_CH2ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 371 #define LPC_CH2ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 372 #define LPC_CH2ADR_ADDRH_S 16 373 #define LPC_CH2ADR_ADDRL_S 3 374 375 //***************************************************************************** 376 // 377 // The following are defines for the bit fields in the LPC_O_CH3CTL register. 378 // 379 //***************************************************************************** 380 #define LPC_CH3CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 381 #define LPC_CH3CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 382 #define LPC_CH3CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 383 #define LPC_CH3CTL_IRQEN2 0x00080000 // IRQ Enable 2 384 #define LPC_CH3CTL_CX 0x00080000 // IRQ Enable 2 385 #define LPC_CH3CTL_IRQEN1 0x00040000 // IRQ Enable 1 386 #define LPC_CH3CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 387 #define LPC_CH3CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 388 #define LPC_CH3CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 389 #define LPC_CH3CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 390 #define LPC_CH3CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 391 #define LPC_CH3CTL_ARBDIS 0x00008000 // Arbitration Disabled 392 #define LPC_CH3CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 393 #define LPC_CH3CTL_AMASK_M 0x0000001C // Address Mask for Ranges 394 #define LPC_CH3CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 395 // size of 4 bytes for an endpoint 396 // range or used for single 397 // endpoints 398 #define LPC_CH3CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 399 // size of 8 bytes 400 #define LPC_CH3CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 401 // size of 16 bytes 402 #define LPC_CH3CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 403 // size of 32 bytes 404 #define LPC_CH3CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 405 // size of 64 bytes 406 #define LPC_CH3CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 407 // size of 128 bytes 408 #define LPC_CH3CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 409 // size of 256 bytes 410 #define LPC_CH3CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 411 // size of 512 bytes 412 #define LPC_CH3CTL_TYPE 0x00000001 // Channel Type 413 #define LPC_CH3CTL_IRQSEL2_S 28 414 #define LPC_CH3CTL_IRQSEL1_S 24 415 #define LPC_CH3CTL_IRQSEL0_S 20 416 #define LPC_CH3CTL_OFFSET_S 5 417 418 //***************************************************************************** 419 // 420 // The following are defines for the bit fields in the LPC_O_CH3ST register. 421 // 422 //***************************************************************************** 423 #define LPC_CH3ST_USER_M 0x00001F00 // User Data 424 #define LPC_CH3ST_LASTHW 0x00000080 // Last Host Write 425 #define LPC_CH3ST_HW1ST 0x00000040 // First Host Write 426 #define LPC_CH3ST_LASTSW 0x00000020 // Last Slave Write 427 #define LPC_CH3ST_SW1ST 0x00000010 // First Slave Write 428 #define LPC_CH3ST_CMD 0x00000008 // Command or Data 429 #define LPC_CH3ST_FRMH 0x00000002 // From-Host Transaction 430 #define LPC_CH3ST_TOH 0x00000001 // To-Host Transaction 431 #define LPC_CH3ST_USER_S 8 432 433 //***************************************************************************** 434 // 435 // The following are defines for the bit fields in the LPC_O_CH3ADR register. 436 // 437 //***************************************************************************** 438 #define LPC_CH3ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 439 #define LPC_CH3ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 440 #define LPC_CH3ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1 441 #define LPC_CH3ADR_ADDRH_S 16 442 #define LPC_CH3ADR_ADDRL_S 3 443 444 //***************************************************************************** 445 // 446 // The following are defines for the bit fields in the LPC_O_CH4CTL register. 447 // 448 //***************************************************************************** 449 #define LPC_CH4CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 450 #define LPC_CH4CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 451 #define LPC_CH4CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 452 #define LPC_CH4CTL_CX 0x00080000 // IRQ Enable 2 453 #define LPC_CH4CTL_IRQEN2 0x00080000 // IRQ Enable 2 454 #define LPC_CH4CTL_IRQEN1 0x00040000 // IRQ Enable 1 455 #define LPC_CH4CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 456 #define LPC_CH4CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 457 #define LPC_CH4CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 458 #define LPC_CH4CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 459 #define LPC_CH4CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 460 #define LPC_CH4CTL_ARBDIS 0x00008000 // Arbitration Disabled 461 #define LPC_CH4CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 462 #define LPC_CH4CTL_AMASK_M 0x0000001C // Address Mask for Ranges 463 #define LPC_CH4CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 464 // size of 4 bytes for an endpoint 465 // range or used for single 466 // endpoints 467 #define LPC_CH4CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 468 // size of 8 bytes 469 #define LPC_CH4CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 470 // size of 16 bytes 471 #define LPC_CH4CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 472 // size of 32 bytes 473 #define LPC_CH4CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 474 // size of 64 bytes 475 #define LPC_CH4CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 476 // size of 128 bytes 477 #define LPC_CH4CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 478 // size of 256 bytes 479 #define LPC_CH4CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 480 // size of 512 bytes 481 #define LPC_CH4CTL_TYPE 0x00000001 // Channel Type 482 #define LPC_CH4CTL_IRQSEL2_S 28 483 #define LPC_CH4CTL_IRQSEL1_S 24 484 #define LPC_CH4CTL_IRQSEL0_S 20 485 #define LPC_CH4CTL_OFFSET_S 5 486 487 //***************************************************************************** 488 // 489 // The following are defines for the bit fields in the LPC_O_CH4ST register. 490 // 491 //***************************************************************************** 492 #define LPC_CH4ST_USER_M 0x00001F00 // User Data 493 #define LPC_CH4ST_LASTHW 0x00000080 // Last Host Write 494 #define LPC_CH4ST_HW1ST 0x00000040 // First Host Write 495 #define LPC_CH4ST_LASTSW 0x00000020 // Last Slave Write 496 #define LPC_CH4ST_SW1ST 0x00000010 // First Slave Write 497 #define LPC_CH4ST_CMD 0x00000008 // Command or Data 498 #define LPC_CH4ST_FRMH 0x00000002 // From-Host Transaction 499 #define LPC_CH4ST_TOH 0x00000001 // To-Host Transaction 500 #define LPC_CH4ST_USER_S 8 501 502 //***************************************************************************** 503 // 504 // The following are defines for the bit fields in the LPC_O_CH4ADR register. 505 // 506 //***************************************************************************** 507 #define LPC_CH4ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 508 #define LPC_CH4ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 509 #define LPC_CH4ADR_ADDRH_S 16 510 #define LPC_CH4ADR_ADDRL_S 3 511 512 //***************************************************************************** 513 // 514 // The following are defines for the bit fields in the LPC_O_CH5CTL register. 515 // 516 //***************************************************************************** 517 #define LPC_CH5CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 518 #define LPC_CH5CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 519 #define LPC_CH5CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 520 #define LPC_CH5CTL_IRQEN2 0x00080000 // IRQ Enable 2 521 #define LPC_CH5CTL_CX 0x00080000 // IRQ Enable 2 522 #define LPC_CH5CTL_IRQEN1 0x00040000 // IRQ Enable 1 523 #define LPC_CH5CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 524 #define LPC_CH5CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 525 #define LPC_CH5CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 526 #define LPC_CH5CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 527 #define LPC_CH5CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 528 #define LPC_CH5CTL_ARBDIS 0x00008000 // Arbitration Disabled 529 #define LPC_CH5CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 530 #define LPC_CH5CTL_AMASK_M 0x0000001C // Address Mask for Ranges 531 #define LPC_CH5CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 532 // size of 4 bytes for an endpoint 533 // range or used for single 534 // endpoints 535 #define LPC_CH5CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 536 // size of 8 bytes 537 #define LPC_CH5CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 538 // size of 16 bytes 539 #define LPC_CH5CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 540 // size of 32 bytes 541 #define LPC_CH5CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 542 // size of 64 bytes 543 #define LPC_CH5CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 544 // size of 128 bytes 545 #define LPC_CH5CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 546 // size of 256 bytes 547 #define LPC_CH5CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 548 // size of 512 bytes 549 #define LPC_CH5CTL_TYPE 0x00000001 // Channel Type 550 #define LPC_CH5CTL_IRQSEL2_S 28 551 #define LPC_CH5CTL_IRQSEL1_S 24 552 #define LPC_CH5CTL_IRQSEL0_S 20 553 #define LPC_CH5CTL_OFFSET_S 5 554 555 //***************************************************************************** 556 // 557 // The following are defines for the bit fields in the LPC_O_CH5ST register. 558 // 559 //***************************************************************************** 560 #define LPC_CH5ST_USER_M 0x00001F00 // User Data 561 #define LPC_CH5ST_LASTHW 0x00000080 // Last Host Write 562 #define LPC_CH5ST_HW1ST 0x00000040 // First Host Write 563 #define LPC_CH5ST_LASTSW 0x00000020 // Last Slave Write 564 #define LPC_CH5ST_SW1ST 0x00000010 // First Slave Write 565 #define LPC_CH5ST_CMD 0x00000008 // Command or Data 566 #define LPC_CH5ST_FRMH 0x00000002 // From-Host Transaction 567 #define LPC_CH5ST_TOH 0x00000001 // To-Host Transaction 568 #define LPC_CH5ST_USER_S 8 569 570 //***************************************************************************** 571 // 572 // The following are defines for the bit fields in the LPC_O_CH5ADR register. 573 // 574 //***************************************************************************** 575 #define LPC_CH5ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 576 #define LPC_CH5ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 577 #define LPC_CH5ADR_ADDRH_S 16 578 #define LPC_CH5ADR_ADDRL_S 3 579 580 //***************************************************************************** 581 // 582 // The following are defines for the bit fields in the LPC_O_CH6CTL register. 583 // 584 //***************************************************************************** 585 #define LPC_CH6CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 586 #define LPC_CH6CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 587 #define LPC_CH6CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 588 #define LPC_CH6CTL_CX 0x00080000 // IRQ Enable 2 589 #define LPC_CH6CTL_IRQEN2 0x00080000 // IRQ Enable 2 590 #define LPC_CH6CTL_IRQEN1 0x00040000 // IRQ Enable 1 591 #define LPC_CH6CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 592 #define LPC_CH6CTL_IRQEN0_DIS 0x00000000 // Trigger disabled 593 #define LPC_CH6CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1 594 #define LPC_CH6CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2 595 #define LPC_CH6CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 596 #define LPC_CH6CTL_ARBDIS 0x00008000 // Arbitration Disabled 597 #define LPC_CH6CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 598 #define LPC_CH6CTL_AMASK_M 0x0000001C // Address Mask for Ranges 599 #define LPC_CH6CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 600 // size of 4 bytes for an endpoint 601 // range or used for single 602 // endpoints 603 #define LPC_CH6CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 604 // size of 8 bytes 605 #define LPC_CH6CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 606 // size of 16 bytes 607 #define LPC_CH6CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 608 // size of 32 bytes 609 #define LPC_CH6CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 610 // size of 64 bytes 611 #define LPC_CH6CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 612 // size of 128 bytes 613 #define LPC_CH6CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 614 // size of 256 bytes 615 #define LPC_CH6CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 616 // size of 512 bytes 617 #define LPC_CH6CTL_TYPE 0x00000001 // Channel Type 618 #define LPC_CH6CTL_IRQSEL2_S 28 619 #define LPC_CH6CTL_IRQSEL1_S 24 620 #define LPC_CH6CTL_IRQSEL0_S 20 621 #define LPC_CH6CTL_OFFSET_S 5 622 623 //***************************************************************************** 624 // 625 // The following are defines for the bit fields in the LPC_O_CH6ST register. 626 // 627 //***************************************************************************** 628 #define LPC_CH6ST_USER_M 0x00001F00 // User Data 629 #define LPC_CH6ST_LASTHW 0x00000080 // Last Host Write 630 #define LPC_CH6ST_HW1ST 0x00000040 // First Host Write 631 #define LPC_CH6ST_LASTSW 0x00000020 // Last Slave Write 632 #define LPC_CH6ST_SW1ST 0x00000010 // First Slave Write 633 #define LPC_CH6ST_CMD 0x00000008 // Command or Data 634 #define LPC_CH6ST_FRMH 0x00000002 // From-Host Transaction 635 #define LPC_CH6ST_TOH 0x00000001 // To-Host Transaction 636 #define LPC_CH6ST_USER_S 8 637 638 //***************************************************************************** 639 // 640 // The following are defines for the bit fields in the LPC_O_CH6ADR register. 641 // 642 //***************************************************************************** 643 #define LPC_CH6ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 644 #define LPC_CH6ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 645 #define LPC_CH6ADR_ADDRH_S 16 646 #define LPC_CH6ADR_ADDRL_S 3 647 648 //***************************************************************************** 649 // 650 // The following are defines for the bit fields in the LPC_O_CH7CTL register. 651 // 652 //***************************************************************************** 653 #define LPC_CH7CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2 654 #define LPC_CH7CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1 655 #define LPC_CH7CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0 656 #define LPC_CH7CTL_CX 0x00080000 // IRQ Enable 2 657 #define LPC_CH7CTL_IRQEN2 0x00080000 // IRQ Enable 2 658 #define LPC_CH7CTL_IRQEN1 0x00040000 // IRQ Enable 1 659 #define LPC_CH7CTL_IRQEN0_M 0x00030000 // IRQ Enable 0 660 #define LPC_CH7CTL_IRQEN0_AUTO 0x00000000 // The automatic IRQ trigger is 661 // disabled 662 #define LPC_CH7CTL_IRQEN0_MST 0x00010000 // If TYPE is set, the IRQ selected 663 // by IRQSEL0 is triggered when the 664 // master wins arbitration (the 665 // HW1ST bit is set) 666 #define LPC_CH7CTL_IRQEN0_SLV 0x00020000 // If TYPE is set, the IRQ selected 667 // by IRQSEL0 is triggered when the 668 // slave wins arbitration (the 669 // SW1ST bit is set) 670 #define LPC_CH7CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3 671 #define LPC_CH7CTL_ARBDIS 0x00008000 // Arbitration Disabled 672 #define LPC_CH7CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool 673 #define LPC_CH7CTL_AMASK_M 0x0000001C // Address Mask for Ranges 674 #define LPC_CH7CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox 675 // size of 4 bytes for an endpoint 676 // range or used for single 677 // endpoints 678 #define LPC_CH7CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox 679 // size of 8 bytes 680 #define LPC_CH7CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox 681 // size of 16 bytes 682 #define LPC_CH7CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox 683 // size of 32 bytes 684 #define LPC_CH7CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox 685 // size of 64 bytes 686 #define LPC_CH7CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox 687 // size of 128 bytes 688 #define LPC_CH7CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox 689 // size of 256 bytes 690 #define LPC_CH7CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox 691 // size of 512 bytes 692 #define LPC_CH7CTL_TYPE 0x00000001 // Channel Type 693 #define LPC_CH7CTL_IRQSEL2_S 28 694 #define LPC_CH7CTL_IRQSEL1_S 24 695 #define LPC_CH7CTL_IRQSEL0_S 20 696 #define LPC_CH7CTL_OFFSET_S 5 697 698 //***************************************************************************** 699 // 700 // The following are defines for the bit fields in the LPC_O_CH7ST register. 701 // 702 //***************************************************************************** 703 #define LPC_CH7ST_USER_M 0x00001F00 // User Data 704 #define LPC_CH7ST_LASTHW 0x00000080 // Last Host Write 705 #define LPC_CH7ST_HW1ST 0x00000040 // Host Wrote First 706 #define LPC_CH7ST_LASTSW 0x00000020 // Last Slave Write 707 #define LPC_CH7ST_SW1ST 0x00000010 // Slave Wrote First 708 #define LPC_CH7ST_CMD 0x00000008 // Command or Data 709 #define LPC_CH7ST_FRMH 0x00000002 // From-Host Transaction 710 #define LPC_CH7ST_TOH 0x00000001 // To-Host Transaction 711 #define LPC_CH7ST_USER_S 8 712 713 //***************************************************************************** 714 // 715 // The following are defines for the bit fields in the LPC_O_CH7ADR register. 716 // 717 //***************************************************************************** 718 #define LPC_CH7ADR_ADDRH_M 0xFFFF0000 // Upper Address Match 719 #define LPC_CH7ADR_ADDRL_M 0x0000FFF8 // Lower Address Match 720 #define LPC_CH7ADR_ADDRH_S 16 721 #define LPC_CH7ADR_ADDRL_S 3 722 723 //***************************************************************************** 724 // 725 // The following are defines for the bit fields in the LPC_O_STSADDR register. 726 // 727 //***************************************************************************** 728 #define LPC_STSADDR_ADDRH_M 0xFFFF0000 // Upper Address Match 729 #define LPC_STSADDR_ADDRL_M 0x0000FFF8 // Lower Address Match 730 #define LPC_STSADDR_ENA 0x00000001 // Enable Status Block 731 #define LPC_STSADDR_ADDRH_S 16 732 #define LPC_STSADDR_ADDRL_S 3 733 734 //***************************************************************************** 735 // 736 // The following are defines for the bit fields in the LPC_O_IM register. 737 // 738 //***************************************************************************** 739 #define LPC_IM_RSTIM 0x80000000 // Reset State Interrupt Mask 740 #define LPC_IM_SLEEPIM 0x40000000 // Sleep State Interrupt Mask 741 #define LPC_IM_COMXIM 0x20000000 // COMx Interrupt Mask 742 #define LPC_IM_SIRQIM 0x10000000 // SERIRQ Frame Complete Interrupt 743 // Mask 744 #define LPC_IM_CH6IM3 0x08000000 // Channel 6 Interrupt Mask 3 745 #define LPC_IM_CH6IM2 0x04000000 // Channel 6 Interrupt Mask 2 746 #define LPC_IM_CH6IM1 0x02000000 // Channel 6 Interrupt Mask 1 747 #define LPC_IM_CH6IM0 0x01000000 // Channel 6 Interrupt Mask 0 748 #define LPC_IM_CH5IM3 0x00800000 // Channel 5 Interrupt Mask 3 749 #define LPC_IM_CH5IM2 0x00400000 // Channel 5 Interrupt Mask 2 750 #define LPC_IM_CH5IM1 0x00200000 // Channel 5 Interrupt Mask 1 751 #define LPC_IM_CH5IM0 0x00100000 // Channel 5 Interrupt Mask 0 752 #define LPC_IM_CH4IM3 0x00080000 // Channel 4 Interrupt Mask 3 753 #define LPC_IM_CH4IM2 0x00040000 // Channel 4 Interrupt Mask 2 754 #define LPC_IM_CH4IM1 0x00020000 // Channel 4 Interrupt Mask 1 755 #define LPC_IM_CH4IM0 0x00010000 // Channel 4 Interrupt Mask 0 756 #define LPC_IM_CH3IM3 0x00008000 // Channel 3 Interrupt Mask 3 757 #define LPC_IM_CH3IM2 0x00004000 // Channel 3 Interrupt Mask 2 758 #define LPC_IM_CH3IM1 0x00002000 // Channel 3 Interrupt Mask 1 759 #define LPC_IM_CH3IM0 0x00001000 // Channel 3 Interrupt Mask 0 760 #define LPC_IM_CH2IM3 0x00000800 // Channel 2 Interrupt Mask 3 761 #define LPC_IM_CH2IM2 0x00000400 // Channel 2 Interrupt Mask 2 762 #define LPC_IM_CH2IM1 0x00000200 // Channel 2 Interrupt Mask 1 763 #define LPC_IM_CH2IM0 0x00000100 // Channel 2 Interrupt Mask 0 764 #define LPC_IM_CH1IM3 0x00000080 // Channel 1 Interrupt Mask 3 765 #define LPC_IM_CH1IM2 0x00000040 // Channel 1 Interrupt Mask 2 766 #define LPC_IM_CH1IM1 0x00000020 // Channel 1 Interrupt Mask 1 767 #define LPC_IM_CH1IM0 0x00000010 // Channel 1 Interrupt Mask 0 768 #define LPC_IM_CH0IM3 0x00000008 // Channel 0 Interrupt Mask 3 769 #define LPC_IM_CH0IM2 0x00000004 // Channel 0 Interrupt Mask 2 770 #define LPC_IM_CH0IM1 0x00000002 // Channel 0 Interrupt Mask 1 771 #define LPC_IM_CH0IM0 0x00000001 // Channel 0 Interrupt Mask 0 772 773 //***************************************************************************** 774 // 775 // The following are defines for the bit fields in the LPC_O_RIS register. 776 // 777 //***************************************************************************** 778 #define LPC_RIS_RSTRIS 0x80000000 // Reset State Raw Interrupt Status 779 #define LPC_RIS_SLEEPRIS 0x40000000 // Sleep State Raw Interrupt Status 780 #define LPC_RIS_COMXRIS 0x20000000 // COMx Raw Interrupt Status 781 #define LPC_RIS_SIRQRIS 0x10000000 // SERIRQ Frame Complete Raw 782 // Interrupt Status 783 #define LPC_RIS_CH6RIS3 0x08000000 // Channel 6 Raw Interrupt Status 3 784 #define LPC_RIS_CH6RIS2 0x04000000 // Channel 6 Raw Interrupt Status 2 785 #define LPC_RIS_CH6RIS1 0x02000000 // Channel 6 Raw Interrupt Status 1 786 #define LPC_RIS_CH6RIS0 0x01000000 // Channel 6 Raw Interrupt Status 0 787 #define LPC_RIS_CH5RIS3 0x00800000 // Channel 5 Raw Interrupt Status 3 788 #define LPC_RIS_CH5RIS2 0x00400000 // Channel 5 Raw Interrupt Status 2 789 #define LPC_RIS_CH5RIS1 0x00200000 // Channel 5 Raw Interrupt Status 1 790 #define LPC_RIS_CH5RIS0 0x00100000 // Channel 5 Raw Interrupt Status 0 791 #define LPC_RIS_CH4RIS3 0x00080000 // Channel 4 Raw Interrupt Status 3 792 #define LPC_RIS_CH4RIS2 0x00040000 // Channel 4 Raw Interrupt Status 2 793 #define LPC_RIS_CH4RIS1 0x00020000 // Channel 4 Raw Interrupt Status 1 794 #define LPC_RIS_CH4RIS0 0x00010000 // Channel 4 Raw Interrupt Status 0 795 #define LPC_RIS_CH3RIS3 0x00008000 // Channel 3 Raw Interrupt Status 3 796 #define LPC_RIS_CH3RIS2 0x00004000 // Channel 3 Raw Interrupt Status 2 797 #define LPC_RIS_CH3RIS1 0x00002000 // Channel 3 Raw Interrupt Status 1 798 #define LPC_RIS_CH3RIS0 0x00001000 // Channel 3 Raw Interrupt Status 0 799 #define LPC_RIS_CH2RIS3 0x00000800 // Channel 2 Raw Interrupt Status 3 800 #define LPC_RIS_CH2RIS2 0x00000400 // Channel 2 Raw Interrupt Status 2 801 #define LPC_RIS_CH2RIS1 0x00000200 // Channel 2 Raw Interrupt Status 1 802 #define LPC_RIS_CH2RIS0 0x00000100 // Channel 2 Raw Interrupt Status 0 803 #define LPC_RIS_CH1RIS3 0x00000080 // Channel 1 Raw Interrupt Status 3 804 #define LPC_RIS_CH1RIS2 0x00000040 // Channel 1 Raw Interrupt Status 2 805 #define LPC_RIS_CH1RIS1 0x00000020 // Channel 1 Raw Interrupt Status 1 806 #define LPC_RIS_CH1RIS0 0x00000010 // Channel 1 Raw Interrupt Status 0 807 #define LPC_RIS_CH0RIS3 0x00000008 // Channel 0 Raw Interrupt Status 3 808 #define LPC_RIS_CH0RIS2 0x00000004 // Channel 0 Raw Interrupt Status 2 809 #define LPC_RIS_CH0RIS1 0x00000002 // Channel 0 Raw Interrupt Status 1 810 #define LPC_RIS_CH0RIS0 0x00000001 // Channel 0 Raw Interrupt Status 0 811 812 //***************************************************************************** 813 // 814 // The following are defines for the bit fields in the LPC_O_MIS register. 815 // 816 //***************************************************************************** 817 #define LPC_MIS_RSTMIS 0x80000000 // Reset State Masked Interrupt 818 // Status 819 #define LPC_MIS_SLEEPMIS 0x40000000 // Sleep State Masked Interrupt 820 // Status 821 #define LPC_MIS_COMXMIS 0x20000000 // COMx Masked Interrupt Status 822 #define LPC_MIS_SIRQMIS 0x10000000 // SERIRQ Frame Complete Masked 823 // Interrupt Status 824 #define LPC_MIS_CH6MIS3 0x08000000 // Channel 6 Masked Interrupt 825 // Status 3 826 #define LPC_MIS_CH6MIS2 0x04000000 // Channel 6 Masked Interrupt 827 // Status 2 828 #define LPC_MIS_CH6MIS1 0x02000000 // Channel 6 Masked Interrupt 829 // Status 1 830 #define LPC_MIS_CH6MIS0 0x01000000 // Channel 6 Masked Interrupt 831 // Status 0 832 #define LPC_MIS_CH5MIS3 0x00800000 // Channel 5 Masked Interrupt 833 // Status 3 834 #define LPC_MIS_CH5MIS2 0x00400000 // Channel 5 Masked Interrupt 835 // Status 2 836 #define LPC_MIS_CH5MIS1 0x00200000 // Channel 5 Masked Interrupt 837 // Status 1 838 #define LPC_MIS_CH5MIS0 0x00100000 // Channel 5 Masked Interrupt 839 // Status 0 840 #define LPC_MIS_CH4MIS3 0x00080000 // Channel 4 Masked Interrupt 841 // Status 3 842 #define LPC_MIS_CH4MIS2 0x00040000 // Channel 4 Masked Interrupt 843 // Status 2 844 #define LPC_MIS_CH4MIS1 0x00020000 // Channel 4 Masked Interrupt 845 // Status 1 846 #define LPC_MIS_CH4MIS0 0x00010000 // Channel 4 Masked Interrupt 847 // Status 0 848 #define LPC_MIS_CH3MIS3 0x00008000 // Channel 3 Masked Interrupt 849 // Status 3 850 #define LPC_MIS_CH3MIS2 0x00004000 // Channel 3 Masked Interrupt 851 // Status 2 852 #define LPC_MIS_CH3MIS1 0x00002000 // Channel 3 Masked Interrupt 853 // Status 1 854 #define LPC_MIS_CH3MIS0 0x00001000 // Channel 3 Masked Interrupt 855 // Status 0 856 #define LPC_MIS_CH2MIS3 0x00000800 // Channel 2 Masked Interrupt 857 // Status 3 858 #define LPC_MIS_CH2MIS2 0x00000400 // Channel 2 Masked Interrupt 859 // Status 2 860 #define LPC_MIS_CH2MIS1 0x00000200 // Channel 2 Masked Interrupt 861 // Status 1 862 #define LPC_MIS_CH2MIS0 0x00000100 // Channel 2 Masked Interrupt 863 // Status 0 864 #define LPC_MIS_CH1MIS3 0x00000080 // Channel 1 Masked Interrupt 865 // Status 3 866 #define LPC_MIS_CH1MIS2 0x00000040 // Channel 1 Masked Interrupt 867 // Status 2 868 #define LPC_MIS_CH1MIS1 0x00000020 // Channel 1 Masked Interrupt 869 // Status 1 870 #define LPC_MIS_CH1MIS0 0x00000010 // Channel 1 Masked Interrupt 871 // Status 0 872 #define LPC_MIS_CH0MIS3 0x00000008 // Channel 0 Masked Interrupt 873 // Status 3 874 #define LPC_MIS_CH0MIS2 0x00000004 // Channel 0 Masked Interrupt 875 // Status 2 876 #define LPC_MIS_CH0MIS1 0x00000002 // Channel 0 Masked Interrupt 877 // Status 1 878 #define LPC_MIS_CH0MIS0 0x00000001 // Channel 0 Masked Interrupt 879 // Status 0 880 881 //***************************************************************************** 882 // 883 // The following are defines for the bit fields in the LPC_O_IC register. 884 // 885 //***************************************************************************** 886 #define LPC_IC_RSTIC 0x80000000 // Reset State Interrupt Clear 887 #define LPC_IC_SLEEPIC 0x40000000 // Sleep State Interrupt Clear 888 #define LPC_IC_COMXIC 0x20000000 // COMx Interrupt Clear 889 #define LPC_IC_SIRQRIC 0x10000000 // SERIRQ Frame Complete Interrupt 890 // Clear 891 #define LPC_IC_CH6IC3 0x08000000 // Channel 6 Interrupt Clear 3 892 #define LPC_IC_CH6IC2 0x04000000 // Channel 6 Interrupt Clear 2 893 #define LPC_IC_CH6IC1 0x02000000 // Channel 6 Interrupt Clear 1 894 #define LPC_IC_CH6IC0 0x01000000 // Channel 6 Interrupt Clear 0 895 #define LPC_IC_CH5IC3 0x00800000 // Channel 5 Interrupt Clear 3 896 #define LPC_IC_CH5IC2 0x00400000 // Channel 5 Interrupt Clear 2 897 #define LPC_IC_CH5IC1 0x00200000 // Channel 5 Interrupt Clear 1 898 #define LPC_IC_CH5IC0 0x00100000 // Channel 5 Interrupt Clear 0 899 #define LPC_IC_CH4IC3 0x00080000 // Channel 4 Interrupt Clear 3 900 #define LPC_IC_CH4IC2 0x00040000 // Channel 4 Interrupt Clear 2 901 #define LPC_IC_CH4IC1 0x00020000 // Channel 4 Interrupt Clear 1 902 #define LPC_IC_CH4IC0 0x00010000 // Channel 4 Interrupt Clear 0 903 #define LPC_IC_CH3IC3 0x00008000 // Channel 3 Interrupt Clear 3 904 #define LPC_IC_CH3IC2 0x00004000 // Channel 3 Interrupt Clear 2 905 #define LPC_IC_CH3IC1 0x00002000 // Channel 3 Interrupt Clear 1 906 #define LPC_IC_CH3IC0 0x00001000 // Channel 3 Interrupt Clear 0 907 #define LPC_IC_CH2IC3 0x00000800 // Channel 2 Interrupt Clear 3 908 #define LPC_IC_CH2IC2 0x00000400 // Channel 2 Interrupt Clear 2 909 #define LPC_IC_CH2IC1 0x00000200 // Channel 2 Interrupt Clear 1 910 #define LPC_IC_CH2IC0 0x00000100 // Channel 2 Interrupt Clear 0 911 #define LPC_IC_CH1IC3 0x00000080 // Channel 1 Interrupt Clear 3 912 #define LPC_IC_CH1IC2 0x00000040 // Channel 1 Interrupt Clear 2 913 #define LPC_IC_CH1IC1 0x00000020 // Channel 1 Interrupt Clear 1 914 #define LPC_IC_CH1IC0 0x00000010 // Channel 1 Interrupt Clear 0 915 #define LPC_IC_CH0IC3 0x00000008 // Channel 0 Interrupt Clear 3 916 #define LPC_IC_CH0IC2 0x00000004 // Channel 0 Interrupt Clear 2 917 #define LPC_IC_CH0IC1 0x00000002 // Channel 0 Interrupt Clear 1 918 #define LPC_IC_CH0IC0 0x00000001 // Channel 0 Interrupt Clear 0 919 920 //***************************************************************************** 921 // 922 // The following are defines for the bit fields in the LPC_O_DMACX register. 923 // 924 //***************************************************************************** 925 #define LPC_DMACX_CXRES 0x02000000 // Raw Event State for COMx 926 #define LPC_DMACX_CXTXRES 0x01000000 // Raw Event State for COMx TX 927 #define LPC_DMACX_CXRXRES 0x00800000 // Raw Event State for COMx RX 928 #define LPC_DMACX_CXEM 0x00200000 // Event Mask for COMx 929 #define LPC_DMACX_CXTXEM 0x00100000 // Event Mask for COMx TX 930 #define LPC_DMACX_CXRXEM 0x00080000 // Event Mask for COMx RX 931 #define LPC_DMACX_CXACT_M 0x00060000 // COMx Action 932 #define LPC_DMACX_CXACT_FRMHNML 0x00000000 // Treat as normal FRMH model and 933 // let be full (and so marked as 934 // full) 935 #define LPC_DMACX_CXACT_FRMHIGN 0x00020000 // Ignore FRMH bytes and continue 936 // to mark FRMH as empty 937 #define LPC_DMACX_CXACT_FRMHDMA 0x00040000 // COMx DMA on FRMH byte (e.g. to 938 // memory) 939 #define LPC_DMACX_CXACT_UARTDMA 0x00060000 // COMx DMA model with UART 940 #define LPC_DMACX_COMX 0x00010000 // COMx Handling 941 #define LPC_DMACX_C3W 0x00000080 // Write Control for Channel 3 942 #define LPC_DMACX_C3R 0x00000040 // Read Control for Channel 3 943 #define LPC_DMACX_C2W 0x00000020 // Write Control for Channel 2 944 #define LPC_DMACX_C2R 0x00000010 // Read Control for Channel 2 945 #define LPC_DMACX_C1W 0x00000008 // Write Control for Channel 1 946 #define LPC_DMACX_C1R 0x00000004 // Read Control for Channel 1 947 #define LPC_DMACX_C0W 0x00000002 // Write Control for Channel 0 948 #define LPC_DMACX_C0R 0x00000001 // Read Control for Channel 0 949 950 //***************************************************************************** 951 // 952 // The following are defines for the bit fields in the LPC_O_POOL register. 953 // 954 //***************************************************************************** 955 #define LPC_POOL_BYTE3_M 0xFF000000 // Byte 3 956 #define LPC_POOL_BYTE2_M 0x00FF0000 // Byte 2 957 #define LPC_POOL_BYTE1_M 0x0000FF00 // Byte 1 958 #define LPC_POOL_BYTE0_M 0x000000FF // Byte 0 959 #define LPC_POOL_BYTE3_S 24 960 #define LPC_POOL_BYTE2_S 16 961 #define LPC_POOL_BYTE1_S 8 962 #define LPC_POOL_BYTE0_S 0 963 964 //***************************************************************************** 965 // 966 // The following are defines for the bit fields in the LPC_O_PP register. 967 // 968 //***************************************************************************** 969 #define LPC_PP_COMX 0x00000010 // COMx Support Available 970 #define LPC_PP_CHANCNT_M 0x0000000F // Number of Channels (Excluding 971 // COMx) 972 #define LPC_PP_CHANCNT_S 0 973 974 #endif // __HW_LPC_H__ 975