1 //***************************************************************************** 2 // 3 // hw_peci.h - Macros used when accessing the PECI hardware. 4 // 5 // Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_PECI_H__ 26 #define __HW_PECI_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the PECI register addresses. 31 // 32 //***************************************************************************** 33 #define PECI_O_CTL 0x00000000 // PECI Control 34 #define PECI_O_DIV 0x00000004 // PECI Poll-Rate Divider 35 #define PECI_O_CMP 0x00000008 // PECI Comparator 36 #define PECI_O_M0D0C 0x00000010 // PECI Microprocessor 0 / Domain 0 37 // Control 38 #define PECI_O_M0D1C 0x00000014 // PECI Microprocessor 0 / Domain 1 39 // Control 40 #define PECI_O_M1D0C 0x00000018 // PECI Microprocessor 1 / Domain 0 41 // Control 42 #define PECI_O_M1D1C 0x0000001C // PECI Microprocessor 1 / Domain 1 43 // Control 44 #define PECI_O_M0D0 0x00000040 // PECI Microprocessor 0 / Domain 0 45 // Value 46 #define PECI_O_M0D1 0x00000044 // PECI Microprocessor 0 / Domain 1 47 // Value 48 #define PECI_O_M1D0 0x00000048 // PECI Microprocessor 1 / Domain 0 49 // Value 50 #define PECI_O_M1D1 0x0000004C // PECI Microprocessor 1 / Domain 1 51 // Value 52 #define PECI_O_IM 0x00000080 // PECI Interrupt Mask 53 #define PECI_O_RIS 0x00000084 // PECI Raw Interrupt Status 54 #define PECI_O_MIS 0x00000088 // PECI Masked Interrupt Status 55 #define PECI_O_IC 0x0000008C // PECI Interrupt Clear 56 #define PECI_O_ACADDR 0x00000100 // PECI Advanced Command Address 57 #define PECI_O_ACARG 0x00000104 // PECI Advanced Command Argument 58 #define PECI_O_ACRDWR0 0x00000108 // PECI Advanced Command Data 0 59 #define PECI_O_ACRDWR1 0x0000010C // PECI Advanced Command Data 1 60 #define PECI_O_ACCMD 0x00000110 // PECI Advanced Command 61 #define PECI_O_ACCODE 0x00000114 // PECI Advanced Command Completion 62 // Code 63 64 //***************************************************************************** 65 // 66 // The following are defines for the bit fields in the PECI_O_CTL register. 67 // 68 //***************************************************************************** 69 #define PECI_CTL_OFFSET_M 0xFFFF0000 // Offset Value 70 #define PECI_CTL_CRETRY_M 0x00007000 // Number of Controller Retries 71 #define PECI_CTL_BYERR 0x00000800 // Number of Retries 72 #define PECI_CTL_RXINV 0x00000400 // Invert PECI RX Input 73 #define PECI_CTL_M1D1EN 0x00000008 // Enable Microprocessor 1 and 74 // Domain 1 75 #define PECI_CTL_M1D0EN 0x00000004 // Enable Microprocessor 1 and 76 // Domain 0 77 #define PECI_CTL_M0D1EN 0x00000002 // Enable Microprocessor 0 and 78 // Domain 1 79 #define PECI_CTL_M0D0EN 0x00000001 // Enable Microprocessor 0 and 80 // Domain 0 81 #define PECI_CTL_OFFSET_S 16 82 #define PECI_CTL_CRETRY_S 12 83 84 //***************************************************************************** 85 // 86 // The following are defines for the bit fields in the PECI_O_DIV register. 87 // 88 //***************************************************************************** 89 #define PECI_DIV_BAUD_M 0xFFFF0000 // Initial Baud Rate 90 #define PECI_DIV_POLL_M 0x0000FFFF // Counter for Inter-Poll Delay 91 #define PECI_DIV_BAUD_S 16 92 #define PECI_DIV_POLL_S 0 93 94 //***************************************************************************** 95 // 96 // The following are defines for the bit fields in the PECI_O_CMP register. 97 // 98 //***************************************************************************** 99 #define PECI_CMP_VREF_M 0x00000007 // Resistor Ladder Voltage Ref 100 #define PECI_CMP_VREF_0_5000V 0x00000000 // 0.5000 101 #define PECI_CMP_VREF_0_5125V 0x00000001 // 0.5125 102 #define PECI_CMP_VREF_0_5250V 0x00000002 // 0.5250 103 #define PECI_CMP_VREF_0_5375V 0x00000003 // 0.5375 104 #define PECI_CMP_VREF_0_5500V 0x00000004 // 0.5500 105 #define PECI_CMP_VREF_0_5625V 0x00000005 // 0.5625 106 #define PECI_CMP_VREF_0_6000V 0x00000006 // 0.6000 107 #define PECI_CMP_VREF_0_6625V 0x00000007 // 0.6625 108 109 //***************************************************************************** 110 // 111 // The following are defines for the bit fields in the PECI_O_M0D0C register. 112 // 113 //***************************************************************************** 114 #define PECI_M0D0C_HITHR_M 0xFFFF0000 // High Threshold 115 #define PECI_M0D0C_LOTHR_M 0x0000FFFF // Low Threshold 116 #define PECI_M0D0C_HITHR_S 16 117 #define PECI_M0D0C_LOTHR_S 0 118 119 //***************************************************************************** 120 // 121 // The following are defines for the bit fields in the PECI_O_M0D1C register. 122 // 123 //***************************************************************************** 124 #define PECI_M0D1C_HITHR_M 0xFFFF0000 // High Threshold 125 #define PECI_M0D1C_LOTHR_M 0x0000FFFF // Low Threshold 126 #define PECI_M0D1C_HITHR_S 16 127 #define PECI_M0D1C_LOTHR_S 0 128 129 //***************************************************************************** 130 // 131 // The following are defines for the bit fields in the PECI_O_M1D0C register. 132 // 133 //***************************************************************************** 134 #define PECI_M1D0C_HITHR_M 0xFFFF0000 // High Threshold 135 #define PECI_M1D0C_LOTHR_M 0x0000FFFF // Low Threshold 136 #define PECI_M1D0C_HITHR_S 16 137 #define PECI_M1D0C_LOTHR_S 0 138 139 //***************************************************************************** 140 // 141 // The following are defines for the bit fields in the PECI_O_M1D1C register. 142 // 143 //***************************************************************************** 144 #define PECI_M1D1C_HITHR_M 0xFFFF0000 // High Threshold 145 #define PECI_M1D1C_LOTHR_M 0x0000FFFF // Low Threshold 146 #define PECI_M1D1C_HITHR_S 16 147 #define PECI_M1D1C_LOTHR_S 0 148 149 //***************************************************************************** 150 // 151 // The following are defines for the bit fields in the PECI_O_M0D0 register. 152 // 153 //***************************************************************************** 154 #define PECI_M0D0_MAXREAD_M 0xFFFF0000 // Highest Value Read 155 #define PECI_M0D0_VALUE_M 0x0000FFFF // Last Value Read 156 #define PECI_M0D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error 157 // on transmitted data 158 #define PECI_M0D0_VALUE_CRCRX 0x000081FA // CRC error on received data 159 #define PECI_M0D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data 160 #define PECI_M0D0_VALUE_NEG 0x000081FC // Negotiation error 161 #define PECI_M0D0_VALUE_TO 0x000081FD // Timeout error 162 #define PECI_M0D0_MAXREAD_S 16 163 164 //***************************************************************************** 165 // 166 // The following are defines for the bit fields in the PECI_O_M0D1 register. 167 // 168 //***************************************************************************** 169 #define PECI_M0D1_MAXREAD_M 0xFFFF0000 // Highest Value Read 170 #define PECI_M0D1_VALUE_M 0x0000FFFF // Last Value Read 171 #define PECI_M0D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error 172 // on transmitted data 173 #define PECI_M0D1_VALUE_CRCRX 0x000081FA // CRC error on received data 174 #define PECI_M0D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data 175 #define PECI_M0D1_VALUE_NEG 0x000081FC // Negotiation error 176 #define PECI_M0D1_VALUE_TO 0x000081FD // Timeout error 177 #define PECI_M0D1_MAXREAD_S 16 178 179 //***************************************************************************** 180 // 181 // The following are defines for the bit fields in the PECI_O_M1D0 register. 182 // 183 //***************************************************************************** 184 #define PECI_M1D0_MAXREAD_M 0xFFFF0000 // Highest Value Read 185 #define PECI_M1D0_VALUE_M 0x0000FFFF // Last Value Read 186 #define PECI_M1D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error 187 // on transmitted data 188 #define PECI_M1D0_VALUE_CRCRX 0x000081FA // CRC error on received data 189 #define PECI_M1D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data 190 #define PECI_M1D0_VALUE_NEG 0x000081FC // Negotiation error 191 #define PECI_M1D0_VALUE_TO 0x000081FD // Timeout error 192 #define PECI_M1D0_MAXREAD_S 16 193 194 //***************************************************************************** 195 // 196 // The following are defines for the bit fields in the PECI_O_M1D1 register. 197 // 198 //***************************************************************************** 199 #define PECI_M1D1_MAXREAD_M 0xFFFF0000 // Highest Value Read 200 #define PECI_M1D1_VALUE_M 0x0000FFFF // Last Value Read 201 #define PECI_M1D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error 202 // on transmitted data 203 #define PECI_M1D1_VALUE_CRCRX 0x000081FA // CRC error on received data 204 #define PECI_M1D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data 205 #define PECI_M1D1_VALUE_NEG 0x000081FC // Negotiation error 206 #define PECI_M1D1_VALUE_TO 0x000081FD // Timeout error 207 #define PECI_M1D1_MAXREAD_S 16 208 209 //***************************************************************************** 210 // 211 // The following are defines for the bit fields in the PECI_O_IM register. 212 // 213 //***************************************************************************** 214 #define PECI_IM_M1D1IM_M 0x00C00000 // Microprocessor 1 and Domain 1 215 // Interrupt Mask 216 #define PECI_IM_M1D1IM_HIGH 0x00400000 // Interrupt when value is above 217 // high threshold 218 #define PECI_IM_M1D1IM_CROSSUP 0x00800000 // Interrupt when crossing above 219 // either threshold 220 #define PECI_IM_M1D1IM_CROSSANY 0x00C00000 // Interrupt when crossing either 221 // threshold in either direction 222 #define PECI_IM_M1D0IM_M 0x00300000 // Microprocessor 1 and Domain 0 223 // Interrupt Mask 224 #define PECI_IM_M0D1IM_M 0x000C0000 // Microprocessor 0 and Domain 1 225 // Interrupt Mask 226 #define PECI_IM_M0D0IM_M 0x00030000 // Microprocessor 0 and Domain 0 227 // Interrupt Mask 228 #define PECI_IM_ACIM 0x00000004 // Advanced Command Interrupt Mask 229 #define PECI_IM_ERRIM 0x00000002 // Error Detected Interrupt Mask 230 #define PECI_IM_POLLIM 0x00000001 // Poll Completed Interrupt Mask 231 #define PECI_IM_M1D0IM_S 20 232 #define PECI_IM_M0D1IM_S 18 233 #define PECI_IM_M0D0IM_S 16 234 235 //***************************************************************************** 236 // 237 // The following are defines for the bit fields in the PECI_O_RIS register. 238 // 239 //***************************************************************************** 240 #define PECI_RIS_M1D1RIS_M 0x00C00000 // Microprocessor 1 and Domain 1 241 // Raw Interrupt Status 242 #define PECI_RIS_M1D0RIS_M 0x00300000 // Microprocessor 1 and Domain 0 243 // Raw Interrupt Status 244 #define PECI_RIS_M0D1RIS_M 0x000C0000 // Microprocessor 0 and Domain 1 245 // Raw Interrupt Status 246 #define PECI_RIS_M0D0RIS_M 0x00030000 // Microprocessor 0 and Domain 0 247 // Raw Interrupt Status 248 #define PECI_RIS_ACRIS 0x00000004 // Advanced Command Raw Interrupt 249 // Status 250 #define PECI_RIS_ERRRIS 0x00000002 // Error Detected Raw Interrupt 251 // Status 252 #define PECI_RIS_POLLRIS 0x00000001 // Poll Completed Raw Interrupt 253 // Status 254 #define PECI_RIS_M1D1RIS_S 22 255 #define PECI_RIS_M1D0RIS_S 20 256 #define PECI_RIS_M0D1RIS_S 18 257 #define PECI_RIS_M0D0RIS_S 16 258 259 //***************************************************************************** 260 // 261 // The following are defines for the bit fields in the PECI_O_MIS register. 262 // 263 //***************************************************************************** 264 #define PECI_MIS_M1D1MIS_M 0x00C00000 // Microprocessor 1 and Domain 1 265 // Masked Interrupt Status 266 #define PECI_MIS_M1D0MIS_M 0x00300000 // Microprocessor 1 and Domain 0 267 // Masked Interrupt Status 268 #define PECI_MIS_M0D1MIS_M 0x000C0000 // Microprocessor 0 and Domain 1 269 // Masked Interrupt Status 270 #define PECI_MIS_M0D0MIS_M 0x00030000 // Microprocessor 0 and Domain 0 271 // Masked Interrupt Status 272 #define PECI_MIS_ACMIS 0x00000004 // Advanced Command Masked 273 // Interrupt Status 274 #define PECI_MIS_ERRMIS 0x00000002 // Error Detected Masked Interrupt 275 // Status 276 #define PECI_MIS_POLLMIS 0x00000001 // Poll Completed Masked Interrupt 277 // Status 278 #define PECI_MIS_M1D1MIS_S 22 279 #define PECI_MIS_M1D0MIS_S 20 280 #define PECI_MIS_M0D1MIS_S 18 281 #define PECI_MIS_M0D0MIS_S 16 282 283 //***************************************************************************** 284 // 285 // The following are defines for the bit fields in the PECI_O_IC register. 286 // 287 //***************************************************************************** 288 #define PECI_IC_M1D1IC_M 0x00C00000 // Microprocessor 1 and Domain 1 289 // Interrupt Clear 290 #define PECI_IC_M1D0IC_M 0x00300000 // Microprocessor 1 and Domain 0 291 // Interrupt Clear 292 #define PECI_IC_M0D1IC_M 0x000C0000 // Microprocessor 0 and Domain 1 293 // Interrupt Clear 294 #define PECI_IC_M0D0IC_M 0x00030000 // Microprocessor 0 and Domain 0 295 // Interrupt Clear 296 #define PECI_IC_ACIC 0x00000004 // Advanced Command Interrupt Clear 297 #define PECI_IC_ERRIC 0x00000002 // Error Detected Interrupt Clear 298 #define PECI_IC_POLLIC 0x00000001 // Poll Completed Interrupt Clear 299 #define PECI_IC_M1D1IC_S 22 300 #define PECI_IC_M1D0IC_S 20 301 #define PECI_IC_M0D1IC_S 18 302 #define PECI_IC_M0D0IC_S 16 303 304 //***************************************************************************** 305 // 306 // The following are defines for the bit fields in the PECI_O_ACADDR register. 307 // 308 //***************************************************************************** 309 #define PECI_ACADDR_HIDRE_M 0xFF000000 // HostID and Retry 310 #define PECI_ACADDR_SIZE_M 0x00FF0000 // Size Override 311 #define PECI_ACADDR_DOMAIN_M 0x0000FF00 // Domain Select 312 #define PECI_ACADDR_PROCADD_M 0x000000FF // Processor Address 313 #define PECI_ACADDR_HIDRE_S 24 314 #define PECI_ACADDR_SIZE_S 16 315 #define PECI_ACADDR_DOMAIN_S 8 316 #define PECI_ACADDR_PROCADD_S 0 317 318 //***************************************************************************** 319 // 320 // The following are defines for the bit fields in the PECI_O_ACARG register. 321 // 322 //***************************************************************************** 323 #define PECI_ACARG_ARG3_M 0xFF000000 // Argument 3 324 #define PECI_ACARG_ARG2_M 0x00FF0000 // Argument 2 325 #define PECI_ACARG_ARG1_M 0x0000FF00 // Argument 1 326 #define PECI_ACARG_ARG0_M 0x000000FF // Argument 0 327 #define PECI_ACARG_ARG3_S 24 328 #define PECI_ACARG_ARG2_S 16 329 #define PECI_ACARG_ARG1_S 8 330 #define PECI_ACARG_ARG0_S 0 331 332 //***************************************************************************** 333 // 334 // The following are defines for the bit fields in the PECI_O_ACRDWR0 register. 335 // 336 //***************************************************************************** 337 #define PECI_ACRDWR0_D3_M 0xFF000000 // Data 3 338 #define PECI_ACRDWR0_D2_M 0x00FF0000 // Data 2 339 #define PECI_ACRDWR0_D1_M 0x0000FF00 // Data 1 340 #define PECI_ACRDWR0_D0_M 0x000000FF // Data 0 341 #define PECI_ACRDWR0_D3_S 24 342 #define PECI_ACRDWR0_D2_S 16 343 #define PECI_ACRDWR0_D1_S 8 344 #define PECI_ACRDWR0_D0_S 0 345 346 //***************************************************************************** 347 // 348 // The following are defines for the bit fields in the PECI_O_ACRDWR1 register. 349 // 350 //***************************************************************************** 351 #define PECI_ACRDWR1_D3_M 0xFF000000 // Data 3 352 #define PECI_ACRDWR1_D2_M 0x00FF0000 // Data 2 353 #define PECI_ACRDWR1_D1_M 0x0000FF00 // Data 1 354 #define PECI_ACRDWR1_D0_M 0x000000FF // Data 0 355 #define PECI_ACRDWR1_D3_S 24 356 #define PECI_ACRDWR1_D2_S 16 357 #define PECI_ACRDWR1_D1_S 8 358 #define PECI_ACRDWR1_D0_S 0 359 360 //***************************************************************************** 361 // 362 // The following are defines for the bit fields in the PECI_O_ACCMD register. 363 // 364 //***************************************************************************** 365 #define PECI_ACCMD_CMD_M 0x000000FF // Base Command 366 #define PECI_ACCMD_CMD_S 0 367 368 //***************************************************************************** 369 // 370 // The following are defines for the bit fields in the PECI_O_ACCODE register. 371 // 372 //***************************************************************************** 373 #define PECI_ACCODE_CODE_M 0xFFFFFFFF // Signed Completion Code 374 375 #endif // __HW_PECI_H__ 376