1 //***************************************************************************** 2 // 3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_WATCHDOG_H__ 26 #define __HW_WATCHDOG_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the Watchdog Timer register offsets. 31 // 32 //***************************************************************************** 33 #define WDT_O_LOAD 0x00000000 // Watchdog Load 34 #define WDT_O_VALUE 0x00000004 // Watchdog Value 35 #define WDT_O_CTL 0x00000008 // Watchdog Control 36 #define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear 37 #define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status 38 #define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status 39 #define WDT_O_TEST 0x00000418 // Watchdog Test 40 #define WDT_O_LOCK 0x00000C00 // Watchdog Lock 41 42 //***************************************************************************** 43 // 44 // The following are defines for the bit fields in the WDT_O_LOAD register. 45 // 46 //***************************************************************************** 47 #define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value 48 #define WDT_LOAD_S 0 49 50 //***************************************************************************** 51 // 52 // The following are defines for the bit fields in the WDT_O_VALUE register. 53 // 54 //***************************************************************************** 55 #define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value 56 #define WDT_VALUE_S 0 57 58 //***************************************************************************** 59 // 60 // The following are defines for the bit fields in the WDT_O_CTL register. 61 // 62 //***************************************************************************** 63 #define WDT_CTL_WRC 0x80000000 // Write Complete 64 #define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type 65 #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable 66 #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable 67 68 //***************************************************************************** 69 // 70 // The following are defines for the bit fields in the WDT_O_ICR register. 71 // 72 //***************************************************************************** 73 #define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear 74 #define WDT_ICR_S 0 75 76 //***************************************************************************** 77 // 78 // The following are defines for the bit fields in the WDT_O_RIS register. 79 // 80 //***************************************************************************** 81 #define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status 82 83 //***************************************************************************** 84 // 85 // The following are defines for the bit fields in the WDT_O_MIS register. 86 // 87 //***************************************************************************** 88 #define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status 89 90 //***************************************************************************** 91 // 92 // The following are defines for the bit fields in the WDT_O_TEST register. 93 // 94 //***************************************************************************** 95 #define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable 96 97 //***************************************************************************** 98 // 99 // The following are defines for the bit fields in the WDT_O_LOCK register. 100 // 101 //***************************************************************************** 102 #define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock 103 #define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked 104 #define WDT_LOCK_LOCKED 0x00000001 // Locked 105 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer 106 107 //***************************************************************************** 108 // 109 // The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and 110 // WDT_MIS registers. 111 // 112 //***************************************************************************** 113 #define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired 114 115 //***************************************************************************** 116 // 117 // The following definitions are deprecated. 118 // 119 //***************************************************************************** 120 #ifndef DEPRECATED 121 122 //***************************************************************************** 123 // 124 // The following are deprecated defines for the Watchdog Timer register 125 // offsets. 126 // 127 //***************************************************************************** 128 #define WDT_O_PeriphID4 0x00000FD0 129 #define WDT_O_PeriphID5 0x00000FD4 130 #define WDT_O_PeriphID6 0x00000FD8 131 #define WDT_O_PeriphID7 0x00000FDC 132 #define WDT_O_PeriphID0 0x00000FE0 133 #define WDT_O_PeriphID1 0x00000FE4 134 #define WDT_O_PeriphID2 0x00000FE8 135 #define WDT_O_PeriphID3 0x00000FEC 136 #define WDT_O_PCellID0 0x00000FF0 137 #define WDT_O_PCellID1 0x00000FF4 138 #define WDT_O_PCellID2 0x00000FF8 139 #define WDT_O_PCellID3 0x00000FFC 140 141 //***************************************************************************** 142 // 143 // The following are deprecated defines for the bit fields in the WDT_O_TEST 144 // register. 145 // 146 //***************************************************************************** 147 #define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable 148 149 //***************************************************************************** 150 // 151 // The following are deprecated defines for the reset values for the WDT 152 // registers. 153 // 154 //***************************************************************************** 155 #define WDT_RV_VALUE 0xFFFFFFFF // Current value register 156 #define WDT_RV_LOAD 0xFFFFFFFF // Load register 157 #define WDT_RV_PCellID1 0x000000F0 158 #define WDT_RV_PCellID3 0x000000B1 159 #define WDT_RV_PeriphID1 0x00000018 160 #define WDT_RV_PeriphID2 0x00000018 161 #define WDT_RV_PCellID0 0x0000000D 162 #define WDT_RV_PCellID2 0x00000005 163 #define WDT_RV_PeriphID0 0x00000005 164 #define WDT_RV_PeriphID3 0x00000001 165 #define WDT_RV_PeriphID5 0x00000000 166 #define WDT_RV_RIS 0x00000000 // Raw interrupt status register 167 #define WDT_RV_CTL 0x00000000 // Control register 168 #define WDT_RV_PeriphID4 0x00000000 169 #define WDT_RV_PeriphID6 0x00000000 170 #define WDT_RV_PeriphID7 0x00000000 171 #define WDT_RV_LOCK 0x00000000 // Lock register 172 #define WDT_RV_MIS 0x00000000 // Masked interrupt status register 173 174 #endif 175 176 #endif // __HW_WATCHDOG_H__ 177