1 //***************************************************************************** 2 // 3 // hw_eeprom.h - Macros used when accessing the EEPROM controller. 4 // 5 // Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_EEPROM_H__ 26 #define __HW_EEPROM_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the EEPROM register offsets. 31 // 32 //***************************************************************************** 33 #define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information 34 #define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block 35 #define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset 36 #define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write 37 #define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment 38 #define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status 39 #define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and 40 // Status 41 #define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock 42 #define EEPROM_EEPROT 0x400AF030 // EEPROM Protection 43 #define EEPROM_EEPASS0 0x400AF034 // EEPROM Password 44 #define EEPROM_EEPASS1 0x400AF038 // EEPROM Password 45 #define EEPROM_EEPASS2 0x400AF03C // EEPROM Password 46 #define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt 47 #define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide 48 #define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase 49 #define EEPROM_EEPROMPP 0x400AFFC0 // EEPROM 50 51 //***************************************************************************** 52 // 53 // The following are defines for the bit fields in the EEPROM_EESIZE register. 54 // 55 //***************************************************************************** 56 #define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words 57 #define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks 58 #define EEPROM_EESIZE_WORDCNT_S 0 59 #define EEPROM_EESIZE_BLKCNT_S 16 60 61 //***************************************************************************** 62 // 63 // The following are defines for the bit fields in the EEPROM_EEBLOCK register. 64 // 65 //***************************************************************************** 66 #define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block 67 #define EEPROM_EEBLOCK_BLOCK_S 0 68 69 //***************************************************************************** 70 // 71 // The following are defines for the bit fields in the EEPROM_EEOFFSET 72 // register. 73 // 74 //***************************************************************************** 75 #define EEPROM_EEOFFSET_OFFSET_M \ 76 0x0000000F // Current Address Offset 77 #define EEPROM_EEOFFSET_OFFSET_S \ 78 0 79 80 //***************************************************************************** 81 // 82 // The following are defines for the bit fields in the EEPROM_EERDWR register. 83 // 84 //***************************************************************************** 85 #define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data 86 #define EEPROM_EERDWR_VALUE_S 0 87 88 //***************************************************************************** 89 // 90 // The following are defines for the bit fields in the EEPROM_EERDWRINC 91 // register. 92 // 93 //***************************************************************************** 94 #define EEPROM_EERDWRINC_VALUE_M \ 95 0xFFFFFFFF // EEPROM Read or Write Data with 96 // Increment 97 #define EEPROM_EERDWRINC_VALUE_S \ 98 0 99 100 //***************************************************************************** 101 // 102 // The following are defines for the bit fields in the EEPROM_EEDONE register. 103 // 104 //***************************************************************************** 105 #define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working 106 #define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase 107 #define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy 108 #define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission 109 #define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy 110 #define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level 111 112 //***************************************************************************** 113 // 114 // The following are defines for the bit fields in the EEPROM_EESUPP register. 115 // 116 //***************************************************************************** 117 #define EEPROM_EESUPP_START 0x00000001 // Start Erase 118 #define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required 119 #define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried 120 #define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried 121 122 //***************************************************************************** 123 // 124 // The following are defines for the bit fields in the EEPROM_EEUNLOCK 125 // register. 126 // 127 //***************************************************************************** 128 #define EEPROM_EEUNLOCK_UNLOCK_M \ 129 0xFFFFFFFF // EEPROM Unlock 130 131 //***************************************************************************** 132 // 133 // The following are defines for the bit fields in the EEPROM_EEPROT register. 134 // 135 //***************************************************************************** 136 #define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control 137 #define EEPROM_EEPROT_PROT_RWNPW \ 138 0x00000000 // This setting is the default. If 139 // there is no password, the block 140 // is not protected and is readable 141 // and writable 142 #define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the 143 // block is readable or writable 144 // only when unlocked 145 #define EEPROM_EEPROT_PROT_RONPW \ 146 0x00000002 // If there is no password, the 147 // block is readable, not writable 148 #define EEPROM_EEPROT_ACC 0x00000008 // Access Control 149 150 //***************************************************************************** 151 // 152 // The following are defines for the bit fields in the EEPROM_EEPASS0 register. 153 // 154 //***************************************************************************** 155 #define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password 156 #define EEPROM_EEPASS0_PASS_S 0 157 158 //***************************************************************************** 159 // 160 // The following are defines for the bit fields in the EEPROM_EEPASS1 register. 161 // 162 //***************************************************************************** 163 #define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password 164 #define EEPROM_EEPASS1_PASS_S 0 165 166 //***************************************************************************** 167 // 168 // The following are defines for the bit fields in the EEPROM_EEPASS2 register. 169 // 170 //***************************************************************************** 171 #define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password 172 #define EEPROM_EEPASS2_PASS_S 0 173 174 //***************************************************************************** 175 // 176 // The following are defines for the bit fields in the EEPROM_EEINT register. 177 // 178 //***************************************************************************** 179 #define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable 180 181 //***************************************************************************** 182 // 183 // The following are defines for the bit fields in the EEPROM_EEHIDE register. 184 // 185 //***************************************************************************** 186 #define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block 187 188 //***************************************************************************** 189 // 190 // The following are defines for the bit fields in the EEPROM_EEDBGME register. 191 // 192 //***************************************************************************** 193 #define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase 194 #define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key 195 #define EEPROM_EEDBGME_KEY_S 16 196 197 //***************************************************************************** 198 // 199 // The following are defines for the bit fields in the EEPROM_EEPROMPP 200 // register. 201 // 202 //***************************************************************************** 203 #define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size 204 #define EEPROM_EEPROMPP_SIZE_S 0 205 206 #endif // __HW_EEPROM_H__ 207