1 //***************************************************************************** 2 // 3 // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_PWM_H__ 26 #define __HW_PWM_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the PWM register offsets. 31 // 32 //***************************************************************************** 33 #define PWM_O_CTL 0x00000000 // PWM Master Control 34 #define PWM_O_SYNC 0x00000004 // PWM Time Base Sync 35 #define PWM_O_ENABLE 0x00000008 // PWM Output Enable 36 #define PWM_O_INVERT 0x0000000C // PWM Output Inversion 37 #define PWM_O_FAULT 0x00000010 // PWM Output Fault 38 #define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable 39 #define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status 40 #define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear 41 #define PWM_O_STATUS 0x00000020 // PWM Status 42 #define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value 43 #define PWM_O_ENUPD 0x00000028 // PWM Enable Update 44 #define PWM_O_0_CTL 0x00000040 // PWM0 Control 45 #define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger 46 // Enable 47 #define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status 48 #define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear 49 #define PWM_O_0_LOAD 0x00000050 // PWM0 Load 50 #define PWM_O_0_COUNT 0x00000054 // PWM0 Counter 51 #define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A 52 #define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B 53 #define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control 54 #define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control 55 #define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control 56 #define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay 57 #define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band 58 // Falling-Edge-Delay 59 #define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 60 #define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 61 #define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period 62 #define PWM_O_1_CTL 0x00000080 // PWM1 Control 63 #define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger 64 // Enable 65 #define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status 66 #define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear 67 #define PWM_O_1_LOAD 0x00000090 // PWM1 Load 68 #define PWM_O_1_COUNT 0x00000094 // PWM1 Counter 69 #define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A 70 #define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B 71 #define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control 72 #define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control 73 #define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control 74 #define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay 75 #define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band 76 // Falling-Edge-Delay 77 #define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 78 #define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 79 #define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period 80 #define PWM_O_2_CTL 0x000000C0 // PWM2 Control 81 #define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger 82 // Enable 83 #define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status 84 #define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear 85 #define PWM_O_2_LOAD 0x000000D0 // PWM2 Load 86 #define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter 87 #define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A 88 #define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B 89 #define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control 90 #define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control 91 #define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control 92 #define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay 93 #define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band 94 // Falling-Edge-Delay 95 #define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 96 #define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 97 #define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period 98 #define PWM_O_3_CTL 0x00000100 // PWM3 Control 99 #define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger 100 // Enable 101 #define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status 102 #define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear 103 #define PWM_O_3_LOAD 0x00000110 // PWM3 Load 104 #define PWM_O_3_COUNT 0x00000114 // PWM3 Counter 105 #define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A 106 #define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B 107 #define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control 108 #define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control 109 #define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control 110 #define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay 111 #define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band 112 // Falling-Edge-Delay 113 #define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 114 #define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 115 #define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period 116 #define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense 117 #define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 118 #define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 119 #define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense 120 #define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 121 #define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 122 #define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense 123 #define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 124 #define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 125 #define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense 126 #define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 127 #define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 128 #define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties 129 #define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration 130 131 //***************************************************************************** 132 // 133 // The following are defines for the bit fields in the PWM_O_CTL register. 134 // 135 //***************************************************************************** 136 #define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 137 #define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 138 #define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 139 #define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 140 141 //***************************************************************************** 142 // 143 // The following are defines for the bit fields in the PWM_O_SYNC register. 144 // 145 //***************************************************************************** 146 #define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter 147 #define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter 148 #define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter 149 #define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter 150 151 //***************************************************************************** 152 // 153 // The following are defines for the bit fields in the PWM_O_ENABLE register. 154 // 155 //***************************************************************************** 156 #define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable 157 #define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable 158 #define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable 159 #define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable 160 #define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable 161 #define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable 162 #define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable 163 #define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the PWM_O_INVERT register. 168 // 169 //***************************************************************************** 170 #define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal 171 #define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal 172 #define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal 173 #define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal 174 #define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal 175 #define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal 176 #define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal 177 #define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal 178 179 //***************************************************************************** 180 // 181 // The following are defines for the bit fields in the PWM_O_FAULT register. 182 // 183 //***************************************************************************** 184 #define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault 185 #define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault 186 #define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault 187 #define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault 188 #define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault 189 #define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault 190 #define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault 191 #define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault 192 193 //***************************************************************************** 194 // 195 // The following are defines for the bit fields in the PWM_O_INTEN register. 196 // 197 //***************************************************************************** 198 #define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 199 #define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 200 #define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 201 #define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable 202 #define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 203 #define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable 204 #define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable 205 #define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable 206 #define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the PWM_O_RIS register. 211 // 212 //***************************************************************************** 213 #define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 214 #define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 215 #define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 216 #define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 217 #define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted 218 #define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted 219 #define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted 220 #define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted 221 #define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted 222 223 //***************************************************************************** 224 // 225 // The following are defines for the bit fields in the PWM_O_ISC register. 226 // 227 //***************************************************************************** 228 #define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted 229 #define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted 230 #define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted 231 #define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted 232 #define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted 233 #define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status 234 #define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status 235 #define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status 236 #define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status 237 238 //***************************************************************************** 239 // 240 // The following are defines for the bit fields in the PWM_O_STATUS register. 241 // 242 //***************************************************************************** 243 #define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status 244 #define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status 245 #define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status 246 #define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status 247 248 //***************************************************************************** 249 // 250 // The following are defines for the bit fields in the PWM_O_FAULTVAL register. 251 // 252 //***************************************************************************** 253 #define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value 254 #define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value 255 #define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value 256 #define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value 257 #define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value 258 #define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value 259 #define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value 260 #define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value 261 262 //***************************************************************************** 263 // 264 // The following are defines for the bit fields in the PWM_O_ENUPD register. 265 // 266 //***************************************************************************** 267 #define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode 268 #define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate 269 #define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized 270 #define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized 271 #define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode 272 #define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate 273 #define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized 274 #define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized 275 #define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode 276 #define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate 277 #define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized 278 #define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized 279 #define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode 280 #define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate 281 #define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized 282 #define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized 283 #define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode 284 #define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate 285 #define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized 286 #define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized 287 #define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode 288 #define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate 289 #define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized 290 #define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized 291 #define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode 292 #define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate 293 #define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized 294 #define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized 295 #define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode 296 #define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate 297 #define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized 298 #define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized 299 300 //***************************************************************************** 301 // 302 // The following are defines for the bit fields in the PWM_O_X_CTL register. 303 // 304 //***************************************************************************** 305 #define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input 306 #define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period 307 #define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source 308 #define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode 309 #define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate 310 #define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized 311 #define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized 312 #define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode 313 #define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate 314 #define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized 315 #define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized 316 #define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode 317 #define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate 318 #define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized 319 #define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized 320 #define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode 321 #define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate 322 #define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized 323 #define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized 324 #define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode 325 #define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate 326 #define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized 327 #define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized 328 #define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode 329 #define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode 330 #define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode 331 #define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode 332 #define PWM_X_CTL_MODE 0x00000002 // Counter Mode 333 #define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable 334 335 //***************************************************************************** 336 // 337 // The following are defines for the bit fields in the PWM_O_X_INTEN register. 338 // 339 //***************************************************************************** 340 #define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB 341 // Down 342 #define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up 343 #define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA 344 // Down 345 #define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up 346 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD 347 #define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 348 #define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB 349 // Down 350 #define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB 351 // Up 352 #define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA 353 // Down 354 #define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA 355 // Up 356 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD 357 #define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 358 359 //***************************************************************************** 360 // 361 // The following are defines for the bit fields in the PWM_O_X_RIS register. 362 // 363 //***************************************************************************** 364 #define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt 365 // Status 366 #define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status 367 #define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt 368 // Status 369 #define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status 370 #define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status 371 #define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status 372 373 //***************************************************************************** 374 // 375 // The following are defines for the bit fields in the PWM_O_X_ISC register. 376 // 377 //***************************************************************************** 378 #define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt 379 #define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt 380 #define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt 381 #define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt 382 #define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt 383 #define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt 384 385 //***************************************************************************** 386 // 387 // The following are defines for the bit fields in the PWM_O_X_LOAD register. 388 // 389 //***************************************************************************** 390 #define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value 391 #define PWM_X_LOAD_S 0 392 393 //***************************************************************************** 394 // 395 // The following are defines for the bit fields in the PWM_O_X_COUNT register. 396 // 397 //***************************************************************************** 398 #define PWM_X_COUNT_M 0x0000FFFF // Counter Value 399 #define PWM_X_COUNT_S 0 400 401 //***************************************************************************** 402 // 403 // The following are defines for the bit fields in the PWM_O_X_CMPA register. 404 // 405 //***************************************************************************** 406 #define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value 407 #define PWM_X_CMPA_S 0 408 409 //***************************************************************************** 410 // 411 // The following are defines for the bit fields in the PWM_O_X_CMPB register. 412 // 413 //***************************************************************************** 414 #define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value 415 #define PWM_X_CMPB_S 0 416 417 //***************************************************************************** 418 // 419 // The following are defines for the bit fields in the PWM_O_X_GENA register. 420 // 421 //***************************************************************************** 422 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 423 #define PWM_X_GENA_ACTCMPBD_NONE \ 424 0x00000000 // Do nothing 425 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA 426 #define PWM_X_GENA_ACTCMPBD_ZERO \ 427 0x00000800 // Drive pwmA Low 428 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High 429 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 430 #define PWM_X_GENA_ACTCMPBU_NONE \ 431 0x00000000 // Do nothing 432 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA 433 #define PWM_X_GENA_ACTCMPBU_ZERO \ 434 0x00000200 // Drive pwmA Low 435 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High 436 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 437 #define PWM_X_GENA_ACTCMPAD_NONE \ 438 0x00000000 // Do nothing 439 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA 440 #define PWM_X_GENA_ACTCMPAD_ZERO \ 441 0x00000080 // Drive pwmA Low 442 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High 443 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 444 #define PWM_X_GENA_ACTCMPAU_NONE \ 445 0x00000000 // Do nothing 446 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA 447 #define PWM_X_GENA_ACTCMPAU_ZERO \ 448 0x00000020 // Drive pwmA Low 449 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High 450 #define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD 451 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing 452 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA 453 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low 454 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High 455 #define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 456 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing 457 #define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA 458 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low 459 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High 460 461 //***************************************************************************** 462 // 463 // The following are defines for the bit fields in the PWM_O_X_GENB register. 464 // 465 //***************************************************************************** 466 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down 467 #define PWM_X_GENB_ACTCMPBD_NONE \ 468 0x00000000 // Do nothing 469 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB 470 #define PWM_X_GENB_ACTCMPBD_ZERO \ 471 0x00000800 // Drive pwmB Low 472 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High 473 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up 474 #define PWM_X_GENB_ACTCMPBU_NONE \ 475 0x00000000 // Do nothing 476 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB 477 #define PWM_X_GENB_ACTCMPBU_ZERO \ 478 0x00000200 // Drive pwmB Low 479 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High 480 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down 481 #define PWM_X_GENB_ACTCMPAD_NONE \ 482 0x00000000 // Do nothing 483 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB 484 #define PWM_X_GENB_ACTCMPAD_ZERO \ 485 0x00000080 // Drive pwmB Low 486 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High 487 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up 488 #define PWM_X_GENB_ACTCMPAU_NONE \ 489 0x00000000 // Do nothing 490 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB 491 #define PWM_X_GENB_ACTCMPAU_ZERO \ 492 0x00000020 // Drive pwmB Low 493 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High 494 #define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD 495 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing 496 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB 497 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low 498 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High 499 #define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 500 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing 501 #define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB 502 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low 503 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High 504 505 //***************************************************************************** 506 // 507 // The following are defines for the bit fields in the PWM_O_X_DBCTL register. 508 // 509 //***************************************************************************** 510 #define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable 511 512 //***************************************************************************** 513 // 514 // The following are defines for the bit fields in the PWM_O_X_DBRISE register. 515 // 516 //***************************************************************************** 517 #define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay 518 #define PWM_X_DBRISE_DELAY_S 0 519 520 //***************************************************************************** 521 // 522 // The following are defines for the bit fields in the PWM_O_X_DBFALL register. 523 // 524 //***************************************************************************** 525 #define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay 526 #define PWM_X_DBFALL_DELAY_S 0 527 528 //***************************************************************************** 529 // 530 // The following are defines for the bit fields in the PWM_O_X_FLTSRC0 531 // register. 532 // 533 //***************************************************************************** 534 #define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input 535 #define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input 536 #define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input 537 #define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input 538 539 //***************************************************************************** 540 // 541 // The following are defines for the bit fields in the PWM_O_X_FLTSRC1 542 // register. 543 // 544 //***************************************************************************** 545 #define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 546 #define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 547 #define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 548 #define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 549 #define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 550 #define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 551 #define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 552 #define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 553 554 //***************************************************************************** 555 // 556 // The following are defines for the bit fields in the PWM_O_X_MINFLTPER 557 // register. 558 // 559 //***************************************************************************** 560 #define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period 561 #define PWM_X_MINFLTPER_S 0 562 563 //***************************************************************************** 564 // 565 // The following are defines for the bit fields in the PWM_O_X_FLTSEN register. 566 // 567 //***************************************************************************** 568 #define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense 569 #define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense 570 #define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense 571 #define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense 572 573 //***************************************************************************** 574 // 575 // The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 576 // register. 577 // 578 //***************************************************************************** 579 #define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 580 #define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 581 #define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 582 #define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 583 584 //***************************************************************************** 585 // 586 // The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 587 // register. 588 // 589 //***************************************************************************** 590 #define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger 591 #define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger 592 #define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger 593 #define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger 594 #define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger 595 #define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger 596 #define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger 597 #define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger 598 599 //***************************************************************************** 600 // 601 // The following are defines for the bit fields in the PWM_O_PP register. 602 // 603 //***************************************************************************** 604 #define PWM_PP_GCNT_M 0x0000000F // Generators 605 #define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs 606 #define PWM_PP_ESYNC 0x00000100 // Extended Synchronization 607 #define PWM_PP_EFAULT 0x00000200 // Extended Fault 608 #define PWM_PP_ONE 0x00000400 // One-Shot Mode 609 #define PWM_PP_GCNT_S 0 610 #define PWM_PP_FCNT_S 4 611 612 //***************************************************************************** 613 // 614 // The following are defines for the bit fields in the PWM_O_PC register. 615 // 616 //***************************************************************************** 617 #define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor 618 #define PWM_PC_PWMDIV_2 0x00000000 // /2 619 #define PWM_PC_PWMDIV_4 0x00000001 // /4 620 #define PWM_PC_PWMDIV_8 0x00000002 // /8 621 #define PWM_PC_PWMDIV_16 0x00000003 // /16 622 #define PWM_PC_PWMDIV_32 0x00000004 // /32 623 #define PWM_PC_PWMDIV_64 0x00000007 // /64 (default) 624 #define PWM_PC_USEOPWMDIV 0x00000100 // Enable PWM Clock Divisor 625 626 //***************************************************************************** 627 // 628 // The following are defines for the PWM Generator standard offsets. 629 // 630 //***************************************************************************** 631 #define PWM_O_X_CTL 0x00000000 // Gen Control Reg 632 #define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg 633 #define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg 634 #define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg 635 #define PWM_O_X_LOAD 0x00000010 // Gen Load Reg 636 #define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg 637 #define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg 638 #define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg 639 #define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg 640 #define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg 641 #define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg 642 #define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg 643 #define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg 644 #define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition 645 #define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition 646 #define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension 647 #define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base 648 #define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base 649 #define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base 650 #define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base 651 652 //***************************************************************************** 653 // 654 // The following are defines for the PWM Generator extended offsets. 655 // 656 //***************************************************************************** 657 #define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense 658 #define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status 659 #define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status 660 #define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base 661 #define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base 662 #define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base 663 #define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base 664 665 //***************************************************************************** 666 // 667 // The following definitions are deprecated. 668 // 669 //***************************************************************************** 670 #ifndef DEPRECATED 671 672 //***************************************************************************** 673 // 674 // The following are deprecated defines for the bit fields in the PWM_O_CTL 675 // register. 676 // 677 //***************************************************************************** 678 #define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 679 #define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 680 #define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 681 682 //***************************************************************************** 683 // 684 // The following are deprecated defines for the bit fields in the PWM_O_STATUS 685 // register. 686 // 687 //***************************************************************************** 688 #define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status 689 690 //***************************************************************************** 691 // 692 // The following are deprecated defines for the PWM Interrupt Register bit 693 // definitions. 694 // 695 //***************************************************************************** 696 #define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending 697 698 //***************************************************************************** 699 // 700 // The following are deprecated defines for the PWM_X Interrupt Status Register 701 // bit definitions. 702 // 703 //***************************************************************************** 704 #define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd 705 #define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd 706 #define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd 707 #define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd 708 #define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd 709 #define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received 710 711 //***************************************************************************** 712 // 713 // The following are deprecated defines for the PWM_X Generator A/B Control 714 // Register bit definitions. 715 // 716 //***************************************************************************** 717 #define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D 718 #define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U 719 #define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D 720 #define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U 721 #define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD 722 #define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 723 724 //***************************************************************************** 725 // 726 // The following are deprecated defines for the PWM_X Generator A/B Control 727 // Register action definitions. 728 // 729 //***************************************************************************** 730 #define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one 731 #define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero 732 #define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal 733 #define PWM_GEN_ACT_NONE 0x00000000 // Do nothing 734 #define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action 735 #define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action 736 #define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action 737 #define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action 738 #define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action 739 #define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action 740 741 //***************************************************************************** 742 // 743 // The following are deprecated defines for the PWM_X Dead Band Control 744 // Register bit definitions. 745 // 746 //***************************************************************************** 747 #define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion 748 749 //***************************************************************************** 750 // 751 // The following are deprecated defines for the PWM Register reset values. 752 // 753 //***************************************************************************** 754 #define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator 755 #define PWM_RV_STATUS 0x00000000 // Status 756 #define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing 757 #define PWM_RV_X_RIS 0x00000000 // Raw interrupt status 758 #define PWM_RV_X_CTL 0x00000000 // Master control of the PWM 759 // generator block 760 #define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators 761 #define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay 762 // count 763 #define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable 764 #define PWM_RV_X_LOAD 0x00000000 // The load value for the counter 765 #define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A 766 #define PWM_RV_CTL 0x00000000 // Master control of the PWM module 767 #define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM 768 // output pins 769 #define PWM_RV_RIS 0x00000000 // Raw interrupt status 770 #define PWM_RV_X_CMPA 0x00000000 // The comparator A value 771 #define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output 772 // pins 773 #define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay 774 // count 775 #define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output 776 // pins 777 #define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B 778 #define PWM_RV_X_CMPB 0x00000000 // The comparator B value 779 #define PWM_RV_ISC 0x00000000 // Interrupt status and clearing 780 #define PWM_RV_INTEN 0x00000000 // Interrupt enable 781 #define PWM_RV_X_COUNT 0x00000000 // The current counter value 782 783 #endif 784 785 #endif // __HW_PWM_H__ 786