1 //***************************************************************************** 2 // 3 // lpc.h - Prototypes for the Low Pin Count (LPC) driver. 4 // 5 // Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Peripheral Driver Library. 22 // 23 //***************************************************************************** 24 25 #ifndef __LPC_H__ 26 #define __LPC_H__ 27 28 //***************************************************************************** 29 // 30 // If building with a C++ compiler, make all of the definitions in this header 31 // have a C binding. 32 // 33 //***************************************************************************** 34 #ifdef __cplusplus 35 extern "C" 36 { 37 #endif 38 39 //***************************************************************************** 40 // 41 // Values that can be passed to LPCConfigSet as the ulConfig value, and 42 // returned from LPCConfigGet. 43 // 44 //***************************************************************************** 45 #define LPC_CFG_WAKE 0x00000100 // Restart the LPC Bus 46 47 //***************************************************************************** 48 // 49 // Values that can be returned from LPCStatus. 50 // 51 //***************************************************************************** 52 #define LPC_STATUS_RST 0x00000400 // LPC is in Reset 53 #define LPC_STATUS_BUSY 0x00000200 // LPC is Busy 54 #define LPC_STATUS_SLEEP 0x00000100 // LPC is in Sleep Mode 55 #define LPC_STATUS_CA7 0x00000080 // Channel 7 Active 56 #define LPC_STATUS_CA6 0x00000040 // Channel 6 Active 57 #define LPC_STATUS_CA5 0x00000020 // Channel 5 Active 58 #define LPC_STATUS_CA4 0x00000010 // Channel 4 Active 59 #define LPC_STATUS_CA3 0x00000008 // Channel 3 Active 60 #define LPC_STATUS_CA2 0x00000004 // Channel 2 Active 61 #define LPC_STATUS_CA1 0x00000002 // Channel 1 Active 62 #define LPC_STATUS_CA0 0x00000001 // Channel 0 Active 63 64 //***************************************************************************** 65 // 66 // Values that can be passed to LPCIRQSet and LPCIRQClear in the ulIRQ 67 // parameter and returned from LPCIRQGet. 68 // 69 //***************************************************************************** 70 #define LPC_IRQ15 0x80000000 // Serial IRQ15 71 #define LPC_IRQ14 0x40000000 // Serial IRQ14 72 #define LPC_IRQ13 0x20000000 // Serial IRQ13 73 #define LPC_IRQ12 0x10000000 // Serial IRQ12 74 #define LPC_IRQ11 0x08000000 // Serial IRQ11 75 #define LPC_IRQ10 0x04000000 // Serial IRQ10 76 #define LPC_IRQ9 0x02000000 // Serial IRQ9 77 #define LPC_IRQ8 0x01000000 // Serial IRQ8 78 #define LPC_IRQ7 0x00800000 // Serial IRQ7 79 #define LPC_IRQ6 0x00400000 // Serial IRQ6 80 #define LPC_IRQ5 0x00200000 // Serial IRQ5 81 #define LPC_IRQ4 0x00100000 // Serial IRQ4 82 #define LPC_IRQ3 0x00080000 // Serial IRQ3 83 #define LPC_IRQ2 0x00040000 // Serial IRQ2 84 #define LPC_IRQ1 0x00020000 // Serial IRQ1 85 #define LPC_IRQ0 0x00010000 // Serial IRQ0 86 87 //***************************************************************************** 88 // 89 // Addition values that can be returned from LPCIRQGet. 90 // 91 //***************************************************************************** 92 #define LPC_IRQ_BUSY 0x00000004 // SERIRQ frame in progress 93 #define LPC_IRQ_CONT 0x00000001 // SERIRQ in Continuous Mode 94 95 //***************************************************************************** 96 // 97 // Values that can be passed as the ulChannel parameter in LPCChannel... 98 // API calls. 99 // 100 //***************************************************************************** 101 #define LPC_CHAN_CH0 0 // LPC Channel 0 102 #define LPC_CHAN_CH1 1 // LPC Channel 1 103 #define LPC_CHAN_CH2 2 // LPC Channel 2 104 #define LPC_CHAN_CH3 3 // LPC Channel 3 105 #define LPC_CHAN_CH4 4 // LPC Channel 4 106 #define LPC_CHAN_CH5 5 // LPC Channel 5 107 #define LPC_CHAN_CH6 6 // LPC Channel 6 108 #define LPC_CHAN_CH7 7 // LPC Channel 7 (COMx) 109 #define LPC_CHAN_COMx 7 // LPC Channel 7 (COMx) 110 111 //***************************************************************************** 112 // 113 // Values that can be passed as part of the ulConfig parameter in the 114 // LPCChannelConfig... functions. 115 // 116 //***************************************************************************** 117 #define LPC_CHAN_IRQSEL2_NONE 0x00000000 // LPC Channel IRQSEL2 Disabled 118 #define LPC_CHAN_IRQSEL2_IRQ0 0x00080000 // LPC Channel IRQSEL2 IRQ0 119 #define LPC_CHAN_IRQSEL2_IRQ1 0x10080000 // LPC Channel IRQSEL2 IRQ1 120 #define LPC_CHAN_IRQSEL2_IRQ2 0x20080000 // LPC Channel IRQSEL2 IRQ2 121 #define LPC_CHAN_IRQSEL2_IRQ3 0x30080000 // LPC Channel IRQSEL2 IRQ3 122 #define LPC_CHAN_IRQSEL2_IRQ4 0x40080000 // LPC Channel IRQSEL2 IRQ4 123 #define LPC_CHAN_IRQSEL2_IRQ5 0x50080000 // LPC Channel IRQSEL2 IRQ5 124 #define LPC_CHAN_IRQSEL2_IRQ6 0x60080000 // LPC Channel IRQSEL2 IRQ6 125 #define LPC_CHAN_IRQSEL2_IRQ7 0x70080000 // LPC Channel IRQSEL2 IRQ7 126 #define LPC_CHAN_IRQSEL2_IRQ8 0x80080000 // LPC Channel IRQSEL2 IRQ8 127 #define LPC_CHAN_IRQSEL2_IRQ9 0x90080000 // LPC Channel IRQSEL2 IRQ9 128 #define LPC_CHAN_IRQSEL2_IRQ10 0xA0080000 // LPC Channel IRQSEL2 IRQ10 129 #define LPC_CHAN_IRQSEL2_IRQ11 0xB0080000 // LPC Channel IRQSEL2 IRQ11 130 #define LPC_CHAN_IRQSEL2_IRQ12 0xC0080000 // LPC Channel IRQSEL2 IRQ12 131 #define LPC_CHAN_IRQSEL2_IRQ13 0xD0080000 // LPC Channel IRQSEL2 IRQ13 132 #define LPC_CHAN_IRQSEL2_IRQ14 0xE0080000 // LPC Channel IRQSEL2 IRQ14 133 #define LPC_CHAN_IRQSEL2_IRQ15 0xF0080000 // LPC Channel IRQSEL2 IRQ15 134 135 #define LPC_CHAN_COMxIRQ_DISABLE \ 136 0x00000000 // LCP Channel COMx IRQ Disabled 137 #define LPC_CHAN_COMxIRQ_ENABLE 0x00080000 // LCP Channel COMx IRQ Enabled 138 139 #define LPC_CHAN_IRQSEL1_NONE 0x00000000 // LPC Channel IRQSEL1 Disabled 140 #define LPC_CHAN_IRQSEL1_IRQ0 0x00040000 // LPC Channel IRQSEL1 IRQ0 141 #define LPC_CHAN_IRQSEL1_IRQ1 0x01040000 // LPC Channel IRQSEL1 IRQ1 142 #define LPC_CHAN_IRQSEL1_IRQ2 0x02040000 // LPC Channel IRQSEL1 IRQ2 143 #define LPC_CHAN_IRQSEL1_IRQ3 0x03040000 // LPC Channel IRQSEL1 IRQ3 144 #define LPC_CHAN_IRQSEL1_IRQ4 0x04040000 // LPC Channel IRQSEL1 IRQ4 145 #define LPC_CHAN_IRQSEL1_IRQ5 0x05040000 // LPC Channel IRQSEL1 IRQ5 146 #define LPC_CHAN_IRQSEL1_IRQ6 0x06040000 // LPC Channel IRQSEL1 IRQ6 147 #define LPC_CHAN_IRQSEL1_IRQ7 0x07040000 // LPC Channel IRQSEL1 IRQ7 148 #define LPC_CHAN_IRQSEL1_IRQ8 0x08040000 // LPC Channel IRQSEL1 IRQ8 149 #define LPC_CHAN_IRQSEL1_IRQ9 0x09040000 // LPC Channel IRQSEL1 IRQ9 150 #define LPC_CHAN_IRQSEL1_IRQ10 0x0A040000 // LPC Channel IRQSEL1 IRQ10 151 #define LPC_CHAN_IRQSEL1_IRQ11 0x0B040000 // LPC Channel IRQSEL1 IRQ11 152 #define LPC_CHAN_IRQSEL1_IRQ12 0x0C040000 // LPC Channel IRQSEL1 IRQ12 153 #define LPC_CHAN_IRQSEL1_IRQ13 0x0D040000 // LPC Channel IRQSEL1 IRQ13 154 #define LPC_CHAN_IRQSEL1_IRQ14 0x0E040000 // LPC Channel IRQSEL1 IRQ14 155 #define LPC_CHAN_IRQSEL1_IRQ15 0x0F040000 // LPC Channel IRQSEL1 IRQ15 156 157 #define LPC_CHAN_IRQSEL0_NONE 0x00000000 // LPC Channel IRQSEL0 Disabled 158 #define LPC_CHAN_IRQSEL0_IRQ0 0x00000000 // LPC Channel IRQSEL0 IRQ0 159 #define LPC_CHAN_IRQSEL0_IRQ1 0x00100000 // LPC Channel IRQSEL0 IRQ1 160 #define LPC_CHAN_IRQSEL0_IRQ2 0x00200000 // LPC Channel IRQSEL0 IRQ2 161 #define LPC_CHAN_IRQSEL0_IRQ3 0x00300000 // LPC Channel IRQSEL0 IRQ3 162 #define LPC_CHAN_IRQSEL0_IRQ4 0x00400000 // LPC Channel IRQSEL0 IRQ4 163 #define LPC_CHAN_IRQSEL0_IRQ5 0x00500000 // LPC Channel IRQSEL0 IRQ5 164 #define LPC_CHAN_IRQSEL0_IRQ6 0x00600000 // LPC Channel IRQSEL0 IRQ6 165 #define LPC_CHAN_IRQSEL0_IRQ7 0x00700000 // LPC Channel IRQSEL0 IRQ7 166 #define LPC_CHAN_IRQSEL0_IRQ8 0x00800000 // LPC Channel IRQSEL0 IRQ8 167 #define LPC_CHAN_IRQSEL0_IRQ9 0x00900000 // LPC Channel IRQSEL0 IRQ9 168 #define LPC_CHAN_IRQSEL0_IRQ10 0x00A00000 // LPC Channel IRQSEL0 IRQ10 169 #define LPC_CHAN_IRQSEL0_IRQ11 0x00B00000 // LPC Channel IRQSEL0 IRQ11 170 #define LPC_CHAN_IRQSEL0_IRQ12 0x00C00000 // LPC Channel IRQSEL0 IRQ12 171 #define LPC_CHAN_IRQSEL0_IRQ13 0x00D00000 // LPC Channel IRQSEL0 IRQ13 172 #define LPC_CHAN_IRQSEL0_IRQ14 0x00E00000 // LPC Channel IRQSEL0 IRQ14 173 #define LPC_CHAN_IRQSEL0_IRQ15 0x00F00000 // LPC Channel IRQSEL0 IRQ15 174 #define LPC_CHAN_IRQEN0_OFF 0x00000000 // LPC Channel IRQEN0 Disabled 175 #define LPC_CHAN_IRQEN0_TRG1 0x00010000 // LPC Channel IRQEN0 Trigger 1 176 #define LPC_CHAN_IRQEN0_TRG2 0x00020000 // LPC Channel IRQEN0 Trigger 2 177 #define LPC_CHAN_IRQEN0_TRG3 0x00030000 // LPC Channel IRQEN0 Trigger 3 178 179 #define LPC_CHAN_MBARB_ENABLED 0x00000000 // LPC Channel Mailbox Arbritration 180 // enabled. 181 #define LPC_CHAN_MBARB_DISABLED 0x00008000 // LPC Channel Mailbox Arbritration 182 // disabled. 183 184 #define LPC_CHAN_SIZE_4 0x00000000 // Mailbox IO/Memory Window size 185 // is 4 Bytes. 186 #define LPC_CHAN_SIZE_8 0x00000004 // Mailbox IO/Memory Window size 187 // is 4 Bytes. 188 #define LPC_CHAN_SIZE_16 0x00000008 // Mailbox IO/Memory Window size 189 // is 4 Bytes. 190 #define LPC_CHAN_SIZE_32 0x0000000C // Mailbox IO/Memory Window size 191 // is 4 Bytes. 192 #define LPC_CHAN_SIZE_64 0x00000010 // Mailbox IO/Memory Window size 193 // is 4 Bytes. 194 #define LPC_CHAN_SIZE_128 0x00000014 // Mailbox IO/Memory Window size 195 // is 4 Bytes. 196 #define LPC_CHAN_SIZE_256 0x00000018 // Mailbox IO/Memory Window size 197 // is 4 Bytes. 198 #define LPC_CHAN_SIZE_512 0x0000001C // Mailbox IO/Memory Window size 199 // is 4 Bytes. 200 201 //***************************************************************************** 202 // 203 // Values that can be passed to LCPChannelConfigCOMxSet as the ulCOMxMode 204 // parameter or returned from LPCChannelConfigGet in the pulCOMxMode 205 // parameter. 206 // 207 //***************************************************************************** 208 #define LPC_COMx_MODE_FRMHNML 0x00000000 // Normal From Host model. 209 #define LPC_COMx_MODE_FRMHIGN 0x00020000 // Ignore From Host data. 210 #define LPC_COMx_MODE_FRMHDMA 0x00040000 // COMx DMA on From Host data to 211 // memory 212 #define LPC_COMx_MODE_UARTDMA 0x00060000 // COMx DMA on From Host data to 213 // UART1 214 215 //***************************************************************************** 216 // 217 // Additinal values that can be returned from LPCChannelConfigGet in the 218 // pulCOMxMode parameter. 219 // 220 //***************************************************************************** 221 #define LPC_COMx_ENABLED 0x00010000 // COMx mode enabled. 222 223 //***************************************************************************** 224 // 225 // Values that can be passed to LPCIntEnable, LPCIntDisable, and LPCIntClear 226 // as the ulIntFlags parameter and returned by LPCIntStatus. 227 // 228 //***************************************************************************** 229 #define LPC_INT_RST 0x80000000 // LPC Bus Enters or Exits 230 // Reset State. 231 #define LPC_INT_SLEEP 0x40000000 // LPC Bus Enters or Exits 232 // Sleep State. 233 #define LPC_INT_COMx 0x20000000 // COMx has read/written 234 // data. 235 #define LPC_INT_SIRQ 0x10000000 // SERIRQ frame has completed 236 #define LPC_INT_CH6_EP_TO_HOST (1 << 24) // To-Host has been read. 237 #define LPC_INT_CH6_EP_FROM_DATA \ 238 (2 << 24) // From-Host has been written as 239 // data. 240 #define LPC_INT_CH6_EP_FROM_CMD (4 << 24) // From-Host has been written as 241 // command. 242 #define LPC_INT_CH6_MB_HOST_WON (1 << 24) // Host Won (HW1ST) 243 #define LPC_INT_CH6_MB_HOST_WRITE \ 244 (2 << 24) // Host Wrote Last Byte. 245 #define LPC_INT_CH6_MB_HOST_READ \ 246 (4 << 24) // Host Read Last Byte 247 #define LPC_INT_CH6_MB_MCU_LOST (8 << 24) // MCU Lost (when host had HW1ST). 248 #define LPC_INT_CH5_EP_TO_HOST (1 << 20) // To-Host has been read. 249 #define LPC_INT_CH5_EP_FROM_DATA \ 250 (2 << 20) // From-Host has been written as 251 // data. 252 #define LPC_INT_CH5_EP_FROM_CMD (4 << 20) // From-Host has been written as 253 // command. 254 #define LPC_INT_CH5_MB_HOST_WON (1 << 20) // Host Won (HW1ST) 255 #define LPC_INT_CH5_MB_HOST_WRITE \ 256 (2 << 20) // Host Wrote Last Byte. 257 #define LPC_INT_CH5_MB_HOST_READ \ 258 (4 << 20) // Host Read Last Byte 259 #define LPC_INT_CH5_MB_MCU_LOST (8 << 20) // MCU Lost (when host had HW1ST). 260 #define LPC_INT_CH4_EP_TO_HOST (1 << 16) // To-Host has been read. 261 #define LPC_INT_CH4_EP_FROM_DATA \ 262 (2 << 16) // From-Host has been written as 263 // data. 264 #define LPC_INT_CH4_EP_FROM_CMD (4 << 16) // From-Host has been written as 265 // command. 266 #define LPC_INT_CH4_MB_HOST_WON (1 << 16) // Host Won (HW1ST) 267 #define LPC_INT_CH4_MB_HOST_WRITE \ 268 (2 << 16) // Host Wrote Last Byte. 269 #define LPC_INT_CH4_MB_HOST_READ \ 270 (4 << 16) // Host Read Last Byte 271 #define LPC_INT_CH4_MB_MCU_LOST (8 << 16) // MCU Lost (when host had HW1ST). 272 #define LPC_INT_CH3_EP_TO_HOST (1 << 12) // To-Host has been read. 273 #define LPC_INT_CH3_EP_FROM_DATA \ 274 (2 << 12) // From-Host has been written as 275 // data. 276 #define LPC_INT_CH3_EP_FROM_CMD (4 << 12) // From-Host has been written as 277 // command. 278 #define LPC_INT_CH3_MB_HOST_WON (1 << 12) // Host Won (HW1ST) 279 #define LPC_INT_CH3_MB_HOST_WRITE \ 280 (2 << 12) // Host Wrote Last Byte. 281 #define LPC_INT_CH3_MB_HOST_READ \ 282 (4 << 12) // Host Read Last Byte 283 #define LPC_INT_CH3_MB_MCU_LOST (8 << 12) // MCU Lost (when host had HW1ST). 284 #define LPC_INT_CH2_EP_TO_HOST (1 << 8) // To-Host has been read. 285 #define LPC_INT_CH2_EP_FROM_DATA \ 286 (2 << 8) // From-Host has been written as 287 // data. 288 #define LPC_INT_CH2_EP_FROM_CMD (4 << 8) // From-Host has been written as 289 // command. 290 #define LPC_INT_CH2_MB_HOST_WON (1 << 8) // Host Won (HW1ST) 291 #define LPC_INT_CH2_MB_HOST_WRITE \ 292 (2 << 8) // Host Wrote Last Byte. 293 #define LPC_INT_CH2_MB_HOST_READ \ 294 (4 << 8) // Host Read Last Byte 295 #define LPC_INT_CH2_MB_MCU_LOST (8 << 8) // MCU Lost (when host had HW1ST). 296 #define LPC_INT_CH1_EP_TO_HOST (1 << 4) // To-Host has been read. 297 #define LPC_INT_CH1_EP_FROM_DATA \ 298 (2 << 4) // From-Host has been written as 299 // data. 300 #define LPC_INT_CH1_EP_FROM_CMD (4 << 4) // From-Host has been written as 301 // command. 302 #define LPC_INT_CH1_MB_HOST_WON (1 << 4) // Host Won (HW1ST) 303 #define LPC_INT_CH1_MB_HOST_WRITE \ 304 (2 << 4) // Host Wrote Last Byte. 305 #define LPC_INT_CH1_MB_HOST_READ \ 306 (4 << 4) // Host Read Last Byte 307 #define LPC_INT_CH1_MB_MCU_LOST (8 << 4) // MCU Lost (when host had HW1ST). 308 #define LPC_INT_CH0_EP_TO_HOST (1 << 0) // To-Host has been read. 309 #define LPC_INT_CH0_EP_FROM_DATA \ 310 (2 << 0) // From-Host has been written as 311 // data. 312 #define LPC_INT_CH0_EP_FROM_CMD (4 << 0) // From-Host has been written as 313 // command. 314 #define LPC_INT_CH0_MB_HOST_WON (1 << 0) // Host Won (HW1ST) 315 #define LPC_INT_CH0_MB_HOST_WRITE \ 316 (2 << 0) // Host Wrote Last Byte. 317 #define LPC_INT_CH0_MB_HOST_READ \ 318 (4 << 0) // Host Read Last Byte 319 #define LPC_INT_CH0_MB_MCU_LOST (8 << 0) // MCU Lost (when host had HW1ST). 320 321 //***************************************************************************** 322 // 323 // Values that can be passed to LPCCOMxInt... functions as the ulIntFlags 324 // parameter and returned by LPCIntStatus. 325 // 326 //***************************************************************************** 327 #define LPC_COMx_INT_CX 0x02000000 // Raw Event State for COMx 328 #define LPC_COMx_INT_CXTX 0x01000000 // Raw Event State for COMx TX 329 #define LPC_COMx_INT_CXRX 0x00800000 // Raw Event State for COMx RX 330 #define LPC_COMx_MASK_CX 0x00200000 // Event Mask for COMx 331 #define LPC_COMx_MASK_CXTX 0x00100000 // Event Mask for COMx TX 332 #define LPC_COMx_MASK_CXRX 0x00080000 // Event Mask for COMx RX 333 334 //***************************************************************************** 335 // 336 // Values that can be passed to the LPCChannelDMAConfigSet function as part 337 // of the ulConfig or ulMask parameter, or can be returned from the 338 // LPCChannelConfigGet function. 339 // 340 //***************************************************************************** 341 #define LPC_DMA_CH3_WEN 0x00000080 // Trigger DMA for "To Host" data 342 // buffer is empty. 343 #define LPC_DMA_CH3_REN 0x00000040 // Trigger DMA when "From Host" 344 // data buffer is full. 345 #define LPC_DMA_CH2_WEN 0x00000020 // Trigger DMA for "To Host" data 346 // buffer is empty. 347 #define LPC_DMA_CH2_REN 0x00000010 // Trigger DMA when "From Host" 348 // data buffer is full. 349 #define LPC_DMA_CH1_WEN 0x00000008 // Trigger DMA for "To Host" data 350 // buffer is empty. 351 #define LPC_DMA_CH1_REN 0x00000004 // Trigger DMA when "From Host" 352 // data buffer is full. 353 #define LPC_DMA_CH0_WEN 0x00000002 // Trigger DMA for "To Host" data 354 // buffer is empty. 355 #define LPC_DMA_CH0_REN 0x00000001 // Trigger DMA when "From Host" 356 // data buffer is full. 357 //***************************************************************************** 358 // 359 // Values that can be passed to the LPCChannelStatusSet and 360 // LPCChannelStatusClear function, and returned by the LPCChannelStatusGet 361 // function. 362 // 363 //***************************************************************************** 364 #define LPC_CH_ST_USER0 0x00000100 // User Status Bit 0 365 #define LPC_CH_ST_USER1 0x00000200 // User Status Bit 1 366 #define LPC_CH_ST_USER2 0x00000400 // User Status Bit 2 367 #define LPC_CH_ST_USER3 0x00000800 // User Status Bit 3 368 #define LPC_CH_ST_USER4 0x00001000 // User Status Bit 4 369 370 //***************************************************************************** 371 // 372 // Additinoal values that can be returned by the LPCChannelStatusGet function. 373 // 374 //***************************************************************************** 375 #define LPC_CH_ST_LASTHW 0x00000080 // Last Host Write 376 #define LPC_CH_ST_HW1ST 0x00000040 // First Host Write 377 #define LPC_CH_ST_LASTSW 0x00000020 // Last Slave Write 378 #define LPC_CH_ST_SW1ST 0x00000010 // First Slave Write 379 #define LPC_CH_ST_CMD 0x00000008 // Command or Data 380 #define LPC_CH_ST_FRMH 0x00000002 // From-Host Transaction 381 #define LPC_CH_ST_TOH 0x00000001 // To-Host Transaction 382 383 //***************************************************************************** 384 // 385 // Prototypes for the APIs. 386 // 387 //***************************************************************************** 388 extern void LPCConfigSet(unsigned long ulBase, unsigned long ulConfig); 389 extern unsigned long LPCConfigGet(unsigned long ulBase); 390 extern unsigned long LPCStatusGet(unsigned long ulBase, 391 unsigned long *pulCount, 392 unsigned long *pulPoolSize); 393 extern void LPCStatusBlockAddressSet(unsigned long ulBase, 394 unsigned long ulAddress, 395 tBoolean bEnabled); 396 extern unsigned LPCStatusBlockAddressGet(unsigned long ulBase); 397 extern void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount); 398 extern void LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse, 399 tBoolean bIRQOnChange); 400 extern void LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ); 401 extern void LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ); 402 extern unsigned long LPCIRQGet(unsigned long ulBase); 403 extern void LPCIRQSend(unsigned long ulBase); 404 extern void LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); 405 extern void LPCIntUnregister(unsigned long ulBase); 406 extern void LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags); 407 extern void LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags); 408 extern unsigned long LPCIntStatus(unsigned long ulBase, tBoolean bMasked); 409 extern void LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags); 410 extern void LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel); 411 extern void LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel); 412 extern void LPCChannelConfigEPSet(unsigned long ulBase, 413 unsigned long ulChannel, 414 unsigned long ulConfig, 415 unsigned long ulAddress, 416 unsigned long ulOffset); 417 extern void LPCChannelConfigMBSet(unsigned long ulBase, 418 unsigned long ulChannel, 419 unsigned long ulConfig, 420 unsigned long ulAddress, 421 unsigned long ulOffset); 422 extern void LPCChannelConfigCOMxSet(unsigned long ulBase, 423 unsigned long ulChannel, 424 unsigned long ulConfig, 425 unsigned long ulAddress, 426 unsigned long ulOffset, 427 unsigned long ulCOMxMode); 428 extern unsigned long LPCChannelConfigGet(unsigned long ulBase, 429 unsigned long ulChannel, 430 unsigned long *pulAddress, 431 unsigned long *pulOffset, 432 unsigned long *pulCOMxMode); 433 extern unsigned long LPCChannelPoolAddressGet(unsigned long ulBase, 434 unsigned long ulChannel); 435 extern unsigned long LPCChannelStatusGet(unsigned long ulBase, 436 unsigned long ulChannel); 437 extern void LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel, 438 unsigned long ulStatus); 439 extern void LPCChannelStatusClear(unsigned long ulBase, 440 unsigned long ulChannel, 441 unsigned long ulStatus); 442 extern void LPCChannelDMAConfigSet(unsigned long ulBase, 443 unsigned long ulConfig, 444 unsigned long ulMask); 445 extern unsigned long LPCChannelDMAConfigGet(unsigned long ulBase); 446 extern unsigned char LPCByteRead(unsigned long ulBase, unsigned long ulOffset); 447 extern void LPCByteWrite(unsigned long ulBase, unsigned long ulOffset, 448 unsigned char ucData); 449 extern unsigned short LPCHalfWordRead(unsigned long ulBase, 450 unsigned long ulOffset); 451 extern void LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset, 452 unsigned short usData); 453 extern unsigned long LPCWordRead(unsigned long ulBase, unsigned long ulOffset); 454 extern void LPCWordWrite(unsigned long ulBase, unsigned long ulOffset, 455 unsigned long ulData); 456 extern void LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags); 457 extern void LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags); 458 extern unsigned long LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked); 459 extern void LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags); 460 461 //***************************************************************************** 462 // 463 // Mark the end of the C bindings section for C++ compilers. 464 // 465 //***************************************************************************** 466 #ifdef __cplusplus 467 } 468 #endif 469 470 #endif // __LPC_H__ 471