1 //***************************************************************************** 2 // 3 // sysctl.h - Prototypes for the system control driver. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Peripheral Driver Library. 22 // 23 //***************************************************************************** 24 25 #ifndef __SYSCTL_H__ 26 #define __SYSCTL_H__ 27 28 //***************************************************************************** 29 // 30 // If building with a C++ compiler, make all of the definitions in this header 31 // have a C binding. 32 // 33 //***************************************************************************** 34 #ifdef __cplusplus 35 extern "C" 36 { 37 #endif 38 39 //***************************************************************************** 40 // 41 // The following are values that can be passed to the 42 // SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), 43 // SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the 44 // ulPeripheral parameter. The peripherals in the fourth group (upper nibble 45 // is 3) can only be used with the SysCtlPeripheralPresent() API. 46 // 47 //***************************************************************************** 48 #ifndef DEPRECATED 49 #define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog 50 #endif 51 #define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0 52 #define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module 53 #ifndef DEPRECATED 54 #define SYSCTL_PERIPH_ADC 0x00100001 // ADC 55 #endif 56 #define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0 57 #define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1 58 #ifndef DEPRECATED 59 #define SYSCTL_PERIPH_PWM 0x00100010 // PWM 60 #endif 61 #define SYSCTL_PERIPH_PWM0 0x00100010 // PWM 62 #define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 63 #define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 64 #define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 65 #define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1 66 #define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 67 #define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 68 #define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 69 #ifndef DEPRECATED 70 #define SYSCTL_PERIPH_SSI 0x10000010 // SSI 71 #endif 72 #define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 73 #define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 74 #ifndef DEPRECATED 75 #define SYSCTL_PERIPH_QEI 0x10000100 // QEI 76 #endif 77 #define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 78 #define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 79 #ifndef DEPRECATED 80 #define SYSCTL_PERIPH_I2C 0x10001000 // I2C 81 #endif 82 #define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 83 #define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 84 #define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 85 #define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 86 #define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 87 #define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 88 #define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 89 #define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 90 #define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 91 #define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0 92 #define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0 93 #define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A 94 #define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B 95 #define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C 96 #define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D 97 #define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E 98 #define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F 99 #define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G 100 #define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H 101 #define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J 102 #define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA 103 #define SYSCTL_PERIPH_USB0 0x20100001 // USB0 104 #define SYSCTL_PERIPH_ETH 0x20105000 // ETH 105 #define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 106 #define SYSCTL_PERIPH_PLL 0x30000010 // PLL 107 #define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor 108 #define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU 109 #define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0 110 #define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1 111 #define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0 112 #define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1 113 #define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2 114 #define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0 115 #define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 116 #define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 117 #define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A 118 #define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B 119 #define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C 120 #define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D 121 #define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E 122 #define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F 123 #define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G 124 #define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H 125 #define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J 126 #define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K 127 #define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L 128 #define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M 129 #define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N 130 #define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P 131 #define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q 132 #define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R 133 #define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S 134 #define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module 135 #define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0 136 #define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1 137 #define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 138 #define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 139 #define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 140 #define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 141 #define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0 142 #define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0 143 #define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0 144 #define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 145 #define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0 146 #define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1 147 #define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0 148 #define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1 149 #define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 150 #define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 151 #define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0 152 #define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1 153 #define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2 154 #define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3 155 #define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 156 #define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 157 #define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 158 #define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 159 #define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 160 #define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 161 #define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 162 #define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 163 #define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0 164 #define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1 165 #define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2 166 #define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 167 #define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 168 #define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 169 #define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 170 #define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 171 #define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA 172 #define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0 173 #define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0 174 #define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1 175 176 //***************************************************************************** 177 // 178 // The following are values that can be passed to the SysCtlPinPresent() API 179 // as the ulPin parameter. 180 // 181 //***************************************************************************** 182 #define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin 183 #define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin 184 #define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin 185 #define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin 186 #define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin 187 #define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin 188 #define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin 189 #define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin 190 #define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin 191 #define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin 192 #define SYSCTL_PIN_C0O 0x00000100 // C0o pin 193 #define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin 194 #define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin 195 #define SYSCTL_PIN_C1O 0x00000800 // C1o pin 196 #define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin 197 #define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin 198 #define SYSCTL_PIN_C2O 0x00004000 // C2o pin 199 #define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin 200 #define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin 201 #define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin 202 #define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin 203 #define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin 204 #define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin 205 #define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin 206 #define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin 207 #define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin 208 #define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin 209 #define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin 210 #define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin 211 #define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin 212 #define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin 213 #define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin 214 #define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin 215 216 //***************************************************************************** 217 // 218 // The following are values that can be passed to the SysCtlLDOSet() API as 219 // the ulVoltage value, or returned by the SysCtlLDOGet() API. 220 // 221 //***************************************************************************** 222 #define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V 223 #define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V 224 #define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V 225 #define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V 226 #define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V 227 #define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V 228 #define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V 229 #define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V 230 #define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V 231 #define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V 232 #define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V 233 234 //***************************************************************************** 235 // 236 // The following are values that can be passed to the SysCtlLDOConfigSet() API. 237 // 238 //***************************************************************************** 239 #define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset 240 #define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure 241 242 //***************************************************************************** 243 // 244 // The following are values that can be passed to the SysCtlIntEnable(), 245 // SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask 246 // by the SysCtlIntStatus() API. 247 // 248 //***************************************************************************** 249 #define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt 250 #define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt 251 #define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt 252 #define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt 253 #define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int 254 #define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int 255 #define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt 256 #define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt 257 #define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt 258 259 //***************************************************************************** 260 // 261 // The following are values that can be passed to the SysCtlResetCauseClear() 262 // API or returned by the SysCtlResetCauseGet() API. 263 // 264 //***************************************************************************** 265 #define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset 266 #define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog1 reset 267 #define SYSCTL_CAUSE_SW 0x00000010 // Software reset 268 #define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset 269 #define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset 270 #define SYSCTL_CAUSE_POR 0x00000002 // Power on reset 271 #define SYSCTL_CAUSE_EXT 0x00000001 // External reset 272 273 //***************************************************************************** 274 // 275 // The following are values that can be passed to the SysCtlBrownOutConfigSet() 276 // API as the ulConfig parameter. 277 // 278 //***************************************************************************** 279 #define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting 280 #define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting 281 282 //***************************************************************************** 283 // 284 // The following are values that can be passed to the SysCtlPWMClockSet() API 285 // as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() 286 // API. 287 // 288 //***************************************************************************** 289 #define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 290 #define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 291 #define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 292 #define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 293 #define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 294 #define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 295 #define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 296 297 //***************************************************************************** 298 // 299 // The following are values that can be passed to the SysCtlADCSpeedSet() API 300 // as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() 301 // API. 302 // 303 //***************************************************************************** 304 #define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second 305 #define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second 306 #define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second 307 #define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second 308 309 //***************************************************************************** 310 // 311 // The following are values that can be passed to the SysCtlClockSet() API as 312 // the ulConfig parameter. 313 // 314 //***************************************************************************** 315 #define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 316 #define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 317 #define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 318 #define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 319 #define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 320 #define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 321 #define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 322 #define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 323 #define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 324 #define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 325 #define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 326 #define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 327 #define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 328 #define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 329 #define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 330 #define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 331 #define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 332 #define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 333 #define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 334 #define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 335 #define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 336 #define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 337 #define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 338 #define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 339 #define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 340 #define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 341 #define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 342 #define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 343 #define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 344 #define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 345 #define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 346 #define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 347 #define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 348 #define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 349 #define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 350 #define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 351 #define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 352 #define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 353 #define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 354 #define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 355 #define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 356 #define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 357 #define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 358 #define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 359 #define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 360 #define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 361 #define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 362 #define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 363 #define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 364 #define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 365 #define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 366 #define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 367 #define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 368 #define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 369 #define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 370 #define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 371 #define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 372 #define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 373 #define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 374 #define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 375 #define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 376 #define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 377 #define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 378 #define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 379 #define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 380 #define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 381 #define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 382 #define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 383 #define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 384 #define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 385 #define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 386 #define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 387 #define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 388 #define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 389 #define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 390 #define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 391 #define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 392 #define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 393 #define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 394 #define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 395 #define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 396 #define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 397 #define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 398 #define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 399 #define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 400 #define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 401 #define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 402 #define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 403 #define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 404 #define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 405 #define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 406 #define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 407 #define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 408 #define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 409 #define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 410 #define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 411 #define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 412 #define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 413 #define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 414 #define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 415 #define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 416 #define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 417 #define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 418 #define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 419 #define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 420 #define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 421 #define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 422 #define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 423 #define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 424 #define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 425 #define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 426 #define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 427 #define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 428 #define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 429 #define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 430 #define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 431 #define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 432 #define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 433 #define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 434 #define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 435 #define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 436 #define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 437 #define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 438 #define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 439 #define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 440 #define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 441 #define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock 442 #define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock 443 #define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz 444 #define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz 445 #define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz 446 #define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz 447 #define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz 448 #define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz 449 #define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz 450 #define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz 451 #define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz 452 #define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz 453 #define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz 454 #define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz 455 #define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz 456 #define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz 457 #define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz 458 #define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz 459 #define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz 460 #define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz 461 #define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz 462 #define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz 463 #define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz 464 #define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz 465 #define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz 466 #define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz 467 #define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz 468 #define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz 469 #define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz 470 #define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc 471 #define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc 472 #define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 473 #define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz 474 #define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz 475 #define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz 476 #define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator 477 #define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator 478 479 //***************************************************************************** 480 // 481 // The following are values that can be passed to the SysCtlDeepSleepClockSet() 482 // API as the ulConfig parameter. 483 // 484 //***************************************************************************** 485 #define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 486 #define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 487 #define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 488 #define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 489 #define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 490 #define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 491 #define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 492 #define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 493 #define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 494 #define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 495 #define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 496 #define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 497 #define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 498 #define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 499 #define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 500 #define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 501 #define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 502 #define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 503 #define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 504 #define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 505 #define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 506 #define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 507 #define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 508 #define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 509 #define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 510 #define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 511 #define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 512 #define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 513 #define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 514 #define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 515 #define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 516 #define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 517 #define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 518 #define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 519 #define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 520 #define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 521 #define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 522 #define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 523 #define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 524 #define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 525 #define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 526 #define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 527 #define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 528 #define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 529 #define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 530 #define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 531 #define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 532 #define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 533 #define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 534 #define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 535 #define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 536 #define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 537 #define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 538 #define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 539 #define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 540 #define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 541 #define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 542 #define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 543 #define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 544 #define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 545 #define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 546 #define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 547 #define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 548 #define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 549 #define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc 550 #define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc 551 #define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz 552 #define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz 553 #define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep 554 555 //***************************************************************************** 556 // 557 // The following are values that can be passed to the SysCtlPIOSCCalibrate() 558 // API as the ulType parameter. 559 // 560 //***************************************************************************** 561 #define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration 562 #define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration 563 #define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration 564 565 //***************************************************************************** 566 // 567 // The following are values that can be passed to the SysCtlMOSCConfigSet() API 568 // as the ulConfig parameter. 569 // 570 //***************************************************************************** 571 #define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation 572 #define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail 573 #define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC 574 575 //***************************************************************************** 576 // 577 // Prototypes for the APIs. 578 // 579 //***************************************************************************** 580 extern unsigned long SysCtlSRAMSizeGet(void); 581 extern unsigned long SysCtlFlashSizeGet(void); 582 extern tBoolean SysCtlPinPresent(unsigned long ulPin); 583 extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); 584 extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral); 585 extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral); 586 extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral); 587 extern void SysCtlPeripheralReset(unsigned long ulPeripheral); 588 extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); 589 extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); 590 extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); 591 extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); 592 extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); 593 extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); 594 extern void SysCtlPeripheralClockGating(tBoolean bEnable); 595 extern void SysCtlIntRegister(void (*pfnHandler)(void)); 596 extern void SysCtlIntUnregister(void); 597 extern void SysCtlIntEnable(unsigned long ulInts); 598 extern void SysCtlIntDisable(unsigned long ulInts); 599 extern void SysCtlIntClear(unsigned long ulInts); 600 extern unsigned long SysCtlIntStatus(tBoolean bMasked); 601 extern void SysCtlLDOSet(unsigned long ulVoltage); 602 extern unsigned long SysCtlLDOGet(void); 603 extern void SysCtlLDOConfigSet(unsigned long ulConfig); 604 extern void SysCtlReset(void); 605 extern void SysCtlSleep(void); 606 extern void SysCtlDeepSleep(void); 607 extern unsigned long SysCtlResetCauseGet(void); 608 extern void SysCtlResetCauseClear(unsigned long ulCauses); 609 extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, 610 unsigned long ulDelay); 611 extern void SysCtlDelay(unsigned long ulCount); 612 extern void SysCtlMOSCConfigSet(unsigned long ulConfig); 613 extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType); 614 extern void SysCtlClockSet(unsigned long ulConfig); 615 extern unsigned long SysCtlClockGet(void); 616 extern void SysCtlDeepSleepClockSet(unsigned long ulConfig); 617 extern void SysCtlPWMClockSet(unsigned long ulConfig); 618 extern unsigned long SysCtlPWMClockGet(void); 619 extern void SysCtlADCSpeedSet(unsigned long ulSpeed); 620 extern unsigned long SysCtlADCSpeedGet(void); 621 extern void SysCtlIOSCVerificationSet(tBoolean bEnable); 622 extern void SysCtlMOSCVerificationSet(tBoolean bEnable); 623 extern void SysCtlPLLVerificationSet(tBoolean bEnable); 624 extern void SysCtlClkVerificationClear(void); 625 extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); 626 extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); 627 extern void SysCtlUSBPLLEnable(void); 628 extern void SysCtlUSBPLLDisable(void); 629 extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock, 630 unsigned long ulMClk); 631 632 //***************************************************************************** 633 // 634 // Mark the end of the C bindings section for C++ compilers. 635 // 636 //***************************************************************************** 637 #ifdef __cplusplus 638 } 639 #endif 640 641 #endif // __SYSCTL_H__ 642