1 //***************************************************************************** 2 // 3 // hw_can.h - Defines and macros used when accessing the CAN controllers. 4 // 5 // Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_CAN_H__ 26 #define __HW_CAN_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the CAN register offsets. 31 // 32 //***************************************************************************** 33 #define CAN_O_CTL 0x00000000 // CAN Control 34 #define CAN_O_STS 0x00000004 // CAN Status 35 #define CAN_O_ERR 0x00000008 // CAN Error Counter 36 #define CAN_O_BIT 0x0000000C // CAN Bit Timing 37 #define CAN_O_INT 0x00000010 // CAN Interrupt 38 #define CAN_O_TST 0x00000014 // CAN Test 39 #define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler 40 // Extension 41 #define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request 42 #define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask 43 #define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 44 #define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 45 #define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 46 #define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 47 #define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control 48 #define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 49 #define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 50 #define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 51 #define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 52 #define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request 53 #define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask 54 #define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 55 #define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 56 #define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 57 #define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 58 #define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control 59 #define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 60 #define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 61 #define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 62 #define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 63 #define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 64 #define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 65 #define CAN_O_NWDA1 0x00000120 // CAN New Data 1 66 #define CAN_O_NWDA2 0x00000124 // CAN New Data 2 67 #define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending 68 #define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending 69 #define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid 70 #define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid 71 72 //***************************************************************************** 73 // 74 // The following are defines for the bit fields in the CAN_O_CTL register. 75 // 76 //***************************************************************************** 77 #define CAN_CTL_TEST 0x00000080 // Test Mode Enable 78 #define CAN_CTL_CCE 0x00000040 // Configuration Change Enable 79 #define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission 80 #define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable 81 #define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable 82 #define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable 83 #define CAN_CTL_INIT 0x00000001 // Initialization 84 85 //***************************************************************************** 86 // 87 // The following are defines for the bit fields in the CAN_O_STS register. 88 // 89 //***************************************************************************** 90 #define CAN_STS_BOFF 0x00000080 // Bus-Off Status 91 #define CAN_STS_EWARN 0x00000040 // Warning Status 92 #define CAN_STS_EPASS 0x00000020 // Error Passive 93 #define CAN_STS_RXOK 0x00000010 // Received a Message Successfully 94 #define CAN_STS_TXOK 0x00000008 // Transmitted a Message 95 // Successfully 96 #define CAN_STS_LEC_M 0x00000007 // Last Error Code 97 #define CAN_STS_LEC_NONE 0x00000000 // No Error 98 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error 99 #define CAN_STS_LEC_FORM 0x00000002 // Format Error 100 #define CAN_STS_LEC_ACK 0x00000003 // ACK Error 101 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error 102 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error 103 #define CAN_STS_LEC_CRC 0x00000006 // CRC Error 104 #define CAN_STS_LEC_NOEVENT 0x00000007 // No Event 105 106 //***************************************************************************** 107 // 108 // The following are defines for the bit fields in the CAN_O_ERR register. 109 // 110 //***************************************************************************** 111 #define CAN_ERR_RP 0x00008000 // Received Error Passive 112 #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter 113 #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter 114 #define CAN_ERR_REC_S 8 115 #define CAN_ERR_TEC_S 0 116 117 //***************************************************************************** 118 // 119 // The following are defines for the bit fields in the CAN_O_BIT register. 120 // 121 //***************************************************************************** 122 #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point 123 #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point 124 #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width 125 #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler 126 #define CAN_BIT_TSEG2_S 12 127 #define CAN_BIT_TSEG1_S 8 128 #define CAN_BIT_SJW_S 6 129 #define CAN_BIT_BRP_S 0 130 131 //***************************************************************************** 132 // 133 // The following are defines for the bit fields in the CAN_O_INT register. 134 // 135 //***************************************************************************** 136 #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier 137 #define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending 138 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt 139 140 //***************************************************************************** 141 // 142 // The following are defines for the bit fields in the CAN_O_TST register. 143 // 144 //***************************************************************************** 145 #define CAN_TST_RX 0x00000080 // Receive Observation 146 #define CAN_TST_TX_M 0x00000060 // Transmit Control 147 #define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control 148 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point 149 #define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low 150 #define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High 151 #define CAN_TST_LBACK 0x00000010 // Loopback Mode 152 #define CAN_TST_SILENT 0x00000008 // Silent Mode 153 #define CAN_TST_BASIC 0x00000004 // Basic Mode 154 155 //***************************************************************************** 156 // 157 // The following are defines for the bit fields in the CAN_O_BRPE register. 158 // 159 //***************************************************************************** 160 #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension 161 #define CAN_BRPE_BRPE_S 0 162 163 //***************************************************************************** 164 // 165 // The following are defines for the bit fields in the CAN_O_IF1CRQ register. 166 // 167 //***************************************************************************** 168 #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag 169 #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number 170 #define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; 171 // it is interpreted as 0x20, or 172 // object 32 173 #define CAN_IF1CRQ_MNUM_S 0 174 175 //***************************************************************************** 176 // 177 // The following are defines for the bit fields in the CAN_O_IF1CMSK register. 178 // 179 //***************************************************************************** 180 #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read 181 #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits 182 #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits 183 #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits 184 #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 185 #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data 186 #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request 187 #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 188 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 189 190 //***************************************************************************** 191 // 192 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register. 193 // 194 //***************************************************************************** 195 #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 196 #define CAN_IF1MSK1_IDMSK_S 0 197 198 //***************************************************************************** 199 // 200 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register. 201 // 202 //***************************************************************************** 203 #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier 204 #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction 205 #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask 206 #define CAN_IF1MSK2_IDMSK_S 0 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register. 211 // 212 //***************************************************************************** 213 #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier 214 #define CAN_IF1ARB1_ID_S 0 215 216 //***************************************************************************** 217 // 218 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register. 219 // 220 //***************************************************************************** 221 #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid 222 #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier 223 #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction 224 #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier 225 #define CAN_IF1ARB2_ID_S 0 226 227 //***************************************************************************** 228 // 229 // The following are defines for the bit fields in the CAN_O_IF1MCTL register. 230 // 231 //***************************************************************************** 232 #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data 233 #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost 234 #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending 235 #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask 236 #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 237 #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable 238 #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable 239 #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request 240 #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer 241 #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code 242 #define CAN_IF1MCTL_DLC_S 0 243 244 //***************************************************************************** 245 // 246 // The following are defines for the bit fields in the CAN_O_IF1DA1 register. 247 // 248 //***************************************************************************** 249 #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data 250 #define CAN_IF1DA1_DATA_S 0 251 252 //***************************************************************************** 253 // 254 // The following are defines for the bit fields in the CAN_O_IF1DA2 register. 255 // 256 //***************************************************************************** 257 #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data 258 #define CAN_IF1DA2_DATA_S 0 259 260 //***************************************************************************** 261 // 262 // The following are defines for the bit fields in the CAN_O_IF1DB1 register. 263 // 264 //***************************************************************************** 265 #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data 266 #define CAN_IF1DB1_DATA_S 0 267 268 //***************************************************************************** 269 // 270 // The following are defines for the bit fields in the CAN_O_IF1DB2 register. 271 // 272 //***************************************************************************** 273 #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data 274 #define CAN_IF1DB2_DATA_S 0 275 276 //***************************************************************************** 277 // 278 // The following are defines for the bit fields in the CAN_O_IF2CRQ register. 279 // 280 //***************************************************************************** 281 #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag 282 #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number 283 #define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; 284 // it is interpreted as 0x20, or 285 // object 32 286 #define CAN_IF2CRQ_MNUM_S 0 287 288 //***************************************************************************** 289 // 290 // The following are defines for the bit fields in the CAN_O_IF2CMSK register. 291 // 292 //***************************************************************************** 293 #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read 294 #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits 295 #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits 296 #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits 297 #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 298 #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data 299 #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request 300 #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 301 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 302 303 //***************************************************************************** 304 // 305 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register. 306 // 307 //***************************************************************************** 308 #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 309 #define CAN_IF2MSK1_IDMSK_S 0 310 311 //***************************************************************************** 312 // 313 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register. 314 // 315 //***************************************************************************** 316 #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier 317 #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction 318 #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask 319 #define CAN_IF2MSK2_IDMSK_S 0 320 321 //***************************************************************************** 322 // 323 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register. 324 // 325 //***************************************************************************** 326 #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier 327 #define CAN_IF2ARB1_ID_S 0 328 329 //***************************************************************************** 330 // 331 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register. 332 // 333 //***************************************************************************** 334 #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid 335 #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier 336 #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction 337 #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier 338 #define CAN_IF2ARB2_ID_S 0 339 340 //***************************************************************************** 341 // 342 // The following are defines for the bit fields in the CAN_O_IF2MCTL register. 343 // 344 //***************************************************************************** 345 #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data 346 #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost 347 #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending 348 #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask 349 #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 350 #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable 351 #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable 352 #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request 353 #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer 354 #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code 355 #define CAN_IF2MCTL_DLC_S 0 356 357 //***************************************************************************** 358 // 359 // The following are defines for the bit fields in the CAN_O_IF2DA1 register. 360 // 361 //***************************************************************************** 362 #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data 363 #define CAN_IF2DA1_DATA_S 0 364 365 //***************************************************************************** 366 // 367 // The following are defines for the bit fields in the CAN_O_IF2DA2 register. 368 // 369 //***************************************************************************** 370 #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data 371 #define CAN_IF2DA2_DATA_S 0 372 373 //***************************************************************************** 374 // 375 // The following are defines for the bit fields in the CAN_O_IF2DB1 register. 376 // 377 //***************************************************************************** 378 #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data 379 #define CAN_IF2DB1_DATA_S 0 380 381 //***************************************************************************** 382 // 383 // The following are defines for the bit fields in the CAN_O_IF2DB2 register. 384 // 385 //***************************************************************************** 386 #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data 387 #define CAN_IF2DB2_DATA_S 0 388 389 //***************************************************************************** 390 // 391 // The following are defines for the bit fields in the CAN_O_TXRQ1 register. 392 // 393 //***************************************************************************** 394 #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits 395 #define CAN_TXRQ1_TXRQST_S 0 396 397 //***************************************************************************** 398 // 399 // The following are defines for the bit fields in the CAN_O_TXRQ2 register. 400 // 401 //***************************************************************************** 402 #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits 403 #define CAN_TXRQ2_TXRQST_S 0 404 405 //***************************************************************************** 406 // 407 // The following are defines for the bit fields in the CAN_O_NWDA1 register. 408 // 409 //***************************************************************************** 410 #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits 411 #define CAN_NWDA1_NEWDAT_S 0 412 413 //***************************************************************************** 414 // 415 // The following are defines for the bit fields in the CAN_O_NWDA2 register. 416 // 417 //***************************************************************************** 418 #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits 419 #define CAN_NWDA2_NEWDAT_S 0 420 421 //***************************************************************************** 422 // 423 // The following are defines for the bit fields in the CAN_O_MSG1INT register. 424 // 425 //***************************************************************************** 426 #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 427 #define CAN_MSG1INT_INTPND_S 0 428 429 //***************************************************************************** 430 // 431 // The following are defines for the bit fields in the CAN_O_MSG2INT register. 432 // 433 //***************************************************************************** 434 #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 435 #define CAN_MSG2INT_INTPND_S 0 436 437 //***************************************************************************** 438 // 439 // The following are defines for the bit fields in the CAN_O_MSG1VAL register. 440 // 441 //***************************************************************************** 442 #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 443 #define CAN_MSG1VAL_MSGVAL_S 0 444 445 //***************************************************************************** 446 // 447 // The following are defines for the bit fields in the CAN_O_MSG2VAL register. 448 // 449 //***************************************************************************** 450 #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 451 #define CAN_MSG2VAL_MSGVAL_S 0 452 453 //***************************************************************************** 454 // 455 // The following definitions are deprecated. 456 // 457 //***************************************************************************** 458 #ifndef DEPRECATED 459 460 //***************************************************************************** 461 // 462 // The following are deprecated defines for the CAN register offsets. 463 // 464 //***************************************************************************** 465 #define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg 466 #define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg 467 #define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg 468 #define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg 469 470 //***************************************************************************** 471 // 472 // The following are deprecated defines for the bit fields in the CAN_O_STS 473 // register. 474 // 475 //***************************************************************************** 476 #define CAN_STS_LEC_MSK 0x00000007 // Last Error Code 477 478 //***************************************************************************** 479 // 480 // The following are deprecated defines for the bit fields in the CAN_O_ERR 481 // register. 482 // 483 //***************************************************************************** 484 #define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status 485 #define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status 486 #define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos 487 #define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos 488 489 //***************************************************************************** 490 // 491 // The following are deprecated defines for the bit fields in the CAN_O_BIT 492 // register. 493 // 494 //***************************************************************************** 495 #define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point 496 #define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point 497 #define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width 498 #define CAN_BIT_BRP 0x0000003F // Baud rate prescaler 499 500 //***************************************************************************** 501 // 502 // The following are deprecated defines for the bit fields in the CAN_O_INT 503 // register. 504 // 505 //***************************************************************************** 506 #define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier 507 508 //***************************************************************************** 509 // 510 // The following are deprecated defines for the bit fields in the CAN_O_TST 511 // register. 512 // 513 //***************************************************************************** 514 #define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin 515 516 //***************************************************************************** 517 // 518 // The following are deprecated defines for the bit fields in the CAN_O_BRPE 519 // register. 520 // 521 //***************************************************************************** 522 #define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension 523 524 //***************************************************************************** 525 // 526 // The following are deprecated defines for the bit fields in the CAN_O_TXRQ1 527 // register. 528 // 529 //***************************************************************************** 530 #define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits 531 532 //***************************************************************************** 533 // 534 // The following are deprecated defines for the bit fields in the CAN_O_TXRQ2 535 // register. 536 // 537 //***************************************************************************** 538 #define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits 539 540 //***************************************************************************** 541 // 542 // The following are deprecated defines for the bit fields in the CAN_O_NWDA1 543 // register. 544 // 545 //***************************************************************************** 546 #define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits 547 548 //***************************************************************************** 549 // 550 // The following are deprecated defines for the bit fields in the CAN_O_NWDA2 551 // register. 552 // 553 //***************************************************************************** 554 #define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits 555 556 //***************************************************************************** 557 // 558 // The following are deprecated defines for the bit fields in the CAN_O_MSGINT1 559 // register. 560 // 561 //***************************************************************************** 562 #define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits 563 564 //***************************************************************************** 565 // 566 // The following are deprecated defines for the bit fields in the CAN_O_MSGINT2 567 // register. 568 // 569 //***************************************************************************** 570 #define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits 571 572 //***************************************************************************** 573 // 574 // The following are deprecated defines for the bit fields in the CAN_O_MSGVAL1 575 // register. 576 // 577 //***************************************************************************** 578 #define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits 579 580 //***************************************************************************** 581 // 582 // The following are deprecated defines for the bit fields in the CAN_O_MSGVAL2 583 // register. 584 // 585 //***************************************************************************** 586 #define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits 587 588 //***************************************************************************** 589 // 590 // The following are deprecated defines for the reset values of the can 591 // registers. 592 // 593 //***************************************************************************** 594 #define CAN_RV_IF1MSK2 0x0000FFFF 595 #define CAN_RV_IF1MSK1 0x0000FFFF 596 #define CAN_RV_IF2MSK1 0x0000FFFF 597 #define CAN_RV_IF2MSK2 0x0000FFFF 598 #define CAN_RV_BIT 0x00002301 599 #define CAN_RV_CTL 0x00000001 600 #define CAN_RV_IF1CRQ 0x00000001 601 #define CAN_RV_IF2CRQ 0x00000001 602 #define CAN_RV_TXRQ2 0x00000000 603 #define CAN_RV_IF2DB1 0x00000000 604 #define CAN_RV_INT 0x00000000 605 #define CAN_RV_IF1DB2 0x00000000 606 #define CAN_RV_BRPE 0x00000000 607 #define CAN_RV_IF2DA2 0x00000000 608 #define CAN_RV_MSGVAL2 0x00000000 609 #define CAN_RV_TXRQ1 0x00000000 610 #define CAN_RV_IF1MCTL 0x00000000 611 #define CAN_RV_IF1DB1 0x00000000 612 #define CAN_RV_STS 0x00000000 613 #define CAN_RV_MSGINT1 0x00000000 614 #define CAN_RV_IF1DA2 0x00000000 615 #define CAN_RV_TST 0x00000000 616 #define CAN_RV_IF1ARB1 0x00000000 617 #define CAN_RV_IF1ARB2 0x00000000 618 #define CAN_RV_NWDA2 0x00000000 619 #define CAN_RV_IF2CMSK 0x00000000 620 #define CAN_RV_NWDA1 0x00000000 621 #define CAN_RV_IF1DA1 0x00000000 622 #define CAN_RV_IF2DA1 0x00000000 623 #define CAN_RV_IF2MCTL 0x00000000 624 #define CAN_RV_MSGVAL1 0x00000000 625 #define CAN_RV_IF1CMSK 0x00000000 626 #define CAN_RV_ERR 0x00000000 627 #define CAN_RV_IF2ARB2 0x00000000 628 #define CAN_RV_MSGINT2 0x00000000 629 #define CAN_RV_IF2ARB1 0x00000000 630 #define CAN_RV_IF2DB2 0x00000000 631 632 //***************************************************************************** 633 // 634 // The following are deprecated defines for the bit fields in the CAN_IF1CRQ 635 // and CAN_IF1CRQ registers. 636 // Note: All bits may not be available in all registers. 637 // 638 //***************************************************************************** 639 #define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status 640 #define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number 641 642 //***************************************************************************** 643 // 644 // The following are deprecated defines for the bit fields in the CAN_IF1CMSK 645 // and CAN_IF2CMSK registers. 646 // Note: All bits may not be available in all registers. 647 // 648 //***************************************************************************** 649 #define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read 650 #define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits 651 #define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits 652 #define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits 653 #define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit 654 #define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) 655 #define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) 656 #define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 657 #define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 658 659 //***************************************************************************** 660 // 661 // The following are deprecated defines for the bit fields in the CAN_IF1MSK1 662 // and CAN_IF2MSK1 registers. 663 // Note: All bits may not be available in all registers. 664 // 665 //***************************************************************************** 666 #define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask 667 668 //***************************************************************************** 669 // 670 // The following are deprecated defines for the bit fields in the CAN_IF1MSK2 671 // and CAN_IF2MSK2 registers. 672 // Note: All bits may not be available in all registers. 673 // 674 //***************************************************************************** 675 #define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier 676 #define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction 677 #define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier 678 679 //***************************************************************************** 680 // 681 // The following are deprecated defines for the bit fields in the CAN_IF1ARB1 682 // and CAN_IF2ARB1 registers. 683 // Note: All bits may not be available in all registers. 684 // 685 //***************************************************************************** 686 #define CAN_IFARB1_ID 0x0000FFFF // Identifier 687 688 //***************************************************************************** 689 // 690 // The following are deprecated defines for the bit fields in the CAN_IF1ARB2 691 // and CAN_IF2ARB2 registers. 692 // Note: All bits may not be available in all registers. 693 // 694 //***************************************************************************** 695 #define CAN_IFARB2_MSGVAL 0x00008000 // Message valid 696 #define CAN_IFARB2_XTD 0x00004000 // Extended identifier 697 #define CAN_IFARB2_DIR 0x00002000 // Message direction 698 #define CAN_IFARB2_ID 0x00001FFF // Message identifier 699 700 //***************************************************************************** 701 // 702 // The following are deprecated defines for the bit fields in the CAN_IF1MCTL 703 // and CAN_IF2MCTL registers. 704 // Note: All bits may not be available in all registers. 705 // 706 //***************************************************************************** 707 #define CAN_IFMCTL_NEWDAT 0x00008000 // New Data 708 #define CAN_IFMCTL_MSGLST 0x00004000 // Message lost 709 #define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending 710 #define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask 711 #define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable 712 #define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable 713 #define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable 714 #define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request 715 #define CAN_IFMCTL_EOB 0x00000080 // End of buffer 716 #define CAN_IFMCTL_DLC 0x0000000F // Data length code 717 718 //***************************************************************************** 719 // 720 // The following are deprecated defines for the bit fields in the CAN_IF1DA1 721 // and CAN_IF2DA1 registers. 722 // Note: All bits may not be available in all registers. 723 // 724 //***************************************************************************** 725 #define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 726 727 //***************************************************************************** 728 // 729 // The following are deprecated defines for the bit fields in the CAN_IF1DA2 730 // and CAN_IF2DA2 registers. 731 // Note: All bits may not be available in all registers. 732 // 733 //***************************************************************************** 734 #define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 735 736 //***************************************************************************** 737 // 738 // The following are deprecated defines for the bit fields in the CAN_IF1DB1 739 // and CAN_IF2DB1 registers. 740 // Note: All bits may not be available in all registers. 741 // 742 //***************************************************************************** 743 #define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 744 745 //***************************************************************************** 746 // 747 // The following are deprecated defines for the bit fields in the CAN_IF1DB2 748 // and CAN_IF2DB2 registers. 749 // Note: All bits may not be available in all registers. 750 // 751 //***************************************************************************** 752 #define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 753 754 #endif 755 756 #endif // __HW_CAN_H__ 757