1 //***************************************************************************** 2 // 3 // hw_epi.h - Macros for use in accessing the EPI registers. 4 // 5 // Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_EPI_H__ 26 #define __HW_EPI_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the External Peripheral Interface register 31 // offsets. 32 // 33 //***************************************************************************** 34 #define EPI_O_CFG 0x00000000 // EPI Configuration 35 #define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate 36 #define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration 37 #define EPI_O_GPCFG 0x00000010 // EPI General-Purpose 38 // Configuration 39 #define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration 40 #define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration 41 #define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 42 #define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 43 #define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose 44 // Configuration 2 45 #define EPI_O_ADDRMAP 0x0000001C // EPI Address Map 46 #define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 47 #define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 48 #define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 49 #define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 50 #define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 51 #define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 52 #define EPI_O_STAT 0x00000060 // EPI Status 53 #define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count 54 #define EPI_O_READFIFO 0x00000070 // EPI Read FIFO 55 #define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 56 #define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 57 #define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 58 #define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 59 #define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 60 #define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 61 #define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 62 #define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects 63 #define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count 64 #define EPI_O_IM 0x00000210 // EPI Interrupt Mask 65 #define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status 66 #define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status 67 #define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and 68 // Clear 69 70 //***************************************************************************** 71 // 72 // The following are defines for the bit fields in the EPI_O_CFG register. 73 // 74 //***************************************************************************** 75 #define EPI_CFG_BLKEN 0x00000010 // Block Enable 76 #define EPI_CFG_MODE_M 0x0000000F // Mode Select 77 #define EPI_CFG_MODE_NONE 0x00000000 // General Purpose 78 #define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM 79 #define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) 80 #define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) 81 82 //***************************************************************************** 83 // 84 // The following are defines for the bit fields in the EPI_O_BAUD register. 85 // 86 //***************************************************************************** 87 #define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 88 #define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 89 #define EPI_BAUD_COUNT1_S 16 90 #define EPI_BAUD_COUNT0_S 0 91 92 //***************************************************************************** 93 // 94 // The following are defines for the bit fields in the EPI_O_HB16CFG register. 95 // 96 //***************************************************************************** 97 #define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable 98 #define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 99 #define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 100 #define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity 101 #define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 102 #define EPI_HB16CFG_WRWS_M 0x000000C0 // CS0n Write Wait States 103 #define EPI_HB16CFG_WRWS_0 0x00000000 // No wait states 104 #define EPI_HB16CFG_WRWS_1 0x00000040 // 1 wait state 105 #define EPI_HB16CFG_WRWS_2 0x00000080 // 2 wait states 106 #define EPI_HB16CFG_WRWS_3 0x000000C0 // 3 wait states 107 #define EPI_HB16CFG_RDWS_M 0x00000030 // CS0n Read Wait States 108 #define EPI_HB16CFG_RDWS_0 0x00000000 // No wait states 109 #define EPI_HB16CFG_RDWS_1 0x00000010 // 1 wait state 110 #define EPI_HB16CFG_RDWS_2 0x00000020 // 2 wait states 111 #define EPI_HB16CFG_RDWS_3 0x00000030 // 3 wait states 112 #define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration 113 #define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 114 #define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 115 #define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] 116 #define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] 117 #define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] 118 #define EPI_HB16CFG_MAXWAIT_S 8 119 120 //***************************************************************************** 121 // 122 // The following are defines for the bit fields in the EPI_O_GPCFG register. 123 // 124 //***************************************************************************** 125 #define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin 126 #define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated 127 #define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable 128 #define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin 129 #define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame 130 #define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count 131 #define EPI_GPCFG_RW 0x00200000 // Read and Write 132 #define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes 133 #define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads 134 #define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 135 #define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size 136 #define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address 137 #define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide 138 #define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size 139 // cannot be used with 24-bit data 140 #define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size 141 // cannot be used with data sizes 142 // other than 8 143 #define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus 144 #define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) 145 #define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) 146 #define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) 147 #define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) 148 #define EPI_GPCFG_FRMCNT_S 22 149 #define EPI_GPCFG_MAXWAIT_S 8 150 151 //***************************************************************************** 152 // 153 // The following are defines for the bit fields in the EPI_O_SDRAMCFG register. 154 // 155 //***************************************************************************** 156 #define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range 157 #define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz 158 #define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz 159 #define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz 160 #define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50 - 100 MHz 161 #define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter 162 #define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode 163 #define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM 164 #define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) 165 #define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) 166 #define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) 167 #define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) 168 #define EPI_SDRAMCFG_RFSH_S 16 169 170 //***************************************************************************** 171 // 172 // The following are defines for the bit fields in the EPI_O_HB8CFG register. 173 // 174 //***************************************************************************** 175 #define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable 176 #define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 177 #define EPI_HB8CFG_WRHIGH 0x00200000 // CS0n WRITE Strobe Polarity 178 #define EPI_HB8CFG_RDHIGH 0x00100000 // CS0n READ Strobe Polarity 179 #define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 180 #define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States 181 #define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states 182 #define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state 183 #define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states 184 #define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states 185 #define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States 186 #define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states 187 #define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state 188 #define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states 189 #define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states 190 #define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 191 #define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] 192 #define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] 193 #define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] 194 #define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] 195 #define EPI_HB8CFG_MAXWAIT_S 8 196 197 //***************************************************************************** 198 // 199 // The following are defines for the bit fields in the EPI_O_HB8CFG2 register. 200 // 201 //***************************************************************************** 202 #define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode 203 #define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate 204 #define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 205 #define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 206 #define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration 207 #define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 208 #define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 209 #define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 210 #define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 211 #define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 212 #define EPI_HB8CFG2_WRWS_0 0x00000000 // No wait states 213 #define EPI_HB8CFG2_WRWS_1 0x00000040 // 1 wait state 214 #define EPI_HB8CFG2_WRWS_2 0x00000080 // 2 wait states 215 #define EPI_HB8CFG2_WRWS_3 0x000000C0 // 3 wait states 216 #define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 217 #define EPI_HB8CFG2_RDWS_0 0x00000000 // No wait states 218 #define EPI_HB8CFG2_RDWS_1 0x00000010 // 1 wait state 219 #define EPI_HB8CFG2_RDWS_2 0x00000020 // 2 wait states 220 #define EPI_HB8CFG2_RDWS_3 0x00000030 // 3 wait states 221 222 //***************************************************************************** 223 // 224 // The following are defines for the bit fields in the EPI_O_HB16CFG2 register. 225 // 226 //***************************************************************************** 227 #define EPI_HB16CFG2_WORD 0x80000000 // Word Access Mode 228 #define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate 229 #define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 230 #define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 231 #define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration 232 #define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 233 #define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 234 #define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 235 #define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 236 #define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 237 #define EPI_HB16CFG2_WRWS_0 0x00000000 // No wait states 238 #define EPI_HB16CFG2_WRWS_1 0x00000040 // 1 wait state 239 #define EPI_HB16CFG2_WRWS_2 0x00000080 // 2 wait states 240 #define EPI_HB16CFG2_WRWS_3 0x000000C0 // 3 wait states 241 #define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 242 #define EPI_HB16CFG2_RDWS_0 0x00000000 // No wait states 243 #define EPI_HB16CFG2_RDWS_1 0x00000010 // 1 wait state 244 #define EPI_HB16CFG2_RDWS_2 0x00000020 // 2 wait states 245 #define EPI_HB16CFG2_RDWS_3 0x00000030 // 3 wait states 246 247 //***************************************************************************** 248 // 249 // The following are defines for the bit fields in the EPI_O_GPCFG2 register. 250 // 251 //***************************************************************************** 252 #define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode 253 254 //***************************************************************************** 255 // 256 // The following are defines for the bit fields in the EPI_O_ADDRMAP register. 257 // 258 //***************************************************************************** 259 #define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size 260 #define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: 261 // 0x00 to 0xFF 262 #define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: 263 // 0x0000 to 0xFFFF 264 #define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: 265 // 0x00.0000 to 0xFF.FFFF 266 #define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: 267 // 0x000.0000 to 0xFFF.FFFF 268 #define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address 269 #define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped 270 #define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 271 #define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 272 #define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size 273 #define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: 274 // 0x00 to 0xFF 275 #define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: 276 // 0x0000 to 0xFFFF 277 #define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: 278 // 0x00.0000 to 0xFF.FFFF 279 #define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: 280 // 0x000.0000 to 0xFFF.FFFF 281 #define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address 282 #define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped 283 #define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 284 #define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 285 286 //***************************************************************************** 287 // 288 // The following are defines for the bit fields in the EPI_O_RSIZE0 register. 289 // 290 //***************************************************************************** 291 #define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size 292 #define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) 293 #define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) 294 #define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) 295 296 //***************************************************************************** 297 // 298 // The following are defines for the bit fields in the EPI_O_RADDR0 register. 299 // 300 //***************************************************************************** 301 #define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address 302 #define EPI_RADDR0_ADDR_S 0 303 304 //***************************************************************************** 305 // 306 // The following are defines for the bit fields in the EPI_O_RPSTD0 register. 307 // 308 //***************************************************************************** 309 #define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count 310 #define EPI_RPSTD0_POSTCNT_S 0 311 312 //***************************************************************************** 313 // 314 // The following are defines for the bit fields in the EPI_O_RSIZE1 register. 315 // 316 //***************************************************************************** 317 #define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size 318 #define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) 319 #define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) 320 #define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) 321 322 //***************************************************************************** 323 // 324 // The following are defines for the bit fields in the EPI_O_RADDR1 register. 325 // 326 //***************************************************************************** 327 #define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address 328 #define EPI_RADDR1_ADDR_S 0 329 330 //***************************************************************************** 331 // 332 // The following are defines for the bit fields in the EPI_O_RPSTD1 register. 333 // 334 //***************************************************************************** 335 #define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count 336 #define EPI_RPSTD1_POSTCNT_S 0 337 338 //***************************************************************************** 339 // 340 // The following are defines for the bit fields in the EPI_O_STAT register. 341 // 342 //***************************************************************************** 343 #define EPI_STAT_CELOW 0x00000200 // Clock Enable Low 344 #define EPI_STAT_XFFULL 0x00000100 // External FIFO Full 345 #define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty 346 #define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence 347 #define EPI_STAT_WBUSY 0x00000020 // Write Busy 348 #define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy 349 #define EPI_STAT_ACTIVE 0x00000001 // Register Active 350 351 //***************************************************************************** 352 // 353 // The following are defines for the bit fields in the EPI_O_RFIFOCNT register. 354 // 355 //***************************************************************************** 356 #define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count 357 #define EPI_RFIFOCNT_COUNT_S 0 358 359 //***************************************************************************** 360 // 361 // The following are defines for the bit fields in the EPI_O_READFIFO register. 362 // 363 //***************************************************************************** 364 #define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data 365 #define EPI_READFIFO_DATA_S 0 366 367 //***************************************************************************** 368 // 369 // The following are defines for the bit fields in the EPI_O_READFIFO1 370 // register. 371 // 372 //***************************************************************************** 373 #define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data 374 #define EPI_READFIFO1_DATA_S 0 375 376 //***************************************************************************** 377 // 378 // The following are defines for the bit fields in the EPI_O_READFIFO2 379 // register. 380 // 381 //***************************************************************************** 382 #define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data 383 #define EPI_READFIFO2_DATA_S 0 384 385 //***************************************************************************** 386 // 387 // The following are defines for the bit fields in the EPI_O_READFIFO3 388 // register. 389 // 390 //***************************************************************************** 391 #define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data 392 #define EPI_READFIFO3_DATA_S 0 393 394 //***************************************************************************** 395 // 396 // The following are defines for the bit fields in the EPI_O_READFIFO4 397 // register. 398 // 399 //***************************************************************************** 400 #define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data 401 #define EPI_READFIFO4_DATA_S 0 402 403 //***************************************************************************** 404 // 405 // The following are defines for the bit fields in the EPI_O_READFIFO5 406 // register. 407 // 408 //***************************************************************************** 409 #define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data 410 #define EPI_READFIFO5_DATA_S 0 411 412 //***************************************************************************** 413 // 414 // The following are defines for the bit fields in the EPI_O_READFIFO6 415 // register. 416 // 417 //***************************************************************************** 418 #define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data 419 #define EPI_READFIFO6_DATA_S 0 420 421 //***************************************************************************** 422 // 423 // The following are defines for the bit fields in the EPI_O_READFIFO7 424 // register. 425 // 426 //***************************************************************************** 427 #define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data 428 #define EPI_READFIFO7_DATA_S 0 429 430 //***************************************************************************** 431 // 432 // The following are defines for the bit fields in the EPI_O_FIFOLVL register. 433 // 434 //***************************************************************************** 435 #define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error 436 #define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error 437 #define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO 438 #define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Trigger when there are 1 to 4 439 // spaces available in the WFIFO 440 #define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are 1 to 3 441 // spaces available in the WFIFO 442 #define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are 1 to 2 443 // spaces available in the WFIFO 444 #define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space 445 // available in the WFIFO 446 #define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO 447 #define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty 448 #define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more 449 // entries in the NBRFIFO 450 #define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more 451 // entries in the NBRFIFO 452 #define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more 453 // entries in the NBRFIFO 454 #define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more 455 // entries in the NBRFIFO 456 #define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more 457 // entries in the NBRFIFO 458 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries 459 // in the NBRFIFO 460 461 //***************************************************************************** 462 // 463 // The following are defines for the bit fields in the EPI_O_WFIFOCNT register. 464 // 465 //***************************************************************************** 466 #define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions 467 #define EPI_WFIFOCNT_WTAV_S 0 468 469 //***************************************************************************** 470 // 471 // The following are defines for the bit fields in the EPI_O_IM register. 472 // 473 //***************************************************************************** 474 #define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask 475 #define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask 476 #define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask 477 478 //***************************************************************************** 479 // 480 // The following are defines for the bit fields in the EPI_O_RIS register. 481 // 482 //***************************************************************************** 483 #define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status 484 #define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status 485 #define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status 486 487 //***************************************************************************** 488 // 489 // The following are defines for the bit fields in the EPI_O_MIS register. 490 // 491 //***************************************************************************** 492 #define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status 493 #define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status 494 #define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status 495 496 //***************************************************************************** 497 // 498 // The following are defines for the bit fields in the EPI_O_EISC register. 499 // 500 //***************************************************************************** 501 #define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error 502 #define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error 503 #define EPI_EISC_TOUT 0x00000001 // Timeout Error 504 505 //***************************************************************************** 506 // 507 // The following definitions are deprecated. 508 // 509 //***************************************************************************** 510 #ifndef DEPRECATED 511 512 //***************************************************************************** 513 // 514 // The following are deprecated defines for the bit fields in the EPI_O_BAUD 515 // register. 516 // 517 //***************************************************************************** 518 #define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter 519 #define EPI_BAUD_COUNT_S 0 520 521 #endif 522 523 #endif // __HW_EPI_H__ 524