1 //***************************************************************************** 2 // 3 // hw_ethernet.h - Macros used when accessing the Ethernet hardware. 4 // 5 // Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_ETHERNET_H__ 26 #define __HW_ETHERNET_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the Ethernet MAC register offsets. 31 // 32 //***************************************************************************** 33 #define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt 34 // Status/Acknowledge 35 #define MAC_O_IACK 0x00000000 // Ethernet MAC Raw Interrupt 36 // Status/Acknowledge 37 #define MAC_O_IM 0x00000004 // Ethernet MAC Interrupt Mask 38 #define MAC_O_RCTL 0x00000008 // Ethernet MAC Receive Control 39 #define MAC_O_TCTL 0x0000000C // Ethernet MAC Transmit Control 40 #define MAC_O_DATA 0x00000010 // Ethernet MAC Data 41 #define MAC_O_IA0 0x00000014 // Ethernet MAC Individual Address 42 // 0 43 #define MAC_O_IA1 0x00000018 // Ethernet MAC Individual Address 44 // 1 45 #define MAC_O_THR 0x0000001C // Ethernet MAC Threshold 46 #define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control 47 #define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider 48 #define MAC_O_MADD 0x00000028 // Ethernet MAC Management Address 49 #define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit 50 // Data 51 #define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive 52 // Data 53 #define MAC_O_NP 0x00000034 // Ethernet MAC Number of Packets 54 #define MAC_O_TR 0x00000038 // Ethernet MAC Transmission 55 // Request 56 #define MAC_O_TS 0x0000003C // Ethernet MAC Timer Support 57 #define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding 58 #define MAC_O_MDIX 0x00000044 // Ethernet PHY MDIX 59 60 //***************************************************************************** 61 // 62 // The following are defines for the bit fields in the MAC_O_RIS register. 63 // 64 //***************************************************************************** 65 #define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt 66 #define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete 67 #define MAC_RIS_RXER 0x00000010 // Receive Error 68 #define MAC_RIS_FOV 0x00000008 // FIFO Overrun 69 #define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty 70 #define MAC_RIS_TXER 0x00000002 // Transmit Error 71 #define MAC_RIS_RXINT 0x00000001 // Packet Received 72 73 //***************************************************************************** 74 // 75 // The following are defines for the bit fields in the MAC_O_IACK register. 76 // 77 //***************************************************************************** 78 #define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt 79 #define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete 80 #define MAC_IACK_RXER 0x00000010 // Clear Receive Error 81 #define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun 82 #define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty 83 #define MAC_IACK_TXER 0x00000002 // Clear Transmit Error 84 #define MAC_IACK_RXINT 0x00000001 // Clear Packet Received 85 86 //***************************************************************************** 87 // 88 // The following are defines for the bit fields in the MAC_O_IM register. 89 // 90 //***************************************************************************** 91 #define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt 92 #define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete 93 #define MAC_IM_RXERM 0x00000010 // Mask Receive Error 94 #define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun 95 #define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty 96 #define MAC_IM_TXERM 0x00000002 // Mask Transmit Error 97 #define MAC_IM_RXINTM 0x00000001 // Mask Packet Received 98 99 //***************************************************************************** 100 // 101 // The following are defines for the bit fields in the MAC_O_RCTL register. 102 // 103 //***************************************************************************** 104 #define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO 105 #define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC 106 #define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode 107 #define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames 108 #define MAC_RCTL_RXEN 0x00000001 // Enable Receiver 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the MAC_O_TCTL register. 113 // 114 //***************************************************************************** 115 #define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode 116 #define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation 117 #define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding 118 #define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter 119 120 //***************************************************************************** 121 // 122 // The following are defines for the bit fields in the MAC_O_DATA register. 123 // 124 //***************************************************************************** 125 #define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data 126 #define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data 127 #define MAC_DATA_RXDATA_S 0 128 #define MAC_DATA_TXDATA_S 0 129 130 //***************************************************************************** 131 // 132 // The following are defines for the bit fields in the MAC_O_IA0 register. 133 // 134 //***************************************************************************** 135 #define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4 136 #define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3 137 #define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2 138 #define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1 139 #define MAC_IA0_MACOCT4_S 24 140 #define MAC_IA0_MACOCT3_S 16 141 #define MAC_IA0_MACOCT2_S 8 142 #define MAC_IA0_MACOCT1_S 0 143 144 //***************************************************************************** 145 // 146 // The following are defines for the bit fields in the MAC_O_IA1 register. 147 // 148 //***************************************************************************** 149 #define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6 150 #define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5 151 #define MAC_IA1_MACOCT6_S 8 152 #define MAC_IA1_MACOCT5_S 0 153 154 //***************************************************************************** 155 // 156 // The following are defines for the bit fields in the MAC_O_THR register. 157 // 158 //***************************************************************************** 159 #define MAC_THR_THRESH_M 0x0000003F // Threshold Value 160 #define MAC_THR_THRESH_S 0 161 162 //***************************************************************************** 163 // 164 // The following are defines for the bit fields in the MAC_O_MCTL register. 165 // 166 //***************************************************************************** 167 #define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address 168 #define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type 169 #define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable 170 #define MAC_MCTL_REGADR_S 3 171 172 //***************************************************************************** 173 // 174 // The following are defines for the bit fields in the MAC_O_MDV register. 175 // 176 //***************************************************************************** 177 #define MAC_MDV_DIV_M 0x000000FF // Clock Divider 178 #define MAC_MDV_DIV_S 0 179 180 //***************************************************************************** 181 // 182 // The following are defines for the bit fields in the MAC_O_MADD register. 183 // 184 //***************************************************************************** 185 #define MAC_MADD_PHYADR_M 0x0000001F // PHY Address 186 #define MAC_MADD_PHYADR_S 0 187 188 //***************************************************************************** 189 // 190 // The following are defines for the bit fields in the MAC_O_MTXD register. 191 // 192 //***************************************************************************** 193 #define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data 194 #define MAC_MTXD_MDTX_S 0 195 196 //***************************************************************************** 197 // 198 // The following are defines for the bit fields in the MAC_O_MRXD register. 199 // 200 //***************************************************************************** 201 #define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data 202 #define MAC_MRXD_MDRX_S 0 203 204 //***************************************************************************** 205 // 206 // The following are defines for the bit fields in the MAC_O_NP register. 207 // 208 //***************************************************************************** 209 #define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive 210 // FIFO 211 #define MAC_NP_NPR_S 0 212 213 //***************************************************************************** 214 // 215 // The following are defines for the bit fields in the MAC_O_TR register. 216 // 217 //***************************************************************************** 218 #define MAC_TR_NEWTX 0x00000001 // New Transmission 219 220 //***************************************************************************** 221 // 222 // The following are defines for the bit fields in the MAC_O_TS register. 223 // 224 //***************************************************************************** 225 #define MAC_TS_TSEN 0x00000001 // Time Stamp Enable 226 227 //***************************************************************************** 228 // 229 // The following are defines for the bit fields in the MAC_O_LED register. 230 // 231 //***************************************************************************** 232 #define MAC_LED_LED1_M 0x00000F00 // LED1 Source 233 #define MAC_LED_LED1_LINK 0x00000000 // Link OK 234 #define MAC_LED_LED1_RXTX 0x00000100 // RX or TX Activity (Default LED1) 235 #define MAC_LED_LED1_100 0x00000500 // 100BASE-TX mode 236 #define MAC_LED_LED1_10 0x00000600 // 10BASE-T mode 237 #define MAC_LED_LED1_DUPLEX 0x00000700 // Full-Duplex 238 #define MAC_LED_LED1_LINKACT 0x00000800 // Link OK & Blink=RX or TX 239 // Activity 240 #define MAC_LED_LED0_M 0x0000000F // LED0 Source 241 #define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0) 242 #define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity 243 #define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode 244 #define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode 245 #define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex 246 #define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX 247 // Activity 248 249 //***************************************************************************** 250 // 251 // The following are defines for the bit fields in the MAC_O_MDIX register. 252 // 253 //***************************************************************************** 254 #define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable 255 256 //***************************************************************************** 257 // 258 // The following are defines for the Ethernet Controller PHY registers. 259 // 260 //***************************************************************************** 261 #define PHY_MR0 0x00000000 // Ethernet PHY Management Register 262 // 0 - Control 263 #define PHY_MR1 0x00000001 // Ethernet PHY Management Register 264 // 1 - Status 265 #define PHY_MR2 0x00000002 // Ethernet PHY Management Register 266 // 2 - PHY Identifier 1 267 #define PHY_MR3 0x00000003 // Ethernet PHY Management Register 268 // 3 - PHY Identifier 2 269 #define PHY_MR4 0x00000004 // Ethernet PHY Management Register 270 // 4 - Auto-Negotiation 271 // Advertisement 272 #define PHY_MR5 0x00000005 // Ethernet PHY Management Register 273 // 5 - Auto-Negotiation Link 274 // Partner Base Page Ability 275 #define PHY_MR6 0x00000006 // Ethernet PHY Management Register 276 // 6 - Auto-Negotiation Expansion 277 #define PHY_MR16 0x00000010 // Ethernet PHY Management Register 278 // 16 - Vendor-Specific 279 #define PHY_MR17 0x00000011 // Ethernet PHY Management Register 280 // 17 - Mode Control/Status 281 #define PHY_MR18 0x00000012 // Ethernet PHY Management Register 282 // 18 - Diagnostic 283 #define PHY_MR19 0x00000013 // Ethernet PHY Management Register 284 // 19 - Transceiver Control 285 #define PHY_MR23 0x00000017 // Ethernet PHY Management Register 286 // 23 - LED Configuration 287 #define PHY_MR24 0x00000018 // Ethernet PHY Management Register 288 // 24 -MDI/MDIX Control 289 #define PHY_MR27 0x0000001B // Ethernet PHY Management Register 290 // 27 - Special Control/Status 291 #define PHY_MR29 0x0000001D // Ethernet PHY Management Register 292 // 29 - Interrupt Status 293 #define PHY_MR30 0x0000001E // Ethernet PHY Management Register 294 // 30 - Interrupt Mask 295 #define PHY_MR31 0x0000001F // Ethernet PHY Management Register 296 // 31 - PHY Special Control/Status 297 298 //***************************************************************************** 299 // 300 // The following are defines for the bit fields in the PHY_MR0 register. 301 // 302 //***************************************************************************** 303 #define PHY_MR0_RESET 0x00008000 // Reset Registers 304 #define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode 305 #define PHY_MR0_SPEEDSL 0x00002000 // Speed Select 306 #define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable 307 #define PHY_MR0_PWRDN 0x00000800 // Power Down 308 #define PHY_MR0_ISO 0x00000400 // Isolate 309 #define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation 310 #define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode 311 #define PHY_MR0_COLT 0x00000080 // Collision Test 312 313 //***************************************************************************** 314 // 315 // The following are defines for the bit fields in the PHY_MR1 register. 316 // 317 //***************************************************************************** 318 #define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode 319 #define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode 320 #define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode 321 #define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode 322 #define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble 323 // Suppressed 324 #define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete 325 #define PHY_MR1_RFAULT 0x00000010 // Remote Fault 326 #define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation 327 #define PHY_MR1_LINK 0x00000004 // Link Made 328 #define PHY_MR1_JAB 0x00000002 // Jabber Condition 329 #define PHY_MR1_EXTD 0x00000001 // Extended Capabilities 330 331 //***************************************************************************** 332 // 333 // The following are defines for the bit fields in the PHY_MR2 register. 334 // 335 //***************************************************************************** 336 #define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique 337 // Identifier[21:6] 338 #define PHY_MR2_OUI_S 0 339 340 //***************************************************************************** 341 // 342 // The following are defines for the bit fields in the PHY_MR3 register. 343 // 344 //***************************************************************************** 345 #define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique 346 // Identifier[5:0] 347 #define PHY_MR3_MN_M 0x000003F0 // Model Number 348 #define PHY_MR3_RN_M 0x0000000F // Revision Number 349 #define PHY_MR3_OUI_S 10 350 #define PHY_MR3_MN_S 4 351 #define PHY_MR3_RN_S 0 352 353 //***************************************************************************** 354 // 355 // The following are defines for the bit fields in the PHY_MR4 register. 356 // 357 //***************************************************************************** 358 #define PHY_MR4_NP 0x00008000 // Next Page 359 #define PHY_MR4_RF 0x00002000 // Remote Fault 360 #define PHY_MR4_A3 0x00000100 // Technology Ability Field [3] 361 #define PHY_MR4_A2 0x00000080 // Technology Ability Field [2] 362 #define PHY_MR4_A1 0x00000040 // Technology Ability Field [1] 363 #define PHY_MR4_A0 0x00000020 // Technology Ability Field [0] 364 #define PHY_MR4_S_M 0x0000001F // Selector Field 365 #define PHY_MR4_S_S 0 366 367 //***************************************************************************** 368 // 369 // The following are defines for the bit fields in the PHY_MR5 register. 370 // 371 //***************************************************************************** 372 #define PHY_MR5_NP 0x00008000 // Next Page 373 #define PHY_MR5_ACK 0x00004000 // Acknowledge 374 #define PHY_MR5_RF 0x00002000 // Remote Fault 375 #define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field 376 #define PHY_MR5_S_M 0x0000001F // Selector Field 377 #define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3 378 #define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T 379 #define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5 380 #define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394 381 #define PHY_MR5_A_S 5 382 383 //***************************************************************************** 384 // 385 // The following are defines for the bit fields in the PHY_MR6 register. 386 // 387 //***************************************************************************** 388 #define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault 389 #define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able 390 #define PHY_MR6_PRX 0x00000002 // New Page Received 391 #define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation 392 // Able 393 394 //***************************************************************************** 395 // 396 // The following are defines for the bit fields in the PHY_MR16 register. 397 // 398 //***************************************************************************** 399 #define PHY_MR16_RPTR 0x00008000 // Repeater Mode 400 #define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity 401 #define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode 402 #define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing 403 #define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode 404 #define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier 405 #define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable 406 #define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity 407 #define PHY_MR16_PCSBP 0x00000002 // PCS Bypass 408 #define PHY_MR16_RXCC 0x00000001 // Receive Clock Control 409 #define PHY_MR16_SR_S 6 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the PHY_MR17 register. 414 // 415 //***************************************************************************** 416 #define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable 417 #define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable 418 #define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable 419 #define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down 420 #define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable 421 #define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault 422 // Interrupt Enable 423 #define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable 424 #define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable 425 #define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt 426 // Enable 427 #define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable 428 #define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete 429 // Interrupt Enable 430 #define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode 431 #define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt 432 #define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt 433 #define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt 434 #define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault 435 // Interrupt 436 #define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt 437 #define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt 438 #define PHY_MR17_FGLS 0x00000004 // Force Good Link Status 439 #define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt 440 #define PHY_MR17_ENON 0x00000002 // Energy On 441 #define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete 442 // Interrupt 443 444 //***************************************************************************** 445 // 446 // The following are defines for the bit fields in the PHY_MR18 register. 447 // 448 //***************************************************************************** 449 #define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure 450 #define PHY_MR18_DPLX 0x00000800 // Duplex Mode 451 #define PHY_MR18_RATE 0x00000400 // Rate 452 #define PHY_MR18_RXSD 0x00000200 // Receive Detection 453 #define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock 454 455 //***************************************************************************** 456 // 457 // The following are defines for the bit fields in the PHY_MR19 register. 458 // 459 //***************************************************************************** 460 #define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection 461 #define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion 462 // loss 463 #define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion 464 // loss 465 #define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion 466 // loss 467 #define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion 468 // loss 469 470 //***************************************************************************** 471 // 472 // The following are defines for the bit fields in the PHY_MR23 register. 473 // 474 //***************************************************************************** 475 #define PHY_MR23_LED1_M 0x000000F0 // LED1 Source 476 #define PHY_MR23_LED1_LINK 0x00000000 // Link OK 477 #define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1) 478 #define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode 479 #define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode 480 #define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex 481 #define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX 482 // Activity 483 #define PHY_MR23_LED0_M 0x0000000F // LED0 Source 484 #define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0) 485 #define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity 486 #define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode 487 #define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode 488 #define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex 489 #define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX 490 // Activity 491 492 //***************************************************************************** 493 // 494 // The following are defines for the bit fields in the PHY_MR24 register. 495 // 496 //***************************************************************************** 497 #define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode 498 #define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable 499 #define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration 500 #define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete 501 #define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed 502 #define PHY_MR24_MDIX_SD_S 0 503 504 //***************************************************************************** 505 // 506 // The following are defines for the bit fields in the PHY_MR27 register. 507 // 508 //***************************************************************************** 509 #define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T 510 511 //***************************************************************************** 512 // 513 // The following are defines for the bit fields in the PHY_MR29 register. 514 // 515 //***************************************************************************** 516 #define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt 517 #define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete 518 // Interrupt 519 #define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt 520 #define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt 521 #define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge 522 #define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault 523 #define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received 524 525 //***************************************************************************** 526 // 527 // The following are defines for the bit fields in the PHY_MR30 register. 528 // 529 //***************************************************************************** 530 #define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled 531 #define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete 532 // Interrupt Enabled 533 #define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled 534 #define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled 535 #define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge 536 // Enabled 537 #define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault Enabled 538 #define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received 539 // Enabled 540 541 //***************************************************************************** 542 // 543 // The following are defines for the bit fields in the PHY_MR31 register. 544 // 545 //***************************************************************************** 546 #define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done 547 #define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value 548 #define PHY_MR31_SPEED_10HD 0x00000004 // 10BASE-T half duplex 549 #define PHY_MR31_SPEED_100HD 0x00000008 // 100BASE-T half duplex 550 #define PHY_MR31_SPEED_10FD 0x00000014 // 10BASE-T full duplex 551 #define PHY_MR31_SPEED_100FD 0x00000018 // 100BASE-T full duplex 552 #define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable 553 554 //***************************************************************************** 555 // 556 // The following definitions are deprecated. 557 // 558 //***************************************************************************** 559 #ifndef DEPRECATED 560 561 //***************************************************************************** 562 // 563 // The following are deprecated defines for the Ethernet MAC register offsets. 564 // 565 //***************************************************************************** 566 #define MAC_O_IS 0x00000000 // Interrupt Status Register 567 568 //***************************************************************************** 569 // 570 // The following are deprecated defines for the bit fields in the MAC_O_IS 571 // register. 572 // 573 //***************************************************************************** 574 #define MAC_IS_PHYINT 0x00000040 // PHY Interrupt 575 #define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete 576 #define MAC_IS_RXER 0x00000010 // RX Error 577 #define MAC_IS_FOV 0x00000008 // RX FIFO Overrun 578 #define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy 579 #define MAC_IS_TXER 0x00000002 // TX Error 580 #define MAC_IS_RXINT 0x00000001 // RX Packet Available 581 582 //***************************************************************************** 583 // 584 // The following are deprecated defines for the bit fields in the MAC_O_IA0 585 // register. 586 // 587 //***************************************************************************** 588 #define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address 589 #define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address 590 #define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address 591 #define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address 592 593 //***************************************************************************** 594 // 595 // The following are deprecated defines for the bit fields in the MAC_O_IA1 596 // register. 597 // 598 //***************************************************************************** 599 #define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address 600 #define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address 601 602 //***************************************************************************** 603 // 604 // The following are deprecated defines for the bit fields in the MAC_O_THR 605 // register. 606 // 607 //***************************************************************************** 608 #define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value 609 610 //***************************************************************************** 611 // 612 // The following are deprecated defines for the bit fields in the MAC_O_MCTL 613 // register. 614 // 615 //***************************************************************************** 616 #define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction 617 618 //***************************************************************************** 619 // 620 // The following are deprecated defines for the bit fields in the MAC_O_MDV 621 // register. 622 // 623 //***************************************************************************** 624 #define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX 625 626 //***************************************************************************** 627 // 628 // The following are deprecated defines for the bit fields in the MAC_O_MTXD 629 // register. 630 // 631 //***************************************************************************** 632 #define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction 633 634 //***************************************************************************** 635 // 636 // The following are deprecated defines for the bit fields in the MAC_O_MRXD 637 // register. 638 // 639 //***************************************************************************** 640 #define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans 641 642 //***************************************************************************** 643 // 644 // The following are deprecated defines for the bit fields in the MAC_O_NP 645 // register. 646 // 647 //***************************************************************************** 648 #define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO 649 650 //***************************************************************************** 651 // 652 // The following are deprecated defines for the bit fields in the PHY_MR23 653 // register. 654 // 655 //***************************************************************************** 656 #define PHY_MR23_LED1_TX 0x00000020 // TX Activity 657 #define PHY_MR23_LED1_RX 0x00000030 // RX Activity 658 #define PHY_MR23_LED1_COL 0x00000040 // Collision 659 #define PHY_MR23_LED0_TX 0x00000002 // TX Activity 660 #define PHY_MR23_LED0_RX 0x00000003 // RX Activity 661 #define PHY_MR23_LED0_COL 0x00000004 // Collision 662 663 //***************************************************************************** 664 // 665 // The following are deprecated defines for the reset values of the MAC 666 // registers. 667 // 668 //***************************************************************************** 669 #define MAC_RV_MDV 0x00000080 670 #define MAC_RV_IM 0x0000007F 671 #define MAC_RV_THR 0x0000003F 672 #define MAC_RV_RCTL 0x00000008 673 #define MAC_RV_IA0 0x00000000 674 #define MAC_RV_TCTL 0x00000000 675 #define MAC_RV_DATA 0x00000000 676 #define MAC_RV_MRXD 0x00000000 677 #define MAC_RV_TR 0x00000000 678 #define MAC_RV_IS 0x00000000 679 #define MAC_RV_NP 0x00000000 680 #define MAC_RV_MCTL 0x00000000 681 #define MAC_RV_MTXD 0x00000000 682 #define MAC_RV_IA1 0x00000000 683 #define MAC_RV_IACK 0x00000000 684 #define MAC_RV_MADD 0x00000000 685 686 #endif 687 688 #endif // __HW_ETHERNET_H__ 689