1 //***************************************************************************** 2 // 3 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_I2C_H__ 26 #define __HW_I2C_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the I2C register offsets. 31 // 32 //***************************************************************************** 33 #define I2C_O_MSA 0x00000000 // I2C Master Slave Address 34 #define I2C_O_SOAR 0x00000000 // I2C Slave Own Address 35 #define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status 36 #define I2C_O_MCS 0x00000004 // I2C Master Control/Status 37 #define I2C_O_SDR 0x00000008 // I2C Slave Data 38 #define I2C_O_MDR 0x00000008 // I2C Master Data 39 #define I2C_O_MTPR 0x0000000C // I2C Master Timer Period 40 #define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask 41 #define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status 42 #define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask 43 #define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status 44 #define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt 45 // Status 46 #define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear 47 #define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt 48 // Status 49 #define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear 50 #define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2 51 #define I2C_O_MCR 0x00000020 // I2C Master Configuration 52 #define I2C_O_SACKCTL 0x00000020 // I2C ACK Control 53 #define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout 54 // Count 55 #define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor 56 #define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties 57 58 //***************************************************************************** 59 // 60 // The following are defines for the bit fields in the I2C_O_MSA register. 61 // 62 //***************************************************************************** 63 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address 64 #define I2C_MSA_RS 0x00000001 // Receive not send 65 #define I2C_MSA_SA_S 1 66 67 //***************************************************************************** 68 // 69 // The following are defines for the bit fields in the I2C_O_SOAR register. 70 // 71 //***************************************************************************** 72 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address 73 #define I2C_SOAR_OAR_S 0 74 75 //***************************************************************************** 76 // 77 // The following are defines for the bit fields in the I2C_O_SCSR register. 78 // 79 //***************************************************************************** 80 #define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write 81 #define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status 82 #define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched 83 #define I2C_SCSR_FBR 0x00000004 // First Byte Received 84 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request 85 #define I2C_SCSR_DA 0x00000001 // Device Active 86 #define I2C_SCSR_RREQ 0x00000001 // Receive Request 87 88 //***************************************************************************** 89 // 90 // The following are defines for the bit fields in the I2C_O_MCS register. 91 // 92 //***************************************************************************** 93 #define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error 94 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy 95 #define I2C_MCS_IDLE 0x00000020 // I2C Idle 96 #define I2C_MCS_QCMD 0x00000020 // Quick Command 97 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost 98 #define I2C_MCS_HS 0x00000010 // High-Speed Enable 99 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable 100 #define I2C_MCS_DATACK 0x00000008 // Acknowledge Data 101 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address 102 #define I2C_MCS_STOP 0x00000004 // Generate STOP 103 #define I2C_MCS_START 0x00000002 // Generate START 104 #define I2C_MCS_ERROR 0x00000002 // Error 105 #define I2C_MCS_RUN 0x00000001 // I2C Master Enable 106 #define I2C_MCS_BUSY 0x00000001 // I2C Busy 107 108 //***************************************************************************** 109 // 110 // The following are defines for the bit fields in the I2C_O_SDR register. 111 // 112 //***************************************************************************** 113 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer 114 #define I2C_SDR_DATA_S 0 115 116 //***************************************************************************** 117 // 118 // The following are defines for the bit fields in the I2C_O_MDR register. 119 // 120 //***************************************************************************** 121 #define I2C_MDR_DATA_M 0x000000FF // Data Transferred 122 #define I2C_MDR_DATA_S 0 123 124 //***************************************************************************** 125 // 126 // The following are defines for the bit fields in the I2C_O_MTPR register. 127 // 128 //***************************************************************************** 129 #define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period 130 #define I2C_MTPR_TPR_S 0 131 132 //***************************************************************************** 133 // 134 // The following are defines for the bit fields in the I2C_O_SIMR register. 135 // 136 //***************************************************************************** 137 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask 138 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask 139 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask 140 141 //***************************************************************************** 142 // 143 // The following are defines for the bit fields in the I2C_O_SRIS register. 144 // 145 //***************************************************************************** 146 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt 147 // Status 148 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt 149 // Status 150 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status 151 152 //***************************************************************************** 153 // 154 // The following are defines for the bit fields in the I2C_O_MIMR register. 155 // 156 //***************************************************************************** 157 #define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask 158 #define I2C_MIMR_IM 0x00000001 // Interrupt Mask 159 160 //***************************************************************************** 161 // 162 // The following are defines for the bit fields in the I2C_O_MRIS register. 163 // 164 //***************************************************************************** 165 #define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt 166 // Status 167 #define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status 168 169 //***************************************************************************** 170 // 171 // The following are defines for the bit fields in the I2C_O_SMIS register. 172 // 173 //***************************************************************************** 174 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt 175 // Status 176 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt 177 // Status 178 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status 179 180 //***************************************************************************** 181 // 182 // The following are defines for the bit fields in the I2C_O_SICR register. 183 // 184 //***************************************************************************** 185 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear 186 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear 187 #define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear 188 189 //***************************************************************************** 190 // 191 // The following are defines for the bit fields in the I2C_O_MMIS register. 192 // 193 //***************************************************************************** 194 #define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt 195 // Status 196 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status 197 198 //***************************************************************************** 199 // 200 // The following are defines for the bit fields in the I2C_O_MICR register. 201 // 202 //***************************************************************************** 203 #define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear 204 #define I2C_MICR_IC 0x00000001 // Interrupt Clear 205 206 //***************************************************************************** 207 // 208 // The following are defines for the bit fields in the I2C_O_SOAR2 register. 209 // 210 //***************************************************************************** 211 #define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable 212 #define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 213 #define I2C_SOAR2_OAR2_S 0 214 215 //***************************************************************************** 216 // 217 // The following are defines for the bit fields in the I2C_O_MCR register. 218 // 219 //***************************************************************************** 220 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable 221 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable 222 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback 223 224 //***************************************************************************** 225 // 226 // The following are defines for the bit fields in the I2C_O_SACKCTL register. 227 // 228 //***************************************************************************** 229 #define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value 230 #define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable 231 232 //***************************************************************************** 233 // 234 // The following are defines for the bit fields in the I2C_O_MCLKOCNT register. 235 // 236 //***************************************************************************** 237 #define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count 238 #define I2C_MCLKOCNT_CNTL_S 0 239 240 //***************************************************************************** 241 // 242 // The following are defines for the bit fields in the I2C_O_MBMON register. 243 // 244 //***************************************************************************** 245 #define I2C_MBMON_SDA 0x00000002 // I2C SDA Status 246 #define I2C_MBMON_SCL 0x00000001 // I2C SCL Status 247 248 //***************************************************************************** 249 // 250 // The following are defines for the bit fields in the I2C_O_PP register. 251 // 252 //***************************************************************************** 253 #define I2C_PP_HS 0x00000001 // High-Speed Capable 254 255 //***************************************************************************** 256 // 257 // The following definitions are deprecated. 258 // 259 //***************************************************************************** 260 #ifndef DEPRECATED 261 262 //***************************************************************************** 263 // 264 // The following are deprecated defines for the I2C register offsets. 265 // 266 //***************************************************************************** 267 #define I2C_O_SLAVE 0x00000800 // Offset from master to slave 268 269 //***************************************************************************** 270 // 271 // The following are deprecated defines for the bit fields in the I2C_O_SIMR 272 // register. 273 // 274 //***************************************************************************** 275 #define I2C_SIMR_IM 0x00000001 // Interrupt Mask 276 277 //***************************************************************************** 278 // 279 // The following are deprecated defines for the bit fields in the I2C_O_SRIS 280 // register. 281 // 282 //***************************************************************************** 283 #define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status 284 285 //***************************************************************************** 286 // 287 // The following are deprecated defines for the bit fields in the I2C_O_SMIS 288 // register. 289 // 290 //***************************************************************************** 291 #define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status 292 293 //***************************************************************************** 294 // 295 // The following are deprecated defines for the bit fields in the I2C_O_SICR 296 // register. 297 // 298 //***************************************************************************** 299 #define I2C_SICR_IC 0x00000001 // Clear Interrupt 300 301 //***************************************************************************** 302 // 303 // The following are deprecated defines for the I2C master register offsets. 304 // 305 //***************************************************************************** 306 #define I2C_MASTER_O_SA 0x00000000 // Slave address register 307 #define I2C_MASTER_O_CS 0x00000004 // Control and Status register 308 #define I2C_MASTER_O_DR 0x00000008 // Data register 309 #define I2C_MASTER_O_TPR 0x0000000C // Timer period register 310 #define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register 311 #define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register 312 #define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg 313 #define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register 314 #define I2C_MASTER_O_CR 0x00000020 // Configuration register 315 316 //***************************************************************************** 317 // 318 // The following are deprecated defines for the I2C slave register offsets. 319 // 320 //***************************************************************************** 321 #define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register 322 #define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg 323 #define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register 324 #define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register 325 #define I2C_SLAVE_O_DR 0x00000008 // Data register 326 #define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register 327 #define I2C_SLAVE_O_OAR 0x00000000 // Own address register 328 329 //***************************************************************************** 330 // 331 // The following are deprecated defines for the bit fields in the I2C master 332 // slave address register. 333 // 334 //***************************************************************************** 335 #define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address 336 #define I2C_MASTER_SA_RS 0x00000001 // Receive/send 337 #define I2C_MASTER_SA_SA_SHIFT 1 338 339 //***************************************************************************** 340 // 341 // The following are deprecated defines for the bit fields in the I2C Master 342 // Control and Status register. 343 // 344 //***************************************************************************** 345 #define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy 346 #define I2C_MASTER_CS_IDLE 0x00000020 // Idle 347 #define I2C_MASTER_CS_ERR_MASK 0x0000001C 348 #define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data 349 #define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred 350 #define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged 351 #define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged 352 #define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration 353 #define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde 354 #define I2C_MASTER_CS_STOP 0x00000004 // Stop 355 #define I2C_MASTER_CS_START 0x00000002 // Start 356 #define I2C_MASTER_CS_RUN 0x00000001 // Run 357 358 //***************************************************************************** 359 // 360 // The following are deprecated defines for the values used in determining the 361 // contents of the I2C Master Timer Period register. 362 // 363 //***************************************************************************** 364 #define I2C_SCL_FAST 400000 // SCL fast frequency 365 #define I2C_SCL_STANDARD 100000 // SCL standard frequency 366 #define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period 367 #define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period 368 #define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) 369 370 //***************************************************************************** 371 // 372 // The following are deprecated defines for the bit fields in the I2C Master 373 // Interrupt Mask register. 374 // 375 //***************************************************************************** 376 #define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask 377 378 //***************************************************************************** 379 // 380 // The following are deprecated defines for the bit fields in the I2C Master 381 // Raw Interrupt Status register. 382 // 383 //***************************************************************************** 384 #define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status 385 386 //***************************************************************************** 387 // 388 // The following are deprecated defines for the bit fields in the I2C Master 389 // Masked Interrupt Status register. 390 // 391 //***************************************************************************** 392 #define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status 393 394 //***************************************************************************** 395 // 396 // The following are deprecated defines for the bit fields in the I2C Master 397 // Interrupt Clear register. 398 // 399 //***************************************************************************** 400 #define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear 401 402 //***************************************************************************** 403 // 404 // The following are deprecated defines for the bit fields in the I2C Master 405 // Configuration register. 406 // 407 //***************************************************************************** 408 #define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable 409 #define I2C_MASTER_CR_MFE 0x00000010 // Master function enable 410 #define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable 411 412 //***************************************************************************** 413 // 414 // The following are deprecated defines for the bit fields in the I2C Slave Own 415 // Address register. 416 // 417 //***************************************************************************** 418 #define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address 419 420 //***************************************************************************** 421 // 422 // The following are deprecated defines for the bit fields in the I2C Slave 423 // Control/Status register. 424 // 425 //***************************************************************************** 426 #define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master 427 #define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received 428 #define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device 429 #define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master 430 431 //***************************************************************************** 432 // 433 // The following are deprecated defines for the bit fields in the I2C Slave 434 // Interrupt Mask register. 435 // 436 //***************************************************************************** 437 #define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask 438 439 //***************************************************************************** 440 // 441 // The following are deprecated defines for the bit fields in the I2C Slave Raw 442 // Interrupt Status register. 443 // 444 //***************************************************************************** 445 #define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status 446 447 //***************************************************************************** 448 // 449 // The following are deprecated defines for the bit fields in the I2C Slave 450 // Masked Interrupt Status register. 451 // 452 //***************************************************************************** 453 #define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status 454 455 //***************************************************************************** 456 // 457 // The following are deprecated defines for the bit fields in the I2C Slave 458 // Interrupt Clear register. 459 // 460 //***************************************************************************** 461 #define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear 462 463 #endif 464 465 #endif // __HW_I2C_H__ 466